Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2, 3 and 7 are objected to because of the following informalities: in claims 2 and 3, line 3, "fist" should read "first". In claim 7, line 2, "updating the ith of the first variable" should read "updating the ith entry of the first variable". Appropriate correction is required.
Applicant is advised that should claim 2 be found allowable, claim 3 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1- 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, under the Alice framework analysis:
For Step 1, the claim is directed to a statutory category, in this case a machine.
For Step 2A Prong One, the claim is directed updating three vectors, which is a mathematical concept, in this case mathematical calculations. The claim recites a series of mathematical calculations used to solve vector optimization problems (Equations 1-3). Per Charu C. Aggarwal’s textbook Linear Algebra and Optimization for Machine Learning, “vectors” are defined as “arrays of numerical values” (“Linear Algebra and Optimization: An Introduction”, Page 2). The updating of vectors requires performing a mathematical calculation that would modify or change the numerical values.
For Step 2A Prong Two, additional elements consist “a calculation device” and “a processing device”. These elements are merely an “apply it” scenario using generically recited computer components to perform the mathematical calculations. See MPEP 2106.05(f).
For Step 2B, he additional elements do not amount, alone or in combination, to significantly more than the abstract idea. The additional elements merely link the mathematical calculations to a generic processing device in a manner that merely recites “apply it”. For this reason, claim 1 does not amount to significantly more than the abstract idea.
Regarding claims 2-7, they all merely further limit the mathematical calculations in claim 1. For Step 2A Prong One are themselves either mathematical calculations (Claims 2-4) or mathematical relationships (Claims 5-7). For Steps 2A Prong Two and 2B, there are no additional elements that either integrate the abstract idea into a practical application or amount to more than the abstract idea.
Regarding claims 8-10, the additional elements are a “processing device”, “processor”, and “memory part”. For Step 2A Prong Two and 2B, these additional elements are merely generic computer components claimed at a high level, and amount to mere instructions to apply the mathematical calculations disclosed in claim 1. These limitations do not amount to significantly more than the abstract idea.
Regarding claim 11, the claim merely describes a memory that is configured to store the result of the mathematical calculations of claim 1. This is insignificant extra-solution activity that for Step 2B is well-understood, routine and conventional per MPEP 2106.05(d)(II)(iv). This limitation does not amount to significantly more than the abstract idea.
Regarding claims 12-14, the additional elements of a “processing device”, “processor”, and “memory part”. For Step 2A Prong Two and 2B, these additional elements are merely generic computer components claimed at a high level, and amount to mere instructions to apply the mathematical calculations disclosed in claim 1. Additionally, the memory part additionally merely stores and retrieves the results of the mathematical calculations of claim 1, and for Step 2B is regarded as insignificant extra-solution activity that is well-understood, routine and conventional per MPEP 2106.05(d)(II)(iv). These limitations do not amount to significantly more than the abstract idea.
Regarding claims 15-17, the additional elements are a “processing portion”, which for Step 2A Prong Two and 2B is merely a generic computer component claimed at a high level and amount to mere instructions to apply the mathematical calculations disclosed in claim 1, and performing portions of the updates at the same time, which for Step 2B is insignificant extra-solution material that is well-understood, routine and conventional per Steven Brawler’s Introduction to Parallel Programming: “In addition to running completely isolated programs, parallel processing is useful for calculations involving a number of nearly independent but communicating calculations” (“Introduction”, page 2). These limitations do not amount to significantly more than the abstract idea.
Regarding claim 20, it is a method claim that recites the same abstract idea as claim 1 and is rejected for the same reasons. For Step 1, it is now a process, and for Steps 2A Prong Two and 2B does not recite any additional elements that would integrate the abstract idea into a practical application or amount to more than the abstract idea.
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the claim is directed towards a computer program, i.e., software per se. See MPEP 2106.03(I). If considered statutory, it recites similar limitations to claim 1, and does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more.
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the "computer-readable recording medium" encompasses signals per se. The specification states the recording medium includes magnetic media, optical media, semiconductor memory, or any other recording medium, which includes both transitory and non-transitory embodiments (Page 22, lines 7-11). See MPEP 2106.03(II). If considered statutory, it recites similar limitations to claim 1, and does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-10 and 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (“Distributed Optimization for Convex Mixed-Integer Programs based on Projected Subgradient Algorithm”), hereinafter Sun.
Regarding claim 1, Sun discloses a calculation device, comprising: a processing device configured to perform a processing procedure, the processing procedure including a first update (Algorithm 1, line 8) of a first vector (Algorithm 1, xi), a second update (Algorithm 1, line 5) of a second vector (Algorithm 1, yi (k+1), i = 1,..., m), and a third update (Algorithm 1, lines 6-7) of a third vector (Algorithm 1, yi (k+1), i = m + 1, m + 2), the first update including updating the first vector using the second vector and the third vector (Algorithm 1, line 8), the second update including updating the second vector using the first vector (Algorithm 1, line 5), and the processing device being configured to output at least one of the first vector (Algorithm 1, line 2) obtained after repeating the processing procedure (Algorithm 1, lines 4-12) or a function of the first vector obtained after the repeating the processing procedure.
Regarding claims 2 and 3, Sun discloses the device from claim 1, wherein the second update includes updating the second vector using the first vector (Algorithm 1, line 5), a first function (Algorithm 1, line 8) and a second function (Algorithm 1, line 5), an element of the first function includes the first vector (Algorithm 1, line 8), and an element of the second function includes the first vector (Algorithm 1, line 5).
Regarding claim 4, Sun discloses the device from claim 1, wherein the third update includes updating the third vector using the first vector (Algorithm 1, line 6).
Regarding claim 8, Sun discloses the device from claim 1, wherein the processing device includes a processor and a memory part, the processor is configured to perform the first update (Figure 1, Master), the second update (Figure 1, Workers 1 through i), and the third update (Figure 1, Workers m+1), the memory part is configured to store the first vector (Figure 1, xi (k + 1)), the second vector (Figure 1, yi (k + 1)), and the third vector (Figure 1, ym+1 (k + 1)), the processor includes a plurality of processing portions (Figure 1), one of the processing portions is configured to perform a part of the first update (Figure 1, Master), and an other one of the processing portions is configured to perform an other part of the first update (Figure 1, Master).
Regarding claim 9, Sun discloses the device from claim 1, wherein the processing device includes a processor and a memory part (Figure 1), the processor is configured to perform the first update (Figure 1, Master), the second update (Figure 1, Workers 1 through i), and the third update (Figure 1, Workers m+1), the memory part is configured to store the first vector (Figure 1, xi (k + 1)), the second vector (Figure 1, yi (k + 1)), and the third vector (Figure 1, ym+1 (k + 1)), the processor includes a plurality of processing portions (Figure 1), one of the processing portions is configured to perform a part of the second update (Figure 1, Worker 1), and an other one of the processing portions is configured to perform an other part of the second update (Figure 1, Worker i).
Regarding claim 9, Sun discloses the device from claim 1, wherein the processing device includes a processor and a memory part (Figure 1), the processor is configured to perform the first update (Figure 1, Master), the second update (Figure 1, Workers 1 through i), and the third update (Figure 1, Workers m+1), the memory part is configured to store the first vector (Figure 1, xi (k + 1)), the second vector (Figure 1, yi (k + 1)), and the third vector (Figure 1, ym+1 (k + 1)), the processor includes a plurality of processing portions (Figure 1), one of the processing portions is configured to perform a part of the third update (Figure 1, Worker m+1), and an other one of the processing portions is configured to perform an other part of the third update (Figure 1, Worker m+2).
Regarding claim 12, Sun discloses the device from claim 1, wherein the processing device includes a processor and a memory part (Figure 1), the processor includes a first processing portion configured to perform the first update (Figure 1, Master), a second processing portion configured to perform the second update (Figure 1, Worker 1), a third processing portion configured to perform the third update (Figure 1, Worker m+1) , the memory part includes a first memory portion configured to store the first vector (Figure 1, xi (k + 1)), a second memory portion configured to store the second vector (Figure 1, yi (k + 1)), a third memory portion configured to store the third vector (Figure 1, ym+1 (k + 1)), the first vector before the update stored in the first memory portion is supplied to the first processing portion and the third processing portion (Figure 1, arrows between Master and Workers), the second vector before the update stored in the second memory portion is supplied to the second processing portion and the first processing portion (Figure 1, arrows between Master and Worker 1), the third vector before the update stored in the third memory portion is supplied to the third processing portion and the first processing portion (Figure 1, arrows between Master and Worker m+1), the first vector after the update output from the first processing portion is supplied to the first memory portion, the second processing portion, and the third processing portion (Figure 1, arrows from Master to Workers), the second vector after the update output from the second processing portion is supplied to the second memory portion (Figure 1, arrows between Master and Worker 1), and the third vector after the update output from the third processing portion is supplied to the third memory portion (Figure 1, arrows between master and Worker m+1).
Regarding claim 13, Sun discloses the device from claim 1, wherein the processing device includes a processor and a memory part (Figure 1), the processor includes a first processing portion configured to perform the first update (Figure 1, Master), a second processing portion configured to perform the second update (Figure 1, Worker 1), a third processing portion configured to perform the third update (Figure 1, Worker m+1) , the memory part includes a first memory portion configured to store the first vector (Figure 1, xi (k + 1)), a second memory portion configured to store the second vector (Figure 1, yi (k + 1)), a third memory portion configured to store the third vector (Figure 1, ym+1 (k + 1)), the first vector before the update stored in the first memory portion is supplied to the first processing portion (Figure 1, arrows to and from Master), the second vector before the update stored in the second memory portion is supplied to the second processing portion and the first processing portion (Figure 1, arrows to and from Worker 1), the third vector before the update stored in the third memory portion is supplied to the third processing portion and the first processing portion (Figure 1, arrows to and from Worker m+1), the first vector after the update output from the first processing portion is supplied to the first memory portion, the second processing portion, and the third processing portion (Figure 1, arrows from Master to Workers), the second vector after the update output from the second processing portion is supplied to the second memory portion, and the third vector after the update output from the third processing portion is supplied to the third memory portion (Figure 1, arrows between master and Worker m+1)..
Regarding claim 14, Sun discloses the device from claim 1, wherein the processing device includes a processor and a memory part (Figure 1), the processor includes a first processing portion configured to perform the first update (Figure 1, Master), a second processing portion configured to perform the second update (Figure 1, Worker 1), a third processing portion configured to perform the third update (Figure 1, Worker m+1) , the memory part includes a first memory portion configured to store the first vector (Figure 1, xi (k + 1)), a second memory portion configured to store the second vector (Figure 1, yi (k + 1)), a third memory portion configured to store the third vector (Figure 1, ym+1 (k + 1)), the first vector before the update stored in the first memory portion is supplied to the first processing portion and the second processing portion (Figure 1, arrows between Master and Worker 1), the second vector before the update stored in the second memory portion is supplied to the second processing portion (Figure 1, arrows to and from Worker 1), the third vector before the update stored in the third memory portion is supplied to the third processing portion and the first processing portion (Figure 1, arrows to and from Worker m+1), the first vector after the update output from the first processing portion is supplied to the first memory portion, and the third processing portion (Figure 1, between Master and Worker m+1), the second vector after the update output from the second processing portion is supplied to the second memory portion, and the first processing portion (Figure 1, arrows between Master and Worker 1), and the third vector after the update output from the third processing portion is supplied to the third memory portion (Figure 1, arrows between Master and Worker m+1).
Regarding claim 15, Sun discloses the device from claim 12, wherein the first processing portion includes a plurality of first processing portions (Figure 1, Master), one of the first processing portions performs a part of the first update (Algorithm 1, Line 8), an other one of the first processing portions performs an other part of the first update (Algorithm 1, Line 8), and at least a part of the other part of the first update is performed at a same time as the part of the first update (Section II B, Paragraph 2).
Regarding claim 16, Sun discloses the device from claim 12, wherein the second processing portion includes a plurality of second processing portions (Figure 1, Workers 1 through i), one of the second processing portions performs a part of the second update (Figure 1, Worker 1), an other one of the second processing portions performs an other part of the second update (Figure 1, Worker i), and at least a part of the other part of the second update is performed at a same time as the part of the second update (Section II B, Paragraph 2).
Regarding claim 17, Sun discloses the device from claim 12, wherein the third processing portion includes a plurality of third processing portions (Figure 1, Workers m+1 and m+2), one of the third processing portions performs a part of the third update (Figure 1, Worker m+1), an other one of the third processing portions performs an other part of the third update (Figure 1, Worker m+2), and at least a part of the other part of the third update is performed at a same time as the part of the third update (Section II B, Paragraph 2).
Regarding claim 18, it is a software claim that implements the device claimed in claim 1 and is rejected for the same reasons.
Regarding claim 19, it is a computer-readable recording media claim that implements the device implemented in claim 1 and is rejected for the same reasons.
Regarding claim 20, it is a method claim corresponding to apparatus claim 1 and is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sun as applied to claim 1 above, and further in view of Gonzalez, "Arrays", in Computer Programming in C for Beginners.
Sun does not specifically disclose the memory architecture for the vectors.
Gonzalez discloses a memory part that includes a plurality of memory portions (Page 98, Array a), wherein a part of the memory portion stores one part of the vector (Page 98, Array a, a[0]), and an other part of the memory portions stores an other part of the vector (Page 98, Array a, a[1]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the application to use the data structure disclosed by Gonzalez in the algorithm disclosed by Sun because contiguous memory arrays allow accessing any element in the array to be easy and efficient, as well as allowing random access to any element in the array (Page 98).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nedic et al. (“Constrained Consensus and Optimization in Multi-Agent Networks”) discloses distributed algorithms for optimization that can be used by several agents. Bagherbeik et al. (US 2021/0326679) discloses a method that obtains three matrices, updating an energy value of the system, and solving optimization problems. Matsuura (US 2021/0319155) discloses an Ising computing device that runs several annealing units in parallel.
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/M.S./
Matthew StrappExaminer, Art Unit 2182
(571) 272-9343
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182