Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Amendments
This action is in response to amendments filed September 3rd, 2025, in which Claim 14 has been amended. Claim 16 has been cancelled. The amendments have been entered, and Claims 1-15 and 17 are currently pending.
Duplicate Claims Warning
Applicant is advised that should Claim 6 be found allowable, Claim 14 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-4, 8, 9, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al., “SNrram: An efficient sparse neural network computation architecture based on resistive random-access memory.”
Regarding Claim 1, Wang teaches a method for mapping weights for kernels of a neural network onto a crossbar array (Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters … it has to fully store the filters as expanded”), comprising: receiving two or more kernels of a neural network, where each kernel is represented as values in a matrix (Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters”); for each kernel of the two or more kernels, converting the kernel into a column vector (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel); for each kernel in the two or more kernels, mapping a corresponding column vector to a column of a crossbar array, wherein the crossbar array is comprised of an array of non-volatile memory cells arranged in columns and rows (Wang, pg. 3, 2nd column, Fig. 1(a)) such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line (Wang, pg. 5, 1st column, 1st paragraph, “the input vector (current signals) are driven in row-lines, and the output vector (current signals) are accumulated in column-lines”); and wherein each memory cell in configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and a weight of the given memory cell onto the corresponding bit line of the given memory cell, where the value of the multiplier is encoded in the input signal and the weight of the given memory cell is stored by the given memory cell (Wang, & pg. 3, 2nd column, Fig. 1(a) “Use the RRAM crossbar as a matrix-vector multiplier” & pg. 4, 2nd column, 2nd-to-last paragraph, “The RRAM crossbars in each PE are used to process the matrix-vector multiplication of neural networks” & pg. 5, 1st column, 1st paragraph, “the input vector (current signals) are driven in row-lines, and the output vector (current signals) are accumulated in column-lines”); and storing values for each kernel of the two or more kernels in the array of non-volatile memory cells (pg. 3, 1st column, 2nd paragraph, “traditional RRAM, [will] fully store the filters as expanded”).
Regarding Claim 2, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches for each kernel of the one or more kernels, mapping the column vector for each kernel in successive columns of the crossbar array (Wang, pg. 3, 2nd column, Fig. 1(a)).
Regarding Claim 3, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches for each kernel of the one or more kernels, converting the matrix into a rectangular array (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel), where the values in the matrix of a given kernel are represented by a binary number having at least two bits, each row in the rectangular array corresponds to a different value in the matrix and each column in the rectangular array corresponds to a bit of the binary number used to represent the value (Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density” denotes that each cell in each column of the array corresponds to multiple bits, and thus corresponds to a bit of the binary number used to represent the value).
Regarding Claim 4, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches for each kernel of the one or more kernels, converting the matrix into a rectangular array (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel), where the values in the matrix of a given kernel are represented by a binary number having at least two bits, each row in the rectangular array corresponds to a different value in the matrix and each column in the rectangular array corresponds to a subset of the bits of the binary number used to represent the value (Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density” denotes that each cell in each column of the array corresponds to multiple bits, and thus corresponds to a subset of bits of the binary number used to represent the value, noting that a set is a subset of itself).
Regarding Claim 8, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches wherein each memory cell is further defined as a resistive random-access memory (Wang, title, “based on Resistive Random-Access Memory” & pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters … it has to fully store the filters as expanded”).
Regarding Claim 9, Wang teaches a method for mapping weights for kernels of a neural network onto a crossbar array (Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters … it has to fully store the filters as expanded”), comprising: receiving two or more kernels of a neural network, where each kernel is represented as values in a matrix (Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters”); for each kernel of the two or more kernels, converting the kernel into a rectangular array (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel), where the values in the matrix of a given kernel are represented by a binary number having at least two bits, each row in the rectangular array corresponds to a different value in the matrix and each column in the rectangular array corresponds to a bit of the binary number used to represent the value (Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density” denotes that each cell in each column of the array corresponds to multiple bits, and thus corresponds to a bit of the binary number used to represent the value); for each kernel of the two or more kernels, mapping a corresponding rectangular array to a subset of columns in a cross-bar array (Wang, pg. 3, 2nd column, Fig. 1(a)) wherein the crossbar array is comprised of an array of non-volatile memory cells arranged in columns and rows (Wang, pg. 3, 2nd column, Fig. 1(a)) such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line (Wang, pg. 5, 1st column, 1st paragraph, “the input vector (current signals) are driven in row-lines, and the output vector (current signals) are accumulated in column-lines”); and wherein each memory cell in configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and a weight of the given memory cell onto the corresponding bit line of the given memory cell, where the value of the multiplier is encoded in the input signal and the weight of the given memory cell is stored by the given memory cell (Wang, & pg. 3, 2nd column, Fig. 1(a) “Use the RRAM crossbar as a matrix-vector multiplier” & pg. 4, 2nd column, 2nd-to-last paragraph, “The RRAM crossbars in each PE are used to process the matrix-vector multiplication of neural networks” & pg. 5, 1st column, 1st paragraph, “the input vector (current signals) are driven in row-lines, and the output vector (current signals) are accumulated in column-lines”); and storing values for each kernel of the two or more kernels in the array of non-volatile memory cells (pg. 3, 1st column, 2nd paragraph, “traditional RRAM, [will] fully store the filters as expanded”).
Regarding Claim 13, Wang teaches the method of Claim 9 (and thus the rejection of Claim 9 is incorporated). Wang further teaches wherein each memory cell is further defined as a resistive random-access memory (Wang, title, “based on Resistive Random-Access Memory” & pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters … it has to fully store the filters as expanded”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 4, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding Claim 3, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches for each kernel of the one or more kernels, converting the matrix into a rectangular array (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel), where the values in the matrix of a given kernel are represented by a binary number having at least two bits, each row in the rectangular array corresponds to a different value in the matrix. Wang does not explicitly teach wherein each column in the rectangular array corresponds to a single bit of the binary number used to represent the value, but implies that this is would be a known way of implementing the storing of weight values in RRAM crossbar networks (Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density” implies that others would use single level cells and only be able to store one bit per cell). It would have been obvious to implement Wang using one bit per cell, as Wang implies other hardware systems would do. The motivation to do so is if the multi-level cell hardware were unavailable.
Regarding Claim 4, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches for each kernel of the one or more kernels, converting the matrix into a rectangular array (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel), where the values in the matrix of a given kernel are represented by a binary number having at least two bits, each row in the rectangular array corresponds to a different value in the matrix. Wang does not explicitly teach wherein each column in the rectangular array corresponds to a strict subset of bits of the binary number used to represent the value, but implies that this is would be a known way of implementing the storing of weight values in RRAM crossbar networks (Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density” implies that others would use single level cells and only be able to store one bit per cell, where a single bit is a strict subset of the total number of bits in the value). It would have been obvious to implement Wang using one bit per cell, as Wang implies other hardware systems would do. The motivation to do so is if the multi-level cell hardware were unavailable.
Regarding Claim 9, Wang teaches a method for mapping weights for kernels of a neural network onto a crossbar array (Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters … it has to fully store the filters as expanded”), comprising: receiving two or more kernels of a neural network, where each kernel is represented as values in a matrix (Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters”); for each kernel of the two or more kernels, converting the kernel into a rectangular array (Wang, pg. 3, 1st column, 2nd paragraph, “In order to save memory, we divide the entire matrix into C sub-matrices with respect to the input channels, thus the size of each sub-matrix is
g
×
M
where
g
=
k
×
k
” i.e. each column of M columns is an entire
k
×
k
kernel), where the values in the matrix of a given kernel are represented by a binary number having at least two bits, each row in the rectangular array corresponds to a different value in the matrix …(Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density”); for each kernel of the two or more kernels, mapping a corresponding rectangular array to a subset of columns in a cross-bar array (Wang, pg. 3, 2nd column, Fig. 1(a)) wherein the crossbar array is comprised of an array of non-volatile memory cells arranged in columns and rows (Wang, pg. 3, 2nd column, Fig. 1(a)) such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line (Wang, pg. 5, 1st column, 1st paragraph, “the input vector (current signals) are driven in row-lines, and the output vector (current signals) are accumulated in column-lines”); and wherein each memory cell in configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and a weight of the given memory cell onto the corresponding bit line of the given memory cell, where the value of the multiplier is encoded in the input signal and the weight of the given memory cell is stored by the given memory cell (Wang, & pg. 3, 2nd column, Fig. 1(a) “Use the RRAM crossbar as a matrix-vector multiplier” & pg. 4, 2nd column, 2nd-to-last paragraph, “The RRAM crossbars in each PE are used to process the matrix-vector multiplication of neural networks” & pg. 5, 1st column, 1st paragraph, “the input vector (current signals) are driven in row-lines, and the output vector (current signals) are accumulated in column-lines”); and storing values for each kernel of the two or more kernels in the array of non-volatile memory cells (pg. 3, 1st column, 2nd paragraph, “traditional RRAM, [will] fully store the filters as expanded”).
Wang does not explicitly teach wherein each column in the rectangular array corresponds to a single bit of the binary number used to represent the value, but implies that this is would be a known way of implementing the storing of weight values in RRAM crossbar networks (Wang, pg. 4, 2nd column, 2nd-to-last paragraph, “we also use multi-level cells to store more than one bit of information in a single cell by various levels of resistance to improve the RRAM density” implies that others would use single level cells and only be able to store one bit per cell). It would have been obvious to implement Wang using one bit per cell, as Wang implies other hardware systems would do. The motivation to do so is if the multi-level cell hardware were unavailable.
Claims 5-7, 10-12, 14, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, in view of Wu, US PG Pub 2022/0335278.
Regarding Claim 5, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches receiving an input … and performing a multiply-accumulate operation in relation to each of the two or more kernels stored in the crossbar array (Wang, pg. 2, 2nd column, 3rd paragraph, “When voltages are applied to each row, each cell generates current to perform multiplication. The out current of each column accumulates the corresponding currents on each row branch. All columns in the entire crossbar then naturally achieve matrix-vector multiplication”).
Wang does not teach, but Wu, in the context of implementing a convolutional neural network on a crossbar circuit, does teach receiving an input representing an image (Wu, [0062], “the convolution layer performs convolution processing on an input image”) where the input is a matrix having same number of rows and same number of columns as a given kernel of the two or more kernels (Wu, [0062], “the input image needs to be split into a plurality of image patches (the size of each image patch is the same as that of the kernel) and then a convolution operation is performed”). It would have been obvious to one of ordinary skill in the art to before the effective filing date of the claimed invention to apply the RRAM system of Wang to images patches of the correct size, as does Wu does. The motivation to do so is that CNNs are often applied to images (Wu, [0047], “A convolutional neural network (CNN) is mainly used to identify two-dimensional shapes”) and, according to Wu, “the image needs to be split” to match the size of the kernel.
Regarding Claim 6, the Wang/Wu combination of Claim 5 teaches the method of Claim 5 (and thus the rejection of Claim 5 is incorporated). Wang further teaches adding an additional column to the array of non-volatile memory cells, where the additional column stores a bias term for the multiply-accumulate operation (Wang, pg. 5, 1st column, 1st paragraph, “we can also write bias into RRAM cells, setting the corresponding input as ‘1’ to implement bias addition operation in neural networks”).
Regarding Claim 7, Wang teaches the method of Claim 1 (and thus the rejection of Claim 1 is incorporated). Wang further teaches receiving an input … and performing a multiply-accumulate operation in relation to each of the two or more kernels stored in the cross-bar array (Wang, pg. 2, 2nd column, 3rd paragraph, “When voltages are applied to each row, each cell generates current to perform multiplication. The out current of each column accumulates the corresponding currents on each row branch. All columns in the entire crossbar then naturally achieve matrix-vector multiplication”).
Wang does not teach, but Wu, in the context of implementing a convolutional neural network on a crossbar circuit, does teach receiving an input representing an image (Wu, [0062], “the convolution layer performs convolution processing on an input image”); segmenting the input into segments, where each segment is a matrix having same number of rows and same number of columns as a given kernel of the two or more kernels and for each segment performing the convolution processing/multiplication-accumulation (Wu, [0062], “the input image needs to be split into a plurality of image patches (the size of each image patch is the same as that of the kernel) and then a convolution operation is performed”). It would have been obvious to one of ordinary skill in the art to before the effective filing date of the claimed invention to apply the RRAM system of Wang to images patches segmented into the correct size, as does Wu does. The motivation to do so is that CNNs are often applied to images (Wu, [0047], “A convolutional neural network (CNN) is mainly used to identify two-dimensional shapes”) and, according to Wu, “the image needs to be split” to match the size of the kernel.
Regarding Claim 10, Wang teaches the method of Claim 9 (and thus the rejection of Claim 1 is incorporated). Wang further teaches receiving an input … and performing a multiply-accumulate operation in relation to each of the two or more kernels stored in the crossbar array (Wang, pg. 2, 2nd column, 3rd paragraph, “When voltages are applied to each row, each cell generates current to perform multiplication. The out current of each column accumulates the corresponding currents on each row branch. All columns in the entire crossbar then naturally achieve matrix-vector multiplication”).
Wang does not teach, but Wu, in the context of implementing a convolutional neural network on a crossbar circuit, does teach receiving an input representing an image (Wu, [0062], “the convolution layer performs convolution processing on an input image”) where the input is a matrix having same number of rows and same number of columns as a given kernel of the two or more kernels (Wu, [0062], “the input image needs to be split into a plurality of image patches (the size of each image patch is the same as that of the kernel) and then a convolution operation is performed”). It would have been obvious to one of ordinary skill in the art to before the effective filing date of the claimed invention to apply the RRAM system of Wang to images patches of the correct size, as does Wu does. The motivation to do so is that CNNs are often applied to images (Wu, [0047], “A convolutional neural network (CNN) is mainly used to identify two-dimensional shapes”) and, according to Wu, “the image needs to be split” to match the size of the kernel.
Regarding Claim 11, the Wang/Wu combination of Claim 10 teaches the method of Claim 10 (and thus the rejection of Claim 10 is incorporated). Wang further teaches adding an additional column to the array of non-volatile memory cells, where the additional column stores a bias term for the multiply-accumulate operation (Wang, pg. 5, 1st column, 1st paragraph, “we can also write bias into RRAM cells, setting the corresponding input as ‘1’ to implement bias addition operation in neural networks”).
Regarding Claim 12, Wang teaches the method of Claim 9 (and thus the rejection of Claim 1 is incorporated). Wang further teaches receiving an input … and performing a multiply-accumulate operation in relation to each of the two or more kernels stored in the cross-bar array (Wang, pg. 2, 2nd column, 3rd paragraph, “When voltages are applied to each row, each cell generates current to perform multiplication. The out current of each column accumulates the corresponding currents on each row branch. All columns in the entire crossbar then naturally achieve matrix-vector multiplication”).
Wang does not teach, but Wu, in the context of implementing a convolutional neural network on a crossbar circuit, does teach receiving an input representing an image (Wu, [0062], “the convolution layer performs convolution processing on an input image”); segmenting the input into segments, where each segment is a matrix having same number of rows and same number of columns as a given kernel of the two or more kernels and for each segment performing the convolution processing/multiplication-accumulation (Wu, [0062], “the input image needs to be split into a plurality of image patches (the size of each image patch is the same as that of the kernel) and then a convolution operation is performed”). It would have been obvious to one of ordinary skill in the art to before the effective filing date of the claimed invention to apply the RRAM system of Wang to images patches segmented into the correct size, as does Wu does. The motivation to do so is that CNNs are often applied to images (Wu, [0047], “A convolutional neural network (CNN) is mainly used to identify two-dimensional shapes”) and, according to Wu, “the image needs to be split” to match the size of the kernel.
Claims 14 recites precisely the same limitations as Claim 6, and is thus rejected for reasons set forth in the rejections of that claim.
Regarding Claim 15, the Wang/Wu combination of Claim 14 teaches the method of Claim 14 (and thus the rejection of Claim 14/5 is incorporated). Wang further teaches for each kernel of the one or more kernels, mapping the column vector for each kernel in successive columns of the crossbar array (Wang, pg. 3, 2nd column, Fig. 1).
Regarding Claim 17, the Wang/Wu combination of Claim 14 teaches the method of Claim 14 (and thus the rejection of Claim 14/5 is incorporated). Wang further teaches wherein each memory cell is further defined as a resistive random-access memory (Wang, title, “based on Resistive Random-Access Memory” & pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters … it has to fully store the filters as expanded”).
Response to Arguments
Applicant’s arguments filed September 3rd, 2025 have been fully considered, but are not fully persuasive.
Applicant’s arguments regarding the Duplicate Claims Warning have been fully considered, but are not fully persuasive. Applicant incorporated the limitations of Claim 16 (previously noted as reciting the same scope as Claim 6) into Claim 14. As Claim 14 now recites exactly the same scope as previous Claim 16, which recited the same scope as Claim 6, Claims 6 and 14 now recite identical scope.
Applicant’s argument regarding the 35 U.S.C. 102(a)(1) rejection of independent Claims 1, 9, and 14 have been fully considered, but are unpersuasive. Applicant argues Wang does not teach converting a kernel into a column vector, asserting that “As best seen in Figure 1 of Wang, the kernel is mapped to a two-dimensional matrix.” This assertion is an incorrect interpretation of the art, which states on pg. 3, 1st column, 2nd paragraph, “Fig. 1 gives a simple example with
k
=
2
,
C
=
2
,
M
=
4
. For the original
8
x
4
sparse matrix weights in Fig. 1(a) …” where the
8
x
4
is obtained based on previous statements in the paragraph “Wang, pg. 3, 1st column, 2nd paragraph, “in traditional RRAM, given a convolution layer with
k
×
k
filters, C input channels, and M output channels, it has to fully store the filters as expanded into an
N
×
M
2D-matrix, where
N
=
k
×
k
×
C
” Thus
N
=
k
×
k
×
C
=
2
×
2
×
C
=
8
and M=4, giving the
N
×
M
=
8
x
4
matrix of Fig. 1(a). In this 2D matrix, each column is length
k
x
k
x
C
, or 8, and thus consists of two
k
×
k
filters. Thus, the matrix of Fig. 1(a), (i.e. the traditional method) and the corresponding matrixes of Fig. 1(b) (Wang’s method) each comprise columns, where each column is a column vector obtained by converting
2
×
2
sized filters/kernels.
Annotated Fig. 1 below shows the
2
×
2
filters/kernels converted into length 4 column vectors.
PNG
media_image1.png
559
1284
media_image1.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Zhang, US Patent 11,893,271 also teaches rearranging a kernel into a column vector, see Fig. 1
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN M SMITH/Primary Examiner, Art Unit 2122