DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 October 2025 has been entered.
Claims 14-19 and 21 have been canceled. Claims 1, 8-10, 20, and 22-23 have been amended. Claims 1-13, 20, and 22-26 are pending.
Response to Arguments
Applicant’s arguments with respect to independent claims 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, 7, 20, and 22-23 rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US PGPUB No. 20170170218 (hereinafter Park) in view of Ho, US PGPUB No. 20160225814 (hereinafter Ho).
Regarding claim 1, Park discloses (figs. 1-7) a sensing device, comprising:
a substrate (102, ¶15);
a switching element (106, 108B, 110B, 120B, 120C, ¶15-17, 19), disposed on the substrate (102), and comprising a source electrode (120B) and a semiconductor layer (106, ¶15-17, 19);
a sensing element (108A, 110A, 112, 114, ¶15-17), disposed at one side of the switching element (106, 108B, 110B, 120B, 120C), and comprising:
a lower electrode (110A), electrically connected to the source electrode (120B) (fig. 5, ¶17);
a photoelectric conversion layer (112), disposed on the lower electrode (110A); and an upper electrode (114), disposed on the photoelectric conversion layer (112); and
a common electrode (120A), electrically connected to the upper electrode (114) and belonging to a same film layer as the source electrode (120B) (fig. 5, ¶19).
Park does not disclose wherein a spacing between the lower electrode and the substrate is less than a spacing between the semiconductor layer and the substrate, with the proviso that the lower electrode is in contact with the photoelectric conversion layer.
In the same field of endeavor, Ho discloses (fig. 1) wherein a spacing between the lower electrode (51, Ho ¶11) and the substrate (10, Ho ¶9) is less than a spacing between the semiconductor layer (41, Ho¶10) and the substrate (10), with the proviso that the lower electrode (51) is in contact with the photoelectric conversion layer (52 Ho ¶11).
It would have been obvious to one of ordinary skill in the art at the time of filing to place the lower electrode closer to the substrate, improving device performance by using more efficient signal routing paths.
Regarding claim 2, Park in view of Ho discloses the sensing device as claimed in claim 1,
wherein the switching element (106, 108B, 110B, 120B, 120C, Park ¶15-17, 19) further comprises a top gate (110B), and the top gate (110B) and the lower electrode (110A) belong to a same film layer (Park fig. 3, ¶17).
Regarding claim 5, Park in view of Ho discloses the sensing device as claimed in claim 1,
further comprising a data line, and the data line and the source electrode belonging to a same film layer (Park fig. 5, ¶19 where the data line element 120B is also attached to the switching element as a source connection).
Regarding claim 7, Park in view of Ho discloses the sensing device as claimed in claim 1,
wherein the photoelectric conversion layer (112) completely overlaps the lower electrode (110A), and the upper electrode (114) completely overlaps the photoelectric conversion layer (112) (Park fig. 3, ¶15-17).
Regarding claim 20, Park in view of Ho discloses the sensing device as claimed in claim 1,
wherein an orthographic projection of the lower electrode (51, Ho ¶11) on the substrate (10, Ho ¶9) is outside an orthographic projection of the semiconductor layer (41, Ho¶10) on the substrate (10).
It would have been obvious to one of ordinary skill in the art at the time of filing to place the projection of lower electrode outside that of semiconductor layer, improving device performance by reducing device height and path length of incoming signals.
Regarding claim 22, Park in view of Ho discloses the sensing device as claimed in claim 1,
wherein the source electrode (120B) electrically connects the semiconductor layer (106) with the lower electrode (110A), and a portion of the source electrode between the semiconductor layer (106) and the lower electrode (110A) has a step profile in a cross-sectional view cut through the semiconductor layer (106) and the lower electrode (110A) (Park fig. 2, ¶15-17).
Regarding claim 23, Park and Ho disclose the sensing device as claimed in claim 1,
further comprising an insulating layer (104 and 116) surrounding the semiconductor layer (106) (Park ¶15-18).
Claim(s) 3-4 rejected under 35 U.S.C. 103 as being unpatentable over Park and Ho in view of Wang et al., Dual-gate photo thin-film transistor: a "smart" pixel for high- resolution and low-dose X-ray imaging, J. Phys.: Conf. Ser. 619 012023, 2015 (hereinafter Wang).
Regarding claim 3, Park in view of Ho discloses the sensing device as claimed in claim 2.
Park in view of Ho does not disclose wherein the switching element further comprises a bottom gate, and the semiconductor layer is located between the bottom gate and the top gate.
In the same field of endeavor, Wang discloses (figs. 1-2) wherein the switching element further comprises a semiconductor layer (amorphous silicon or a-Si:H) and a bottom gate (Dark Gate and Bottom Gate Dielectric), and the semiconductor layer (a-Si:H) is located between the bottom gate (Dark Gate and Bottom Gate Dielectric) and the top gate (Photo Gate and Top Gate Dielectric) (Wang, Sec. 2 and 3.1, figs. 1-2).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the gate architecture of Wang in the device of Park, adding to the low noise advantage of a top gate device (Park, ¶6) with in-pixel signal amplification and improved electrical performance (Wang, Intro ¶3-4) for improved device performance with minimal additional mask processing steps.
Regarding claim 4, Park in view of Ho and Wang discloses the sensing device as claimed in claim 3,
wherein the bottom gate (Dark Gate and Bottom Gate Dielectric of Wang) and the top gate (Photo Gate and Top Gate Dielectric of Wang) (Wang, Sec. 2 and 3.1, figs. 1-2) surround the semiconductor layer (106, Park ¶15-17, 19).
Claim(s) 6 rejected under 35 U.S.C. 103 as being unpatentable over Park, Ho, and Wang in view of Ren et al. US PGPUB No. 20190019813 (hereinafter Ren).
Regarding claim 6, Park in view of Ho discloses the sensing device as claimed in claim 5.
Park does not disclose further comprising a scan line, wherein a spacing between the scan line and the data line is 3,000-12,000 Å in a normal direction of the substrate.
In the same field of endeavor, Ren discloses (figs. 1-2) further comprising a scan line (12). Ren further discloses the scan line in the same film layer as the gate (Ren fig. 2, ¶110, 113, 124).
It would have been obvious to one of ordinary skill in the art at the time of filing to include a scan line of Ren in the device of Park in order efficiently process data from the signals in an array of pixel sensors.
Park in view of Ho and Ren does not disclose wherein a spacing between the scan line and the data line is 3,000-12,000 Å in a normal direction of the substrate.
In the same field of endeavor, Wang discloses (figs. 1-2) a gate structure, surrounding the semiconductor layer (a-Si:H), where the gate includes a bottom gate portion (Dark Gate and Bottom Gate Dielectric) and a top gate portion (Photo Gate and Top Gate Dielectric) surrounding the semiconductor layer (Wang, Sec. 2 and 3.1, figs. 1-2). Wang further discloses a spacing between the first metal layer (that would contain the scan line) and the second metal layer (containing the source/data line) as a triple layer with a thickness of 520 nm (220 nm SiNx + 240 nm a-Si:H + 60 nm n+-a-Si:H).
The gate architecture of Wang included within the device of Park, Ho, and Ren would have a scan line in the same layer of the bottom gate as disclosed by Ren, the source in same layer as the data line (Park, fig. 5, ¶19), with a distance normal of the substrate between the scan line and the data line of 520 nm (5,200 Å) that lies within the claimed range of 3,000-12,000 Å.
It would have been obvious to one of ordinary skill in the art at the time of filing to include the device architecture of Wang in the device of Park and Ren, adding to the low noise advantage of a top gate device disclosed by (Park, ¶06) with in-pixel signal amplification and improved electrical performance (Wang, Intro ¶3-4).
Claim(s) 8-9, 11, and 13 rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Koezuka et al. US PGPUB No. 20170104090 (hereinafter Koezuka) and Wang.
Regarding claim 8, Park discloses a sensing device, comprising:
a substrate (102, ¶15);
a switching element (106, 108B, 110B, 120B, 120C, ¶15-17, 19), disposed on the substrate (102), and comprising:
a semiconductor layer (106, ¶15, 17);
a gate (110b); and
a sensing element (108A, 110A, 112, 114, ¶15-17), located on the substrate, and comprising:
a lower electrode (110A);
an upper electrode (114) , overlapping the lower electrode (110A); and
a photoelectric conversion layer (112), disposed between the upper electrode (114) and the lower electrode (110A).
Park does not disclose a gate, surrounding the semiconductor layer;
an insulating layer disposed between the semiconductor layer and the gate,
wherein the gate comprises a top gate top gate electrode above the semiconductor layer and a bottom gate electrode below the semiconductor layer and in contact with the top gate electrode, and the top gate electrode extends downward along two opposite sidewalls of the insulating layer.
In the same field of endeavor, Koezuka discloses (figs. 4A-4C) a gate (112 and 106), surrounding the semiconductor layer (108i , Koezuka ¶130);
an insulating layer (110/111 and 104, Koezuka ¶130) disposed between the semiconductor layer (108i) and the gate (112 and 106),
wherein the gate (112 and 106) comprises a top gate top gate electrode (112) above the semiconductor layer (108i) and a bottom gate electrode (106) below the semiconductor layer and in contact with the top gate electrode (112), and the top gate electrode extends downward along two opposite sidewalls of the insulating layer (Koezuka fig. 4C, where the top gate electrode extends downward on the sidewalls of the insulating layer 110/111 and connects to 106 via opening 143).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the gate architecture of Koezuka in the device of Park, adding to the low noise advantage of a top gate device disclosed by (Park, ¶6) with in-pixel signal amplification and improved electrical performance (Wang, Intro ¶3-4) for improved device performance while minimizing additional mask processing steps to form a surrounding gate structure.
Regarding claim 9, Park in view of Koezuka and Wang discloses the sensing device as claimed in claim 8,
wherein the top gate electrode (110B) and the lower electrode (110A) belong to a same film layer (Park, fig. 3, ¶17).
Regarding claim 11, Park in view of Koezuka and Wang discloses the sensing device as claimed in claim 8,
wherein the switching element (106, 108B, 110B, 120B, 120C) further comprises a source electrode (120B), and the source electrode (120B) is electrically connected to the semiconductor layer (106) and the lower electrode (110A) Park (¶15-17, 19).
Regarding claim 13, Park in view of Koezuka and Wang discloses the sensing device as claimed in claim 11,
further comprising a common electrode (120A) electrically connected to the upper electrode (114) and belonging to a same film layer as the source electrode (120B) (Park fig. 5, ¶19).
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Koezuka, Wang and Ren.
Regarding claim 10, Park in view of Koezuka and Wang discloses the sensing device as claimed in claim 8.
Koezuka discloses wherein the gate (112 and 106 Koezuka ¶130) further comprises a bottom gate electrode (106).
Park in view of Koezuka and Wang does not disclose further comprising a scan line, wherein the scan line and the bottom gate belong to a same film layer.
In the same field of endeavor, Ren discloses (figs. 1-2) further comprising a scan line (12), wherein the scan line and the bottom gate belong to a same film layer on the same film layer as the gate (Ren fig. 2, ¶110, 0113, 0124).
It would have been obvious to one of ordinary skill in the art at the time of filing to include a scan line of Ren in the same film layer in the device of Park in view of Wang in order efficiently process data from the signals in an array of pixel sensors and reducing number of masks to form the bottom gate and the scan line.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Park, Koezuka and Wang in further view of Lee et al. US PGPUB No. 20180114866 (hereinafter Lee).
Regarding claim 12, Park in view of Koezuka and Wang discloses the sensing device as claimed in claim 11.
Park in view of Koezuka and Wang does not disclose wherein a minimum spacing between an orthogonal projection of the gate on the substrate and an orthogonal projection of the source electrode on the substrate is 0 to 5 µm.
Park shows a spacing between an orthogonal projection of the gate on the substrate and an orthogonal projection of the source electrode on the substrate. However, Park does not disclose any expressed motivation for a minimum spacing.
In the same field of endeavor, Lee discloses (fig. 1) an expressed motivation to maintain a minimum spacing between an orthogonal projection of a gate (160) on a substrate (100) and an orthogonal projection of a source electrode (181) on the substrate (Lee, fig. 1, ¶51-52).
It is evident that Lee recognizes that a minimum spacing between the gate and the source is a parameter that is a result effective variable since varying it affects parasitic capacitance formed between the source electrode (181), the drain electrode (182) and the gate electrode (160) and impacts the reliability of the transistor (Lee ¶51).
It would therefore have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the minimum spacing between the gate and the source of Park and make it between 0 to 5 microns in order to reduce the parasitic capacitance formed between the source electrode and the gate electrode and accordingly, reliability of the transistor can be improved (Lee, ¶51).
MPEP §2144.05-II (A) states "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).
Furthermore, MPEP §2144.05-II (B) describes that it is considered to be prima facie obvious when there is a motivation to optimize result-effective variables, i.e., a variable which achieves a recognized result.
Based on Park, as modified by Lee, controlling the minimum spacing between the gate electrode and the source electrode is a result effective variable and thus is considered to be prima facie obvious as explained above.
Claims 24-26 rejected under 35 U.S.C. 103 as being unpatentable over Park, Ho, and Koezuka in further view of Konishi et al. US PGPUB No. 20040235261 (hereinafter Konishi).
Regarding claim 24, Park and Ho disclose the sensing device as claimed in claim 23.
Park and Ho do not disclose further comprising an annular gate extending from above the insulating layer downward along two opposite sidewalls of the insulating layer to below the insulating layer.
In the same field of endeavor, Koezuka discloses (figs. 4A-4C) further comprising a gate (112 and 106 Koezuka ¶130) extending from above the insulating (110/111 and 104, Koezuka ¶130) downward along two opposite sidewalls of the insulating layer to below the insulating layer (fig. 4C).
It would have been obvious to one of ordinary skill in the art at the time of filing to include the gate architecture of Koezuka in the device of Park, adding to the low noise advantage of a top gate device disclosed by (Park, ¶6) with in-pixel signal amplification and improved electrical performance (Wang, Intro ¶3-4) for improved device performance while minimizing additional mask processing steps to form a surrounding gate structure.
Park in view of Ho and Koezuka does not disclose the gate as an annular gate. In the same field of endeavor, Konishi discloses (figs. 5-6) a transistor with an annular gate electrode (222 Konishi ¶12). It would have been obvious to one of ordinary skill in the art at the time of filing to use an annular gate shape as disclosed by Konishi, reducing drain electric field to improve reliability and device lifetime.
Regarding claim 25, Park in view of Ho, Koezuka and Konishi disclose the sensing device as claimed in claim 24,
wherein a central axis of the annular gate (222 Konishi ¶12) is located in the semiconductor layer (216b, Konishi ¶10) (Konishi figs. 5-6).
Regarding claim 26, Park in view of Ho, Koezuka and Konishi disclose the sensing device as claimed in claim 24,
further comprising a drain electrode (227, Konishi ¶13) disposed at a side of the annular gate opposite the source electrode (227, Konishi ¶13).
Conclusion
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/Seth D Lawson/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893