DETAILED ACTION
The instant application having Application No. 17/888,573 has a total of 20 claims pending in the application; there are 2 independent claims and 18 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9, 11, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Avarez, II et al. (Publication Number US 2003/0046356 A1).
As per claim 1, Avarez, II et al. discloses “A method of serialized broadcast command messaging in a distributed symmetric multiprocessing (SMP) system (Abstract, lines 1-3), the method comprising: sending a serial broadcast command from a home chip to a plurality of other chips comprising serial primary chip, wherein each chip of the plurality of other chips comprises a broadcast controller mapped to a home chip broadcast controller (multiple master devices such as processors are organized into a set of nodes supported by a node controller, where the node controller receives transactions from a master device and communicates with a master device as another master device or as a slave device; Paragraph 0013).” Avarez, II et al. discloses “assigning, by the serial primary chip, a tag to the serial broadcast command (see the transaction tag; Paragraph 0065).” Avarez, II et al. discloses “sending, from the serial primary chip, to the home chip and a remainder of the plurality of other chips, the tag (Paragraph 0109-0110, 0116-0117; FIG. 11).” Avarez, II et al. discloses “and broadcasting, by the home chip and each chip of the plurality of other chips, the serial broadcast command in an order based on the tag of the serial broadcast command (Paragraph 0109-0110, 0116-0117; FIG. 11).”
As per claims 9 and 19, Avarez, II et al. discloses “The method of claim 1 (as disclosed by Avarez, II et al. above), wherein the serial broadcast command is broadcast by the home chip and the plurality of other chips responsive to a respective local tag matching the tag of the serial broadcast command (see the transaction tag; Paragraph 0065).”
As per claim 11, Avarez, II et al. discloses “A system for serialized broadcast command messaging in a distributed symmetric multiprocessing (SMP) system (Abstract, lines 1-3), comprising: a home chip (multiple master devices such as processors; Paragraph 0013).” Avarez, II et al. discloses “a plurality of other chips comprising a serial primary chip, wherein each chip of the plurality of other chips comprises a broadcast controller mapped to a home chip broadcast controller (multiple master devices such as processors are organized into a set of nodes supported by a node controller, where the node controller receives transactions from a master device and communicates with a master device as another master device or as a slave device; Paragraph 0013).” Avarez, II et al. discloses “and wherein the system is configured to perform steps comprising: sending a serial broadcast command from the home chip to the plurality of other chips (Paragraph 0109-0110, 0116-0117; FIG. 11).” Avarez, II et al. discloses “assigning, by the serial primary chip, a tag to the serial broadcast command (see the transaction tag; Paragraph 0065).” Avarez, II et al. discloses “sending, from the serial primary chip, to the home chip and a remainder of the plurality of other chips, the tag (Paragraph 0109-0110, 0116-0117; FIG. 11).” Avarez, II et al. discloses “and broadcasting, by the home chip and each chip of the plurality of other chips, the serial broadcast command based on the tag of the serial broadcast command (Paragraph 0109-0110, 0116-0117; FIG. 11).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 2-10 and 12-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Avarez, II et al. (Publication Number US 2003/0046356 A1) in view of Kohl et al. (Publication Number US 2020/0264797 A1).
As per claims 2 and 12, Avarez, II et al. discloses “The method of claim 1 (as disclosed by Avarez, II et al. above).” However, Avarez, II et al. does not explicitly disclose the use of “drawers” as disclosed in the limitation “wherein the home chip is included in a home drawer and the serial primary chip is included in a serial primary drawer.”
Kohl et al. disclose the use of “drawers“ as disclosed in the limitation “wherein the home chip is included in a home drawer and the serial primary chip is included in a serial primary drawer (FIG. 1; Paragraph 0030).”
Avarez, II et al. and Kohl et al. are analogous art in that they in the field of processor groupings.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Avarez, II et al. and Kohl et al. to enable optimal resource allocation among groupings/partitions without disruption [Paragraph 0003].
As per claims 3 and 13, Avarez, II et al. discloses “The method of claim 2 (as disclosed by Avarez, II et al. and Kohl et al. above), wherein sending the serial broadcast command from the home chip to the plurality of other chips comprises: sending, by the home chip, the serial broadcast command to other chips on the home drawer (while Kohl et al. disclose the drawers [FIG. 1; Paragraph 0030], Avarez, II et al. is directed to the transmission/broadcasting of commands; Paragraph 0109-0110, 0116-0117; FIG. 11).” Avarez, II et al. discloses “and sending, via a bus coupling the home drawer and the serial primary drawer, the serial broadcast command to the serial primary drawer (while Kohl et al. disclose the drawers [FIG. 1; Paragraph 0030], Avarez, II et al. is directed to the transmission/broadcasting of commands particularly with the involvement of node controllers; Paragraph 0109-0110, 0116-0117; FIG. 11).”
As per claims 4 and 14, Avarez, II et al. discloses “The method of claim 3 (as disclosed by Avarez, II et al. and Kohl et al. above), wherein sending the serial broadcast command to the serial primary drawer comprises: sending, from a first fork chip in the home drawer to a first branch chip in the serial primary drawer, the serial broadcast command (while Kohl et al. disclose the drawers [FIG. 1; Paragraph 0030], Avarez, II et al. is directed to the transmission/broadcasting of commands particularly with the involvement of node controllers; Paragraph 0109-0110, 0116-0117; FIG. 11).” Avarez, II et al. discloses “and sending, from the first branch chip to a remainder of chips in the serial primary drawer, the serial broadcast command (while Kohl et al. disclose the drawers [FIG. 1; Paragraph 0030], Avarez, II et al. is directed to the transmission/broadcasting of commands particularly with the involvement of node controllers; Paragraph 0109-0110, 0116-0117; FIG. 11).”
As per claims 5 and 15, Kohl et al. discloses “The method of claim 4 (as disclosed by Avarez, II et al. and Kohl et al. above), wherein the bus is a first bus of a pair of buses coupling the home drawer to the serial primary drawer (see buses 118 connecting the chips 110, 112, 114, and 116; FIG. 1).”
As per claims 6 and 16, Kohl et al. discloses “The method of claim 5 (as disclosed by Avarez, II et al. and Kohl et al. above), wherein the pair of buses further comprises a second bus coupling a second fork chip in the home drawer to a second branch chip in the serial primary drawer (highlighted by the presence of separate drawers (evacuating drawer and destination drawer); FIG. 4-5).”
As per claims 7 and 17, Avarez, II et al. discloses “The method of claim 5 (as disclosed by Avarez, II et al. and Kohl et al. above), wherein sending the tag comprises: sending, from the serial primary chip, to one or more chips on the serial primary drawer, the tag (see the transaction tag; Paragraph 0065).” Avarez, II et al. discloses “and sending, from the one or more chips on the serial primary drawer to one or more other drawers, the serial broadcast command and the tag (while Kohl et al. disclose the drawers [FIG. 1; Paragraph 0030], Avarez, II et al. is directed to the transmission/broadcasting of commands particularly with the involvement of node controllers; Paragraph 0109-0110, 0116-0117; FIG. 11).”
As per claims 8 and 18, Kohl et al. discloses “The method of claim 7 (as disclosed by Avarez, II et al. and Kohl et al. above), wherein each of the one or more chips of the serial primary drawer is coupled to a corresponding drawer of the one or more other drawers (chip 110 is connected to chip 112, chip 112 to chips 110 and 114, and chip 114 to chips 112 and 116; FIG. 1).”
As per claims 10 and 20, Avarez, II et al. discloses “The method of claim 9 (as disclosed by Avarez, II et al. above).” However, Avarez, II et al. does not disclose “wherein the serial broadcast command is broadcast via an on-chip ring.”
Kohl et al. discloses “wherein the serial broadcast command is broadcast via an on-chip ring (connection from drawer 102 to 108 which loops back to drawer 102; FIG. 1).”
Avarez, II et al. and Kohl et al. are analogous art in that they in the field of processor groupings.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Avarez, II et al. and Kohl et al. to enable optimal resource allocation among groupings/partitions without disruption [Paragraph 0003].
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated August 16, 2022, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach command broadcasting.
U.S. PATENT NUMBERS:2011/0320665 A1 – [Abstract; Paragraphs 0018-0020]
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
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/H.W.Y/Examiner, Art Unit 2181 September 29, 2025
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181