DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5, 7-8, and 10-20 are presented for examination based on the amended claims in the application filed on July 13, 2026. Claims 6 and 9 have been cancelled by the applicant.
Claims 1-3, 5, 7, 11-12, 14-15, and 17-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2021/0191765 A1 Bokam, Lava Kumar et al.
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Brandalero, Marcelo, Thiago Dadalt Souto, Luigi Carro, and Antonio Carlos Schneider Beck. “Predicting performance in multi-core systems with shared reconfigurable accelerators.” Journal of Systems Architecture 98 (2019): 201-213.
Claims 8 and 10 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Wang, Lu, Yanghua Xiao, Bin Shao, and Haixun Wang. “How to partition a billion-node graph.” In 2014 IEEE 30th International Conference on Data Engineering, pp. 568-579. IEEE, 2014.
Claims 13 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Hestness, Joel, Boris Grot, and Stephen W. Keckler. “Netrace: dependency-driven trace-based network-on-chip simulation.” In Proceedings of the Third International Workshop on Network on Chip Architectures, pp. 31-36. 2010.
This action is made Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 13, 2026 has been entered.
Response to Amendment
The amendment filed July 13, 2026 has been entered. Claims 1-5, 7-8, and 10-20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Final Office Action mailed May 12, 2026.
Claim Objections
Claims 11-12 are objected to because of the following informality: Claim 11, which recites “The method of claim 9” in Ln. 1, should be “The system of claim 1”. All claims dependent on an objected base claim are objected based on their dependency.
Appropriate correction is required.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. § 102 and 103 (or as subject to pre-AIA 35 U.S.C. § 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7, 11-12, 14-15, and 17-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2021/0191765 A1 Bokam, Lava Kumar et al. [herein “Bokam”].
As per claim 1, Bokam teaches “A processor-implemented method of estimating execution time of a neural network in a multi-core accelerator”. (Para. 0014, “the method S100 additionally includes aggregating the selected schedule for each layer in the set of layers to generate a complete schedule for execution of the artificial neural network on the multicore processor in Block S150” [method of estimating execution of a neural network in a multicore processor]. Para. 0097, “the system can: simulate the set of complete schedules based on the processor representation to calculate an inference time and a power consumption of each complete schedule in the set of complete schedules” [method of estimating execution time of a neural network]. Para. 0017, “the multicore processor can include: compute resources, such as central processing unit cores (hereinafter “CPU cores”), graphics process unit cores (hereinafter “GPU cores”), and/or network-specific processor cores (e.g., the deep vision processor as described in U.S. patent application Ser. No. 16/026,480 and shown in FIG. 4)” [e.g., in a multi-core accelerator]. Para. 0099, “The systems and methods described herein can be embodied and/or implemented at least in part as a machine configured to receive a computer-readable medium storing computer-readable instructions. The instructions can be executed by computer-executable components”. “The computer-executable component can be a processor” [e.g., a processor-implemented method]. Further see Para. 0014, 0017, 0097, and 0099. The examiner has interpreted that a method executed by a processor for generating a schedule with a calculated inference time of the execution of an artificial neural network on a multicore deep vision processor as a processor-implemented method of estimating execution time of a neural network in a multi-core accelerator.)
Bokam teaches “generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer, each of the partitions comprising a plurality of nodes of the weighted node graph, and each node of the weighted node graph corresponding to one layer of the layers of the neural network”. (Para. 0014, “the method S100 additionally includes aggregating the selected schedule for each layer in the set of layers to generate a complete schedule for execution of the artificial neural network on the multicore processor in Block S150” [execution time for each layer of layers of the neural network]. Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [generating trace information comprising operation timing information for each core of the multi-core accelerator based on an estimated execution time for each layer of layers of the neural network]. Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130. More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” [a node graph corresponding to the neural network]. Para. 0048, “the system can calculate a cost for each node in the graph. For example, the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network, each node of the weighted node graph corresponding to one layer of the layers of the neural network]. Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” and Para. 0061, “the system generates a set of weight partitions dividing the set of weights for a layer into chunks that can be efficiently processed by the processor” [by partitioning a weighted node graph corresponding to the neural network, each of the partitions comprising a plurality of nodes of the weighted node graph]. Para. 0036, “the system can access register dimensions of the processor in order to calculate valid partition sizes for the input tensors, weight tensors, and output tensors of each layer of the network” and Para. 0053, “the system can, partition the input tensor and weight tensor of the layer based on the input tensor dimensions and the weight tensor dimensions and the properties of the processor, as shown in FIG. 5” [based on a size of input and output data between the nodes]. Furthermore see Para. 0077, “Generally, upon generating a graph representing execution of a layer of the network on the multicore processor, the system can convert this graph into a schedule assigning (or allocating) each of the operations represented by nodes of the graph to individual compute resources and data-transfer resources of the network via a DAG scheduling algorithm, as shown in FIG. 6. More specifically, the system can, for each layer in the set of layers, generate a schedule for the layer based on the graph for the layer, the schedule assigning the set of compute nodes to the set of processor cores and assigning the set of data transfer nodes to the set of direct memory access cores in Block S140” [generating trace information by partitioning a weighted node graph, each of the partitions comprising a plurality of nodes of the weighted node graph and each node of the weighted node graph corresponding to one layer of the layers of the neural network]. Further see Para. 0014, 0036, 0040-0042, 0047-0053, and 0061. Also see Fig. 5-6. The examiner has interpreted that when generating the schedule of processor operations in the execution of the artificial neural network for each layer by generating a graph for each layer on the multicore processor that represents compute and data transfer operations as nodes, defining the time of each node in the graph by a cost model for each layer, generating weighted partitions of each layer and dividing the weights into chucks for the processor and using properties of processor based on sizes of the input, weight, and output tensors dimensions of each layer and processor of the network, and generating a graph based on the weight partitions as generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer, each of the partitions comprising a plurality of nodes of the weighted node graph, and each node of the weighted node graph corresponding to one layer of the layers of the neural network.)
Bokam teaches “assigning the plurality of partitions to cores of the multi-core accelerator to make communication overhead between the plurality of partitions equal to or lesser than a threshold”. ( Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” [wherein the generating of the trace information comprises the plurality of partitions]. Para. 0077, “Generally, upon generating a graph representing execution of a layer of the network on the multicore processor, the system can convert this graph into a schedule assigning (or allocating) each of the operations represented by nodes of the graph to individual compute resources and data-transfer resources of the network via a DAG scheduling algorithm, as shown in FIG. 6. More specifically the system can, for each layer in the set of layers, generate a schedule for the layer based on the graph for the layer, the schedule assigning the set of compute nodes to the set of processor cores and assigning the set of data transfer nodes to the set of direct memory access cores in Block S140” [assigning the plurality of partitions to the cores of the multi-core accelerator]. Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule. More specifically, the system can access the processor representation of the multicore processor including a cost model indicating a number of cycles and a power consumption of each operation in the set of compute operations and each operation in the set of data-transfer operations” and Para. 0066, “the system can generate graphs defining a set of data-transfer nodes representing a set of data-transfer operations for the set of DMA cores, the set of data-transfer operations including: a data transfer from a main memory of the multicore processor to a shared cache of the multicore processor; and a data transfer from the shared cache of the multicore processor to an individual cache in the set of individual caches of the multicore processor; a data transfer from an individual cache in the set of individual caches of the multicore processor to the shared cache of the multicore processor; and a data transfer from the shared cache of the multicore processor to the main memory of the multicore processor” [i.e. to make communication overhead between the plurality of partitions equal to or lesser than a threshold]. Further see Para. 0040-0042, 0051-0052, and 0077-0078. The examiner has interpreted that generating a graph based on the weighted partitions that execute node data transfer operations of layers that are assigned to processor cores to minimize the cost of the data transfer operations as assigning the plurality of partitions to cores of the multi-core accelerator to make communication overhead between the plurality of partitions equal to or lesser than a threshold.)
Bokam teaches “calculating the execution time of the neural network reflecting communication overhead between the cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information.” (Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [calculating the execution time of the neural network based on the trace information]. Para. 0066, “the system can generate graphs defining a set of data-transfer nodes representing a set of data-transfer operations for the set of DMA cores, the set of data-transfer operations including: a data transfer from a main memory of the multicore processor to a shared cache of the multicore processor; and a data transfer from the shared cache of the multicore processor to an individual cache in the set of individual caches of the multicore processor; a data transfer from an individual cache in the set of individual caches of the multicore processor to the shared cache of the multicore processor; and a data transfer from the shared cache of the multicore processor to the main memory of the multicore processor” [reflecting communication overhead between the cores of the multi-core accelerator and memory for each core of the cores]. Para. 0086, “the system can define signal/wait operations between only a subset of dependent operations from the DAG, thereby decreasing the processing delay caused by each signal/wait dependency” [reflecting memory access time]. Further see Para. 0048, 0066, 0083, 0086 and 0097. The examiner has interpreted that calculating a time value of each node in the graph based on the cost model and operations of the node including a data transfer from a main memory of the multicore processor to a shared cache of the multicore processor, from the shared cache of the multicore processor to an individual cache in the set of individual caches of the multicore processor, from an individual cache in the set of individual caches of the multicore processor to the shared cache of the multicore processor, from the shared cache of the multicore processor to the main memory of the multicore processor to include a signal /wait operation that decreases the processing delay caused by the signal/wait dependency as calculating the execution time of the neural network reflecting communication overhead between the cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information.)
As per claim 2, Bokam teaches “wherein the generating of the trace information comprises generating one or more nodes for the each layer of the layers of neural network, and generating a node graph corresponding to the neural network by connecting a data dependency between the one or more nodes via an edge.” (Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130” [generating a node graph corresponding to the neural network]. “More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” [generating one or more nodes for the each layer], “a set of data transfer nodes representing a set of data transfer operations for the set of direct memory access cores, and a set of edges representing dependencies between the set of compute operations and the set of data transfer operations” [by connecting a data dependency between the one or more nodes via an edge]. Further see Para. 0047. The examiner has interpreted that generating a directed acyclic graph for each layer in the set of layers of the network that defines nodes representing operations of the cores and a set of edges representing dependencies between the operations and a set of data transfer operations as wherein the generating of the trace information comprises generating one or more nodes for the each layer, and generating a node graph corresponding to the neural network by connecting a data dependency between the one or more nodes via an edge.)
As per claim 3, Bokam teaches “wherein the generating of the trace information comprises: extracting operation information of the neural network based on the node graph”. (Para. 0047, “the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores, a set of data transfer nodes representing a set of data transfer operations for the set of direct memory access cores, and a set of edges representing dependencies between the set of compute operations and the set of data transfer operations” [extracting operation information of the neural network based on the node graph]. Further see Para. 0047-0051. The examiner has interpreted that generating a directed acyclic graph for each layer that defines nodes representing operations of the cores as wherein the generating of the trace information comprises: extracting operation information of the neural network based on the node graph.)
Bokam teaches “acquiring a hardware information”. (Para. 0019, “The system generates a static schedule for a network based on the particular hardware components and layout of the multicore processor. Therefore, the system can access processor characteristics via the processor representation, such as the register dimensions (e.g., register file dimensions) of each compute resource of the multicore processor, arithmetic logic unit configuration (hereinafter “ALU”) and reduction unit configuration, and/or the instruction set of each compute resource of the multicore processor” [acquiring a hardware information]. Further see Para. 0019. The examiner teaches that accessing processor characteristics of the particular hardware components as acquiring a hardware information.)
Bokam teaches “determining the estimated execution time for the each layer based on the operation information and the hardware information”. (Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130. More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” [for the each layer]. Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [determining the estimated execution time based on the operation information and the hardware information]. Further see Para. 0047-0051. The examiner has interpreted that generating a graph for each layer of the network that each contain a set of nodes and calculate a time value for each node based on the operations and set of processor characteristics as determining the estimated execution time for the each layer based on the operation information and the hardware information.)
Bokam teaches “generating the weighted node graph based on the estimated execution time for the each layer.” (Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130. More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” and Para. 0048, “the system can calculate a cost for each node in the graph. For example, the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [generating the weighted node graph based on the estimated execution time for the each layer]. Further see Para. 0047-0051. The examiner has interpreted that generating a cost for each node in the graph by calculating a time value for each node in the graph and for each layer as generating the weighted node graph based on the estimated execution time for the each layer.)
As per claim 5, Bokam teaches “wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph.” (Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130. More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” and Para. 0048, “the system can calculate a cost for each node in the graph. For example, the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [generating of the weighted node graph]. Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” [wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph]. Further see Para. 0047-0050. The examiner has interpreted that generating a graph that representing the computing and data transfer operations by transforming weight partition for the output based on the time value calculated on each node in the graph as wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph.)
As per claim 7, Bokam teaches “wherein the partitioning of the weighted node graph comprises partitioning the weighted node graph into the plurality of partitions based on the execution time of each of the plurality of partitions having a difference equal to or lesser than a threshold time.” (Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [i.e., the execution time of each of the plurality of partitions having a difference equal to or lesser than a threshold time ]. Para. 0068, “More specifically, the system can: for each execution parameter combination in an execution parameter set, calculate a lower-bound cost for the execution parameter combination based on the set of processor characteristics, the set of direct memory access characteristics, the cost model, and a heuristic function; select a set of candidate execution parameter combinations as a threshold number of lowest-cost execution parameter combinations; and, for each candidate execution parameter combination in the set of candidate execution parameter combinations, generate a candidate graph in the set of candidate graphs according to the candidate execution parameter combination. Thus, the system can test multiple partitioning and scheduling strategies (via the heuristic function) and can select the most efficient strategies for graphing and scheduling” [wherein the partitioning of the weighted node graph comprises partitioning the weighted node graph into the plurality of partitions based on the execution time of each of the plurality of partitions having a difference equal to or lesser than a threshold time]. Further see Para. 0040-0047, 0068, and 0083. The examiner has interpreted that testing a partition graph that calculated the lower cost based on the cost model, which defines the time of the computing resource in order to minimize the time of the operations when generating the schedule for the layer in the selection of parameters as a threshold of the lowest cost combination as wherein the partitioning of the weighted node graph comprises partitioning the weighted node graph into the plurality of partitions based on the execution time of each of the plurality of partitions having a difference equal to a threshold time.)
As per claim 11, Bokam teaches “wherein the generating of the trace information comprises generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core.” (Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [generating trace information comprising operation timing information for each core]. Para. 0064, “Other compute operations can include: executing a 1D convolution step on an input partition and a weight partition stored in the register file; executing a 2D convolution step on an input partition and a weight partition stored in the register file; loading bits into a shift register to obtain a shifted section of an input partition; performing matrix operations on 1D or 2D data stored in the register files; or any other instructions executable by a processor. In examples in which the processor includes multiple heterogenous cores with variable capabilities, the system can define operations corresponding to each core in the instructions set of each core such that the fixed schedule resulting from these instructions is executable by all cores of the processor” [e.g., generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core]. Further see Para. 0040 and 0064. The examiner has interpreted that defining the time of each function of the computing resources of the multicore processor when generating the schedule of the processor operations that are defined in instructions to be executed by each core as wherein the generating of the trace information comprises generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core.)
As per claim 12, Bokam teaches “wherein the generating of the trace code comprises generating the trace code that comprises at least one of a read/write command comprising a memory address and a data size, data movement information between the cores, or operation timing information performed in each core.” (Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [operation timing information for each core]. Para. 0064, “Other compute operations can include: executing a 1D convolution step on an input partition and a weight partition stored in the register file; executing a 2D convolution step on an input partition and a weight partition stored in the register file; loading bits into a shift register to obtain a shifted section of an input partition; performing matrix operations on 1D or 2D data stored in the register files; or any other instructions executable by a processor. In examples in which the processor includes multiple heterogenous cores with variable capabilities, the system can define operations corresponding to each core in the instructions set of each core such that the fixed schedule resulting from these instructions is executable by all cores of the processor” [e.g., generating trace code that comprises a read/write command comprising operation timing information performed in each core]. Further see Para. 0040 and 0064. The examiner has interpreted that defining the time of each function of the computing resources of the multicore processor when generating the schedule of the processor operations that are defined in instructions to be executed by each core as wherein the generating of the trace code comprises generating the trace code that comprises at least one of a read/write command comprising a memory address and a data size, data movement information between the cores, or operation timing information performed in each core.)
As per claim 14, Bokam teaches “wherein the calculating of the execution time of the neural network comprises: acquiring the memory access time for each core, based on at least one of a memory address or a size”. (Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [calculating the execution time of the neural network]. Para. 0086, “the system can define signal/wait operations between only a subset of dependent operations from the DAG, thereby decreasing the processing delay caused by each signal/wait dependency” [e.g., acquiring the memory access time]. Para. 0031, “the system can access a processor representation that indicates that each DMA core in a subset of DMA cores is configured to transfer data into or out of a specific subset of primary caches. Thus, the system can identify primary memory locations addressable via each DMA core represented in the processor representation” [acquiring memory time for each core based on memory address]. Para. 0032, “the system can also access the size and bandwidth of the transfer busses between primary caches, the shared cache, and/or the main memory of the processor” [acquiring memory time for each core based on a memory size]. Further see Para. 0031-0032, 0048, and 0086. The examiner has interpreted that calculating a time value of each node in the graph based on the cost model and operations of the node to include a signal /wait operation that decreases the processing delay caused by the signal/wait dependency and transferring data between each core and the memory locations when accessing the size and bandwidth of the transfer bus as wherein the calculating of the execution time of the neural network comprises: acquiring the memory access time for each core, based on at least one of a memory address or a size.)
Bokam teaches “acquiring read information and write information between the cores based on the trace information.” (Para. 0086, “the system can define signal/wait operations between only a subset of dependent operations from the DAG, thereby decreasing the processing delay caused by each signal/wait dependency” [e.g., acquiring read information and write information between the cores based on the trace information].” Further see Para. 0086. The examiner has interpreted that defining a signal /wait operation that decreases the processing delay caused by the signal/wait dependency as acquiring read information and write information between the cores based on the trace information.)
As per claim 15, Bokam teaches “wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator.” (Para. 0024, “Once the schedule for the processor is complete, the system can also simulate the execution of this schedule on the processor to calculate IPS of the network executed on the multicore processor, the power consumption of the processor executing the network, and/or the memory utilization of the processor during execution of the network” [e.g., wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator]. Further see Para. 0024 and 0091. The examiner has interpreted that simulating the execution of the operation schedules to calculate the inference per second for the operation of the processor on the multicore processor as wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator.)
Re Claim 17, it is an article of manufacture claim, having similar limitations of claim 1. Thus, claim 17 is also rejected under the similar rationale as cited in the rejection of claim 1.
Furthermore, regarding claim 17, Bokam teaches “a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1”. (Para. 0099, “The systems and methods described herein can be embodied and/or implemented at least in part as a machine configured to receive a computer-readable medium storing computer-readable instruction” [computer-readable storage medium storing instructions that perform the method of claim 1]. Para. 0099, “The instructions can be executed by computer-executable components integrated by computer-executable components integrated with apparatuses and networks of the type described above. The computer-readable medium can be stored on any suitable computer readable media such as RAMs, ROMs, flash memory, EEPROMs, optical devices (CD or DVD), hard drives, floppy drives, or any suitable device” [non-transitory computer-readable storage medium]. “The computer-executable component can be a processor but any suitable dedicated hardware device can (alternatively or additionally) execute the instructions.” [cause the processor to perform the method]. Further see Para. 0099. The examiner has interpreted that embodied the described method into a computer-readable medium storing computer-readable instruction such as an optical or hard drive integrated with a computer-executable component such as a processor to execute the instructions as a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1.)
Re Claim 18, it is a system claim, having similar limitations of claim 1. Thus, claim 18 is also rejected under the similar rationale as cited in the rejection of claim 1.
Furthermore, regarding claim 17, Bokam teaches “An apparatus comprising one or more processors”. (Para. 0017, “as shown in FIG. 1, a computer system (hereinafter “the system”), which can include a single computational device or multiple computational devices (e.g., servers) connected over the internet, executes Blocks of the method S100” [An apparatus]. Para. 0024, “Once the schedule for the processor is complete, the system can also simulate the execution of this schedule on the processor to calculate IPS of the network executed on the multicore processor, the power consumption of the processor executing the network, and/or the memory utilization of the processor during execution of the network” [An apparatus comprising one or more processors]. Further see Para. 0017, 0019, 0024, and 0099. The examiner has interpreted that including a computer system to execute the method and simulate the execution of the schedule on the processor as an apparatus comprising one or more processors.)
Re Claim 19, it is a system claim, having similar limitations of claim 3. Thus, claim 19 is also rejected under the similar rationale as cited in the rejection of claim 3.
Re Claim 20, it is an article of manufacture claim, having similar limitations of claim 14. Thus, claim 20 is also rejected under the similar rationale as cited in the rejection of claim 14.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Brandalero, Marcelo, Thiago Dadalt Souto, Luigi Carro, and Antonio Carlos Schneider Beck. “Predicting performance in multi-core systems with shared reconfigurable accelerators.” Journal of Systems Architecture 98 (2019): 201-213 [herein “Brandalero”].
As per claim 4, Bokam does not specifically teach “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers.”
However, in the same field of endeavor namely estimating the performance of multi-core accelerators, Brandalero teaches “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers.” (Pg. 202 Sect. 1, “To determine the performance impacts of sharing or implementing dedicated reconfigurable accelerators, we propose a new metric: Shared Accelerator Concurrency Level (SACL). In contrast to TLP, which indicates the utilization of the resources (GPP cores) in a multi-core system, SACL estimates the potential for acceleration in turning a shared resource (the reconfigurable fabric) into dedicated resources for each core or group of cores” [for a single-core accelerator to execute the layers]. Pg. 203 Sect. 3, “This metric is independent of the target architecture and evaluates the fraction of the execution time in which two or more threads would be competing to use the shared acceleration resource. By doing so, it can be used to estimate the possible speedup with the addition of new accelerators in different configurations” [wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers]. Further see Sect. 1-3. The examiner has interpreted that estimating the speedup of a dedicated accelerator for each core as wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers” as conceptually seen from the teaching of Brandalero, into that of Bokam because this modification of estimating time for a single core accelerator for the advantageous purpose of accessing performance impacts of accelerator type (Brandalero, Pg. 201-202, Sect. 1). Further motivation to combine be that Bokam and Brandalero are analogous art to the current claim are directed to estimating the performance of multi-core accelerators.
Claims 8 and 10 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Wang, Lu, Yanghua Xiao, Bin Shao, and Haixun Wang. “How to partition a billion-node graph.” In 2014 IEEE 30th International Conference on Data Engineering, pp. 568-579. IEEE, 2014 [herein “Wang”].
As per claim 8, Bokam does not specifically teach “setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm.”
However, in the same field of endeavor namely partitioning node graphs, Wang teaches “setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm.” (Pg. 572 Sect. IV, “Initially, each vertex is assigned a unique label, which indicates the partition it belongs to” [setting each of the nodes as a single preliminary partition]. “In the end, the entire graph will have k labels, and each label has the same number of vertices” [based on a balanced graph partitioning algorithm]. Pg. 570 Sect. II, “we update the vertex label iteratively. In each iteration, a vertex takes the label that is prevalent in its neighborhood as its own label” [merging the preliminary partition]. “The process terminates when labels no longer change. Vertices that have the same label belong to the same partition” [until a number of final partitions]. Pg. 571, Sect. III, “Given k machines, we expect the graph equally distributed over machines, i.e., each machine has approximately [|V|/k] vertices” [e.g., becomes less than a number of cores]. Further see Sect II-IV. The examiner has interpreted that assigning each vertex a unique label identifying its partition, updating the vertex label where the vertex takes the label of its neighborhood as its own label to belong to the same partition, and terminating the iterative labeling process when the labels do not change and where each machine a greater number of vertices as setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm” as conceptually seen from the teaching of Wang, into that of Bokam because this modification of combining partitions based on the number of cores for the advantageous purpose of creating a balanced load across the computing environment (Wang, Pg. 571 Sect. III). Further motivation to combine be that Bokam and Wang are analogous art to the current claim are directed to partitioning node graphs.
As per claim 10, Bokam does not specifically teach “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information.”
However, Wang teaches “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information”. (Pg. 571 Sect. III, “Besides edge cut or communication volume, we measure the goodness of a partitioning by its balance. A partitioning is balanced if each partition has more or less the same amount of nodes. This is desired in a distributed environment for load balance. Given k machines, we expect the graph equally distributed over machines, i.e., each machine has approximately [|V|/k] vertices” [e.g., assigning the plurality of partitions to the cores]. Pg. 569 Sect. I, “For example, graph exploration, i.e., following links from one vertex to its neighbors, is implemented by MapReduce iterations. Each iteration requires large amount of disk space and network I/O” [large amount of communication to adjacent cores]. Pg. 575 Sect. V, “We divide a sub-graph into a set of disjoint blocks so that each block is small enough to fit in the memory of a single machine. A block contains a set of vertices and their adjacent lists. During computation, we load the blocks into memory one by one. For each block, we need to ensure we can carry out the following computation when no other blocks is in memory: each vertex in the block sends its label to all of its neighbors, receives messages from its neighbors, and finally updates its label. This allows us to pipeline the process to improve the usage of the CPU, disk I/O, and network communication” [e.g., mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information]. Further see Sect. I, III, and V. The examiner has interpreted that partitioning amount of nodes to be distributed into machines through iterations that require a large amount of disk space and where the blocks fit into the memory of the machine that contain the set of vertices and their adjacent lists to be send to its respective neighbors and for receiving messages as wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information” as conceptually seen from the teaching of Wang, into that of Bokam because this modification of mapping partition to neighboring cores for the advantageous purpose of improving the usage of the CPU, disk I/O, and network communication (Wang, Pg. 575, Sect. V). Further motivation to combine be that Bokam and Wang are analogous art to the current claim are directed to partitioning node graphs.
Claims 13 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Hestness, Joel, Boris Grot, and Stephen W. Keckler. “Netrace: dependency-driven trace-based network-on-chip simulation.” In Proceedings of the Third International Workshop on Network on Chip Architectures, pp. 31-36. 2010 [herein “Hestness”].
As per claim 13, Bokam teaches “wherein the calculating of the execution time of the neural network [comprises executing a network on chip (NoC) simulator by decoding the trace information].” (Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [calculating the execution time of the neural network based on the trace information]. Further see Para. 0048. The examiner has interpreted that calculating a time value of each node in the graph based on the cost model and operations of the node including a data transfer as calculating the execution time of the neural network.)
Bokam does not specifically teach “comprises executing a network on chip (NoC) simulator by decoding the trace information”.
However, in the same field of endeavor namely modeling the execution time of network cores, Hestness teaches “comprises executing a network on chip (NoC) simulator by decoding the trace information.” (Pg. 2 Sect. 2, “As such, they fail to offer the designer application-level performance insights, such as memory access time or end-to-end runtime” [execution time of network]. Pg. 35, Sect. 6, “we compare application-level performance metrics between M5 full-system simulation and trace-based NOC simulation”… “We then use a custom NOC simulator to test three network topologies” [calculating of the execution time comprises executing a network on chip (NoC) simulator]. Pg. 34 Sect. 4, “Our post-processing application first syntactically parses the simulation trace to build network packets that include the injection cycle, source and destination node, and others. The second phase inspects a window of packets from the previous 1,000,000 trace cycles to detect and track dependencies between them” [by decoding the trace information]. Further Pg. 32 Sect. 2, “We propose a new evaluation methodology for trace-based NOC simulation that captures and obeys the dependencies between messages. Our approach is to construct a directed acyclic graph (DAG) between network messages based on the ordering and dependencies among memory transactions recorded during full-system simulation. The dependency information is stored along with packet data in the network trace. By enforcing the ordering constraints in a network simulator, the proposed technique can greatly increase the fidelity of trace driven evaluation with little impact on simulation speed” [decoding the trace information]. Further see Sect. 2 and 6. The examiner has interpreted that using a custom network on chip simulation to test network topologies in comparing the memory access time and end-to-end runtime by detecting and tracking messages dependencies through parsing simulation traces to build network packets as comprises executing a network on chip (NoC) simulator by decoding the trace information.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “comprises executing a network on chip (NoC) simulator by decoding the trace information” as conceptually seen from the teaching of Hestness, into that of Bokam because this modification of determining trace information with a NoC for the advantageous purpose of increasing the fidelity of the evaluation of the traces with little impact to the simulation speed (Hestness, Pg. 32, Sect. 2). Further motivation to combine be that Bokam and Hestness are analogous art to the current claim are directed to modeling the execution time of network cores.
As per claim 16, Bokam does not specifically teach “generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router.”
However, Hestness teaches “generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router.” (Pg. 33 Sect. 3, “When the L2 receives a packet i containing new data, it may trigger a writeback of the old data via a message to a memory controller” [generating a write packet and transmitting the write packet]. Pg. 34 Sect. 4, “Actual network latencies are dependent on the amount of contention in the network at a given time, as well as the network implementation, such as the number of routers between source and destination of a message” [through a router]. Pg. 34 Sect. 4, “This allows us to concentrate the L2 and memory traffic through a single point, simplifying trace post-processing and eliminating variable access time to physically distinct components” [based on the trace information]. Pg. 33 Sect. 3, “Architectural dependencies arise as a result of architectural component interaction, such as messages between cores, caches, and memory controllers. For our target system, there are 3 types of architectural dependencies: request-request, request-response and response-response. Each of these different types is depicted in Figure 3. For instance, request-request dependencies occur when a request for data causes a miss in the L2 and thus, a subsequent request to the memory controller for the data. Analogously, when the response comes back on-chip,” [e.g., to/by a network controller] “it first returns to the L2 before being forwarded to the requesting L1. Request-response dependencies occur when an architectural component can service a request, so after it receives the request, it can send the response data. In this target system, the L2 and memory controllers can service requests” [transmitting a read request to a target core to generate a read packet, and receiving the read packet]. Further see Sect. 3-4 and Figures 2-3. The examiner has interpreted that triggering a writeback via a message to the memory controller through a single point router for simplifying trace post-processing, generating a response to go on/off chip to supply and receive a request for the sending of response data in a target system contain cores as generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router” as conceptually seen from the teaching of Hestness, into that of Bokam because this modification of monitoring network traffic for the advantageous purpose of generating insight into the network- and application-level performances and bottlenecking in the system (Hestness, Pg. 31, Sect. 1). Further motivation to combine be that Bokam and Hestness are analogous art to the current claim are directed to modeling the execution time of network cores.
Response to Arguments
Applicant’s arguments, see Pg. 7-18, filed July 13, 2026, with respect to the rejection(s) of claims 1-20 under 35 U.S.C. § 101 being directed to an abstract idea have been fully considered and are persuasive with regards to the amended independent claims that integrate the claimed invention into a practical application. Therefore, the rejection has been withdrawn. Furthermore, the rejection(s) of claims 18-20 under 35 U.S.C. § 101 being directed to non-statutory subject matter has also been withdrawn with regards to the amended claims being directed to a statutory subject matter.
Applicant's arguments, see Pg. 19-26, filed July 13, 2026 have been fully considered but they are not persuasive because of the following:
Applicant argues that reference does not teach each and every limitation in the amended claims 1 and 18 because cited reference fails to teach “generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer” (See Applicant’s response, Pg. 24-26).
MPEP § 2143.03 recites “All words in a claim must be considered in judging the patentability of that claim against the prior art” and “Examiners must consider all claim limitations when determining patentability of an invention over the prior art.”
As provided above in amended claim 1, Bokam discloses “generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer, each of the partitions comprising a plurality of nodes of the weighted node graph, and each node of the weighted node graph corresponding to one layer of the layers of the neural network” as when generating the schedule of processor operations in the execution of the artificial neural network for each layer by generating a graph for each layer on the multicore processor that represents compute and data transfer operations as nodes, defining the time of each node in the graph by a cost model for each layer, generating weighted partitions of each layer and dividing the weights into chucks for the processor and using properties of processor based on sizes of the input, weight, and output tensors dimensions of each layer and processor of the network, and generating a graph based on the weight partitions. While the Applicant points out that tensor dimensions are partitioned, while this is true, the examiner has relied on the weight partitioning of the layer that are divided into chucks for the processors and generating the schedule for each layer by assigning nodes to the processor cores as the partitioning of the weighted node graph as provided in the updated citations which have been added to the mapping in the rejection above to the amended limitation. Bokam, in fact, teaches both the partitioning of the tensor and the weight, but the citations relied up for the rejection of the claimed limitation are the weight partitioning and not the partition on the tensor data, specifically. Further see Fig. 5 and 6. Furthermore, the Applicant further argues the partitioning is based on the size of the register and not the data between the nodes, it is both register dimensions and dimensions of the input and output tensors which determine where the partitions are made (see updated citations Para. 0061 and Para. 0053). Additionally, the Applicant argues that partitions are used to create the node graph and the node graph itself is not partitioned. Seen in Para. 0047, a graph is generated comprising nodes, and in Para. a cost for each node in graph is calculated. This first requires a creation of a node graph to be then weighted, i.e. time of the layer to be calculated (also see citations for rejection to claim 2). Once weighted, Bokam then proceeds to partition it and create a partitioned node graph. Thus, the claimed limitation is taught.
Therefore, all of the limitations of the amended claims 1 and 18 are disclosed in Bokam. Therefore, applicant’s arguments are not persuasive and the rejection of claim 1 and 18 as anticipated by Bokam is maintained.
Applicant argues that reference does not teach each and every limitation in the amended claims 1 and 18 because cited reference fails to teach “each of the partitions comprising a plurality of nodes of the weighted node graph, and each node of the weighted node graph corresponding to one layer of the layers of the neural network” (See Applicant’s response, Pg. 24-26).
MPEP § 2143.03 recites “All words in a claim must be considered in judging the patentability of that claim against the prior art” and “Examiners must consider all claim limitations when determining patentability of an invention over the prior art.” Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As provided above in amended claim 1, Bokam discloses “each node of the weighted node graph corresponding to one layer of the layers of the neural network” as in the execution of the artificial neural network for each layer by generating a graph for each layer on the multicore processor that represents compute and data transfer operations as nodes. While the Applicant argues that Bokam generates node per layer and does not generate a single unified graph representing the entire neural network at the layer level. The claim only requires that the nodes merely correspond to a layer and not that each layer is represented by one and only one node as argued. Thus when creating nodes for each layer, the claimed limitation is taught.
Therefore, all of the limitations of the amended claims 1 and 18 are disclosed in Bokam. Therefore, applicant’s arguments are not persuasive and the rejection of claim 1 and 18 as anticipated by Bokam is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Harlap, Aaron, Deepak Narayanan, Amar Phanishayee, Vivek Seshadri, Nikhil Devanur, Greg Ganger, and Phil Gibbons. "Pipedream: Fast and efficient pipeline parallel dnn training." arXiv preprint arXiv:1806.03377 (2018) teaches a method for partitioning layers of a DNN based on the computation time of each layer, data size, and memory required to reduce overhead for training the DNN.
Jia, Zhihao, Sina Lin, Mingyu Gao, Matei Zaharia, and Alex Aiken. "Improving the accuracy, scalability, and performance of graph neural networks with roc." Proceedings of Machine Learning and Systems 2 (2020): 187-198 teaches partitioning a node graph of a GNN based on execution time of the GNN.
Examiner’s Note: The examiner has cited particular columns and line numbers in the reference that applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. In the case of amending the claimed invention, the applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for the proper interpretation and also to verify and ascertain the metes and bound of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Simeon P Drapeau whose telephone number is (571)-272-1173. The examiner can normally be reached Monday - Friday, 8 a.m. - 5 p.m. ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached on (571) 272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SIMEON P DRAPEAU/Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188
Prosecution Insights