DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination based on the amended claims in the application filed on February 4, 2026.
Claims 18-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter.
Claims 1-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception.
Claims 1-3, 5-7, 14-15, and 17-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2021/0191765 A1 Bokam, Lava Kumar et al. [herein “Bokam”].
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Brandalero, Marcelo, Thiago Dadalt Souto, Luigi Carro, and Antonio Carlos Schneider Beck. “Predicting performance in multi-core systems with shared reconfigurable accelerators.” Journal of Systems Architecture 98 (2019): 201-213 [herein “Brandalero”].
Claims 8-12 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Wang, Lu, Yanghua Xiao, Bin Shao, and Haixun Wang. “How to partition a billion-node graph.” In 2014 IEEE 30th International Conference on Data Engineering, pp. 568-579. IEEE, 2014 [herein “Wang”].
Claims 13 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Hestness, Joel, Boris Grot, and Stephen W. Keckler. “Netrace: dependency-driven trace-based network-on-chip simulation.” In Proceedings of the Third International Workshop on Network on Chip Architectures, pp. 31-36. 2010 [herein “Hestness”].
This action is made Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed February 4, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed November 4, 2025. The claim interpretation of the 112(f) limitation found in claims 18-20 is moot due the amendment on the claim limitation which now avoids the claim from being interpreted under 35 U.S.C. 112(f) and the subsequent rejection of claims 18-20 under 35 U.S.C. § 112(b) for lack of corresponding structure is withdrawn.
Claim Objections
Applicant is advised that should claim 1 be found allowable, claim 6 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of “An apparatus comprising a compiler” and “a simulator” encompasses a computer program product, which is merely software per se, a nonstatutory subject matter. The specification does not comprehensively define the “apparatus”, “compiler”, or the “simulator” comprising of any hardware or combination of hardware and software. While specification Para. 00103 cites “In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers”, but there is no clear distinction or link that the components of the claim, e.g., components of the apparatus, are hardware components as provided here in the specification. Therefore, the broadest reasonable interpretation (BRI) of the claim in light of the disclosure is drawn to a computer program per se (referred to as “software per se”) as the accepted definitions of a complier1,2 and simulator3 are computer programs, as given in the technological field. A claim whose BRI covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter. See MPEP 2106.03(II). Therefore, the claims do not fall within at least one of the four categories of patent eligible subject matter recited in 35 U.S.C. § 101 (process, machine, manufacture, or composition of matter).
Claims 1-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
1 Alfred, V., S. Monica, Sethi Ravi, and Ullman Jeffrey D. Compilers Principles, Techniques. Pearson, 2007 defines a compiler as “a program that can read a program in one language – the source language – and translate it into an equivalent program in another language – the target language”.
2 “IEEE Standard Glossary of Software Engineering Terminology,” in IEEE Std 610.12-1990 , vol., no., pp.1-84, 31 Dec. 1990, doi: 10.1109/IEEESTD.1990.101064 similar defines a compiler as “A computer program that translates programs expressed in a high order language into their machine language equivalents.”
3 Catania, Vincenzo, et al. "Noxim: An open, extensible and cycle-accurate network on chip simulator." In 2015 IEEE 26th international conference on application-specific systems, architectures and processors (ASAP), pp. 162-163. IEEE, 2015 defines a simulator (see Para. 0088) as “an open, configurable, extendible, cycle accurate NoC simulator developed in SystemC which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures” and “developed using SystemC, a system description library written in C++”.
Step 1:
Claims 1-16 are directed to a method and fall within the statutory category of a process; claim 17 is directed to a non-transitory computer-readable medium and falls within the statutory category of articles of manufacture; and claims 18-20 are directed to an apparatus and fall within the statutory category of a machine. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1, 17, and 18: The limitations of “generating trace information comprising operation timing information for each core of the multi-core accelerator by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer” and “calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally create or draw with pen and paper a data log with information that specifies when cores of a multiple core accelerator access a memory, what data is accessed to perform functions, when the cores leave the memory based how cores are divided in a weighted node graph of the nodes of a neural network divided sections based on the time determined to complete the tasks as a weight for the graph and size of data shared between the nodes, and a person can mentally determine or draw with pen and paper how long a neural network in a multiple core accelerator takes to perform tasks by calculating the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claims 1, 17, and 18: The limitation of “calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information”, as drafted, is an operation that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation of mathematical evaluations. For example, calculating how long a neural network in a multiple core accelerator takes to perform tasks by taking the difference between the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log based on access time and memory address and size (Para. 0086, “the NoC simulator 300 according to an example may calculate execution time reflecting network contention and memory access time (e.g., the DRAM access time) for trace information for each core, by interworking with the memory simulator 400 (e.g., the DRAM simulator)” and Para. 0089, “the memory manager 320 according to an example may calculate memory access time according to the memory address and a size, and reflect the calculated memory access time in the execution time”).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation of mathematic operation but for the recitation of generic computer components, then it falls within the “Mathematical Operation” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Therefore, yes, claims 1, 17, and 18 recite judicial exceptions. The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 1, 17, and 18: The judicial exception is not integrated into a practical application. In particular, the claims recite the following additional elements: “A processor-implemented method of estimating execution time of a neural network in a multi-core accelerator”, “A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1”, “An apparatus comprising: a compiler”, and “a simulator” which is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) with the broadest reasonable interpretation, which does not integrate a judicial exception into elements.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application?” No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1, 17, and 18 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1, 17, and 18: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components which do not amount to significantly more than the abstract idea.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception?” No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception. Having concluded the analysis within the provided framework, claims 1, 17, and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claim 2, it recites an additional limitation of “generating a node graph corresponding to the neural network by connecting a data dependency between the one or more nodes via an edge”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally create or draw with pen and paper a node graph of the nodes of a neural network that are interconnected with edges that show how the nodes are connected and share data.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claim 2, it recites additional element recitation of “wherein the generating of the trace information comprises generating one or more nodes for the each layer” is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional element amounts to significantly more, this claim also fails both Step 2A prong 2, thus this claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 2 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 3 and 19, they recite additional limitations of:
“extracting operation information of the neural network based on the node graph”,
“acquiring a hardware information”,
“determining the estimated execution time for the each layer based on the operation information and the hardware information”, and
“generating the weighted node graph based on the estimated execution time for the each layer”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, the limitation can be conducted as the following:
a person can mentally determine or draw with pen and paper operational relationships between the nodes of the neural network based on the edges connecting the nodes,
person can mentally determine or draw with pen and paper information about the hardware uses for the nodes such as the processing speed of the hardware,
a person can mentally determine or draw with pen and paper how long a neural network in a multiple core accelerator takes to perform tasks by calculating the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log and processing speed of the hardware, and
a person can mentally update or draw with pen and paper with node graph of the nodes of a neural network based on the time determined to complete the tasks as a weight for the nodes in the graph.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claims 3 and 19, they recite an additional limitation of “determining the estimated execution time for the each layer based on the operation information and the hardware information” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation of mathematical evaluations. For example, calculating how long a neural network in a multiple core accelerator takes to perform tasks by taking the difference between the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log and processing speed of the hardware.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation of mathematic evaluations but for the recitation of generic computer components, then it falls within the “Mathematical Operation” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 4, it recites an additional limitation of “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally determine or draw with pen and paper how long a neural network in a sing core accelerator takes to perform tasks by calculating the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log and processing speed of the hardware for a single core accelerator.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claim 4, it recites an additional limitation of “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation of mathematical evaluations. For example, calculating how long a neural network in a multiple core accelerator takes to perform tasks by taking the difference between the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log and processing speed of the hardware for a single core accelerator.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation of mathematic evaluations but for the recitation of generic computer components, then it falls within the “Mathematical Operation” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 5, it recites an additional limitation of “wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally update or draw with pen and paper with node graph of the nodes of a neural network based on adding the time determined to complete the tasks to the node of the graph.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 6, it recites an additional limitation of “wherein the generating of the trace information comprises partitioning the weighted node graph into a plurality of partitions, based on the estimated execution time for the each layer and the size of the input and output data between the node”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally create or draw with pen and paper a data log with information that specifies when cores of a multiple core accelerator access a memory, what data is accessed to perform functions, when the cores leave the memory based how cores are divided in a weighted node graph of the nodes of a neural network divided sections based on the time determined to complete the tasks as a weight for the graph and size of data shared between the nodes.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 7, it recites an additional limitation of “wherein the partitioning of the weighted node graph comprises partitioning the weighted node graph into the plurality of partitions based on the execution time of each of the plurality of partitions having a difference equal to or lesser than a threshold time”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally divide or draw with pen and paper weighted node graph of the nodes of a neural network into sections based on the time determined to complete the tasks as a weight for the graph and size of data shared between the nodes than is less than a certain threshold.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 8, it recites additional limitations of “wherein the partitioning of the weighted node graph comprises: setting each of the nodes as a single preliminary partition” and “merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally divide or draw with pen and paper weighted node graph of the nodes of a neural network into sections each containing one node, and a person can mentally combine or draw with pen and paper the partitions of weighted node graph of the nodes of a neural network based on the time determined to complete the tasks as a weight for the graph and size of data shared between the nodes until the number of partitions is less than the number of cores.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 9, it recites an additional limitation of “wherein the generating of the trace information comprises assigning the plurality of partitions to the cores to make communication overhead between the plurality of partitions equal to or lesser than a threshold”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally set or draw with pen and paper the partitions of weighted node graph of the nodes of a neural network to certain cores to reduce the amount of data traffic under a certain threshold.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 10, it recites an additional limitation of “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally set or draw with pen and paper the partitions of weighted node graph of the nodes of a neural network having large amounts of data to communicate to adjacent cores to reduce the amount of data traffic under a certain threshold based on the amount of data transfer between adjacent cores and speeds from the hardware information.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 11, it recites an additional limitation of “wherein the generating of the trace information comprises generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally create or draw with pen and paper code for executing functions in the form of computer code of the partitions of cores to track information that specifies when cores of a multiple core accelerator access a memory, communicate with other cores, and what data is accessed to perform the functions.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 12, it recites an additional limitation of “wherein the generating of the trace code comprises generating the trace code that comprises at least one of a read/write command comprising a memory address and a data size, data movement information between the cores, or operation timing information performed in each core”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally create or draw with pen and paper code for executing functions of the partitions of cores in the form of computer code that will track information that specifies when cores of a multiple core accelerator access a memory, communicated with other cores, and what data is accessed to perform the functions.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 13, it recites additional element recitation of “wherein the calculating of the execution time of the neural network comprises executing a network on chip (NoC) simulator by decoding the trace information” is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional element amounts to significantly more, this claim also fails both Step 2A prong 2, thus this claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 13 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 14 and 20, they recite additional limitations of “acquiring the memory access time for each core, based on at least one of a memory address or a size” and “acquiring read information and write information between the cores based on the trace information”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally determine or draw with pen and paper how long a neural network in a multiple core accelerator takes to perform tasks by calculating the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log and location of the memory, and a person can mentally determine or draw with pen and paper what perform tasks were performed by analyzing what was read and wrote in the data by analyzing responses.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claims 14 and 20, they recite an additional limitation of “acquiring the memory access time for each core, based on at least one of a memory address or a size” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation of mathematical evaluations. For example, calculating how long a neural network in a multiple core accelerator takes to perform tasks by taking the difference between the entry time and exit time of a core accessing memory and time taken to exchange memory between cores that was captured in the data log and processing speed of the hardware and location of the memory.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation of mathematic evaluations but for the recitation of generic computer components, then it falls within the “Mathematical Operation” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 15, it recites additional element recitation of “wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator” is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional element amounts to significantly more, this claim also fails both Step 2A prong 2, thus this claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 15 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claim 16, it recites additional element recitation of “generating a write packet based on the trace information, and transmitting the write packet through a router”, “transmitting a read request to a network controller, based on the trace information”, “transmitting, by the network controller, the read request to a target core to generate a read packet”, and “receiving the read packet through the router” which is merely an insignificant extra-solution data gathering and data outputting activities (see MPEP § 2106.05(g)) and a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) both of which do not integrate a judicial exception into practical application. Further, the insignificant extra-solution data gathering, record update, and data transmission activities are also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(II), “The courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, ii. Performing repetitive calculations, iii. Electronic recordkeeping, iv. Storing and retrieving information in memory”). Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional element amounts to significantly more, this claim also fails both Step 2A prong 2, thus this claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 16 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, having concluded the analysis within the provided framework, claims 1-20 do not recite patent eligible subject matter and are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, that has not been integrated into a practical application. The claims further do not recite significantly more than the judicial exception. Claims 2-17 and 19-20 are also rejected for incorporating the deficiency of their independent claims 1, and 18, respectively.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. § 102 and 103 (or as subject to pre-AIA 35 U.S.C. § 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 14-15, and 17-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2021/0191765 A1 Bokam, Lava Kumar et al. [herein “Bokam”].
As per claim 1, Bokam teaches “A processor-implemented method of estimating execution time of a neural network in a multi-core accelerator”. (Para. 0014, “the method S100 additionally includes aggregating the selected schedule for each layer in the set of layers to generate a complete schedule for execution of the artificial neural network on the multicore processor in Block S150” [method of estimating execution of a neural network in a multicore processor]. Para. 0097, “the system can: simulate the set of complete schedules based on the processor representation to calculate an inference time and a power consumption of each complete schedule in the set of complete schedules” [method of estimating execution time of a neural network]. Para. 0017, “the multicore processor can include: compute resources, such as central processing unit cores (hereinafter “CPU cores”), graphics process unit cores (hereinafter “GPU cores”), and/or network-specific processor cores (e.g., the deep vision processor as described in U.S. patent application Ser. No. 16/026,480 and shown in FIG. 4)” [e.g., in a multi-core accelerator]. Para. 0099, “The systems and methods described herein can be embodied and/or implemented at least in part as a machine configured to receive a computer-readable medium storing computer-readable instructions. The instructions can be executed by computer-executable components”. “The computer-executable component can be a processor” [e.g., a processor-implemented method]. Further see Para. 0014, 0017, 0097, and 0099. The examiner has interpreted that a method executed by a processor for generating a schedule with a calculated inference time of the execution of an artificial neural network on a multicore deep vision processor as a processor-implemented method of estimating execution time of a neural network in a multi-core accelerator.)
Bokam teaches “generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer”. (Para. 0014, “the method S100 additionally includes aggregating the selected schedule for each layer in the set of layers to generate a complete schedule for execution of the artificial neural network on the multicore processor in Block S150” [layers of the neural network]. Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [generating trace information comprising operation timing information for each core of the multi-core accelerator based on an estimated execution time for each layer of layers of the neural network]. Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” [a weighted node graph corresponding to the neural network]. Para. 0061, “the system generates a set of weight partitions dividing the set of weights for a layer into chunks that can be efficiently processed by the processor” [by partitioning a weighted node graph corresponding to the neural network]. Para. 0036, “the system can access register dimensions of the processor in order to calculate valid partition sizes for the input tensors, weight tensors, and output tensors of each layer of the network” [based on a size of input and output data between the nodes]. Further see Para. 0014, 0036, 0040, 0050, and 0061. The examiner has interpreted that defining the time of each function of the computing resources of the multicore processor when generating the schedule of the processor operations in the execution of the artificial neural network by generating a graph representing compute and data transfer operations for weighted partitions of each layer and dividing the weights into chucks for the processor and using properties of processor based on sizes of the input, weight, and output tensors of each layer of the network as generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer.)
Bokam teaches “calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information.” (Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [calculating the execution time of the neural network based on the trace information]. Para. 0066, “the system can generate graphs defining a set of data-transfer nodes representing a set of data-transfer operations for the set of DMA cores, the set of data-transfer operations including: a data transfer from a main memory of the multicore processor to a shared cache of the multicore processor; and a data transfer from the shared cache of the multicore processor to an individual cache in the set of individual caches of the multicore processor; a data transfer from an individual cache in the set of individual caches of the multicore processor to the shared cache of the multicore processor; and a data transfer from the shared cache of the multicore processor to the main memory of the multicore processor” [reflecting communication overhead between cores of the multi-core accelerator and memory for each core of the cores]. Para. 0086, “the system can define signal/wait operations between only a subset of dependent operations from the DAG, thereby decreasing the processing delay caused by each signal/wait dependency” [reflecting memory access time]. Further see Para. 0048, 0066, 0083, 0086 and 0097. The examiner has interpreted that calculating a time value of each node in the graph based on the cost model and operations of the node including a data transfer from a main memory of the multicore processor to a shared cache of the multicore processor, from the shared cache of the multicore processor to an individual cache in the set of individual caches of the multicore processor, from an individual cache in the set of individual caches of the multicore processor to the shared cache of the multicore processor, from the shared cache of the multicore processor to the main memory of the multicore processor to include a signal /wait operation that decreases the processing delay caused by the signal/wait dependency as calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information.)
As per claim 2, Bokam teaches “wherein the generating of the trace information comprises generating one or more nodes for the each layer of the layers of neural network, and generating a node graph corresponding to the neural network by connecting a data dependency between the one or more nodes via an edge.” (Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130” [generating a node graph corresponding to the neural network]. “More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” [generating one or more nodes for the each layer], “a set of data transfer nodes representing a set of data transfer operations for the set of direct memory access cores, and a set of edges representing dependencies between the set of compute operations and the set of data transfer operations” [by connecting a data dependency between the one or more nodes via an edge]. Further see Para. 0047. The examiner has interpreted that generating a directed acyclic graph for each layer in the set of layers of the network that defines nodes representing operations of the cores and a set of edges representing dependencies between the operations and a set of data transfer operations as wherein the generating of the trace information comprises generating one or more nodes for the each layer, and generating a node graph corresponding to the neural network by connecting a data dependency between the one or more nodes via an edge.)
As per claim 3, Bokam teaches “wherein the generating of the trace information comprises: extracting operation information of the neural network based on the node graph”. (Para. 0047, “the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores, a set of data transfer nodes representing a set of data transfer operations for the set of direct memory access cores, and a set of edges representing dependencies between the set of compute operations and the set of data transfer operations” [extracting operation information of the neural network based on the node graph]. Further see Para. 0047. The examiner has interpreted that generating a directed acyclic graph for each layer that defines nodes representing operations of the cores as wherein the generating of the trace information comprises: extracting operation information of the neural network based on the node graph.)
Bokam teaches “acquiring a hardware information”. (Para. 0019, “The system generates a static schedule for a network based on the particular hardware components and layout of the multicore processor. Therefore, the system can access processor characteristics via the processor representation, such as the register dimensions (e.g., register file dimensions) of each compute resource of the multicore processor, arithmetic logic unit configuration (hereinafter “ALU”) and reduction unit configuration, and/or the instruction set of each compute resource of the multicore processor” [acquiring a hardware information]. Further see Para. 0019. The examiner teaches that accessing processor characteristics of the particular hardware components as acquiring a hardware information.)
Bokam teaches “determining the estimated execution time for the each layer based on the operation information and the hardware information”. (Para. 0047, “Generally, the system can, for each layer in the set of layers of the network, generate a graph (i.e., a DAG) representing execution of the layer on the multicore processor in Block S130. More specifically, the system can generate a graph for a layer that defines: a set of compute nodes representing a set of compute operations for the set of processor cores” [for the each layer]. Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [determining the estimated execution time based on the operation information and the hardware information]. Further see Para. 0047-0048. The examiner has interpreted that generating a graph for each layer of the network that each contain a set of nodes and calculate a time value for each node based on the operations and set of processor characteristics as determining the estimated execution time for the each layer based on the operation information and the hardware information.)
Bokam teaches “generating the weighted node graph based on the estimated execution time for the each layer.” (Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” [generating the weighted node graph based on the estimated execution time for the each layer]. Further see Para. 0047-0050. The examiner has interpreted that generating a graph that representing the computing and data transfer operations by transforming weight partition based on the time value calculated on each node in the graph as generating the weighted node graph based on the estimated execution time for the each layer.)
As per claim 5, Bokam teaches “wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph.” (Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” [wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph]. Further see Para. 0050. The examiner has interpreted that generating a graph that representing the computing and data transfer operations by transforming weight partition for the output based on the time value calculated on each node in the graph as wherein the generating of the weighted node graph comprises generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph.)
Re Claim 6, it is a method claim, having similar limitations of claim 1. Thus, claim 6 is also rejected under the similar rationale as cited in the rejection of claim 1.
As per claim 7, Bokam teaches “wherein the partitioning of the weighted node graph comprises partitioning the weighted node graph into the plurality of partitions based on the execution time of each of the plurality of partitions having a difference equal to or lesser than a threshold time.” (Para. 0068, “More specifically, the system can: for each execution parameter combination in an execution parameter set, calculate a lower-bound cost for the execution parameter combination based on the set of processor characteristics, the set of direct memory access characteristics, the cost model, and a heuristic function; select a set of candidate execution parameter combinations as a threshold number of lowest-cost execution parameter combinations; and, for each candidate execution parameter combination in the set of candidate execution parameter combinations, generate a candidate graph in the set of candidate graphs according to the candidate execution parameter combination. Thus, the system can test multiple partitioning and scheduling strategies (via the heuristic function) and can select the most efficient strategies for graphing and scheduling”. Further see Para. 0068 and 0083. The examiner has interpreted that testing a partition graph that calculated the lower cost based on the cost model, e.g., the time value, for the selection of parameters as a threshold of the lowest cost combination as wherein the partitioning of the weighted node graph comprises partitioning the weighted node graph into the plurality of partitions based on the execution time of each of the plurality of partitions having a difference equal to a threshold time.)
As per claim 14, Bokam teaches “wherein the calculating of the execution time of the neural network comprises: acquiring the memory access time for each core, based on at least one of a memory address or a size”. (Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [calculating the execution time of the neural network]. Para. 0086, “the system can define signal/wait operations between only a subset of dependent operations from the DAG, thereby decreasing the processing delay caused by each signal/wait dependency” [e.g., acquiring the memory access time]. Para. 0031, “the system can access a processor representation that indicates that each DMA core in a subset of DMA cores is configured to transfer data into or out of a specific subset of primary caches. Thus, the system can identify primary memory locations addressable via each DMA core represented in the processor representation” [acquiring memory time for each core based on memory address]. Para. 0032, “the system can also access the size and bandwidth of the transfer busses between primary caches, the shared cache, and/or the main memory of the processor” [acquiring memory time for each core based on a memory size]. Further see Para. 0031-0032, 0048, and 0086. The examiner has interpreted that calculating a time value of each node in the graph based on the cost model and operations of the node to include a signal /wait operation that decreases the processing delay caused by the signal/wait dependency and transferring data between each core and the memory locations when accessing the size and bandwidth of the transfer bus as wherein the calculating of the execution time of the neural network comprises: acquiring the memory access time for each core, based on at least one of a memory address or a size.)
Bokam teaches “acquiring read information and write information between the cores based on the trace information.” (Para. 0086, “the system can define signal/wait operations between only a subset of dependent operations from the DAG, thereby decreasing the processing delay caused by each signal/wait dependency” [e.g., acquiring read information and write information between the cores based on the trace information].” Further see Para. 0086. The examiner has interpreted that defining a signal /wait operation that decreases the processing delay caused by the signal/wait dependency as acquiring read information and write information between the cores based on the trace information.)
As per claim 15, Bokam teaches “wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator.” (Para. 0024, “Once the schedule for the processor is complete, the system can also simulate the execution of this schedule on the processor to calculate IPS of the network executed on the multicore processor, the power consumption of the processor executing the network, and/or the memory utilization of the processor during execution of the network” [e.g., wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator]. Further see Para. 0024 and 0091. The examiner has interpreted that simulating the execution of the operation schedules to calculate the inference per second for the operation of the processor on the multicore processor as wherein the acquiring of the memory access time comprises acquiring the memory access time for each core by interworking with a memory simulator.)
Re Claim 17, it is an article of manufacture claim, having similar limitations of claim 1. Thus, claim 17 is also rejected under the similar rationale as cited in the rejection of claim 1.
Furthermore, regarding claim 17, Bokam teaches “a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1”. (Para. 0099, “The systems and methods described herein can be embodied and/or implemented at least in part as a machine configured to receive a computer-readable medium storing computer-readable instruction” [computer-readable storage medium storing instructions that perform the method of claim 1]. Para. 0099, “The instructions can be executed by computer-executable components integrated by computer-executable components integrated with apparatuses and networks of the type described above. The computer-readable medium can be stored on any suitable computer readable media such as RAMs, ROMs, flash memory, EEPROMs, optical devices (CD or DVD), hard drives, floppy drives, or any suitable device” [non-transitory computer-readable storage medium]. “The computer-executable component can be a processor but any suitable dedicated hardware device can (alternatively or additionally) execute the instructions.” [cause the processor to perform the method]. Further see Para. 0099. The examiner has interpreted that embodied the described method into a computer-readable medium storing computer-readable instruction such as an optical or hard drive integrated with a computer-executable component such as a processor to execute the instructions as a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1.)
Re Claim 18, it is a system claim, having similar limitations of claim 1. Thus, claim 18 is also rejected under the similar rationale as cited in the rejection of claim 1.
Furthermore, regarding claim 17, Bokam teaches “An apparatus comprising a compiler and a simulator”. (Para. 0017, “as shown in FIG. 1, a computer system (hereinafter “the system”), which can include a single computational device or multiple computational devices (e.g., servers) connected over the internet, executes Blocks of the method S100” [An apparatus comprising a compiler]. Para. 0024, “Once the schedule for the processor is complete, the system can also simulate the execution of this schedule on the processor to calculate IPS of the network executed on the multicore processor, the power consumption of the processor executing the network, and/or the memory utilization of the processor during execution of the network” [a simulator]. Further see Para. 0017, 0019, 0024, and 0099. The examiner has interpreted that including a computer system to execute the method and simulate the execution of the schedule for the processors as an apparatus comprising a compiler and a simulator.)
Re Claim 19, it is a system claim, having similar limitations of claim 3. Thus, claim 19 is also rejected under the similar rationale as cited in the rejection of claim 3.
Re Claim 20, it is an article of manufacture claim, having similar limitations of claim 14. Thus, claim 20 is also rejected under the similar rationale as cited in the rejection of claim 14.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Brandalero, Marcelo, Thiago Dadalt Souto, Luigi Carro, and Antonio Carlos Schneider Beck. “Predicting performance in multi-core systems with shared reconfigurable accelerators.” Journal of Systems Architecture 98 (2019): 201-213 [herein “Brandalero”].
As per claim 4, Bokam does not specifically teach “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers.”
However, in the same field of endeavor namely estimating the performance of multi-core accelerators, Brandalero teaches “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers.” (Pg. 202 Sect. 1, “To determine the performance impacts of sharing or implementing dedicated reconfigurable accelerators, we propose a new metric: Shared Accelerator Concurrency Level (SACL). In contrast to TLP, which indicates the utilization of the resources (GPP cores) in a multi-core system, SACL estimates the potential for acceleration in turning a shared resource (the reconfigurable fabric) into dedicated resources for each core or group of cores” [for a single-core accelerator to execute the layers]. Pg. 203 Sect. 3, “This metric is independent of the target architecture and evaluates the fraction of the execution time in which two or more threads would be competing to use the shared acceleration resource. By doing so, it can be used to estimate the possible speedup with the addition of new accelerators in different configurations” [wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers]. Further see Sect. 1-3. The examiner has interpreted that estimating the speedup of a dedicated accelerator for each core as wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the determining of the estimated execution time comprises determining the estimated execution time for a single-core accelerator to execute the layers” as conceptually seen from the teaching of Brandalero, into that of Bokam because this modification of estimating time for a single core accelerator for the advantageous purpose of accessing performance impacts of accelerator type (Brandalero, Pg. 201-202, Sect. 1). Further motivation to combine be that Bokam and Brandalero are analogous art to the current claim are directed to estimating the performance of multi-core accelerators.
Claims 8-12 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Wang, Lu, Yanghua Xiao, Bin Shao, and Haixun Wang. “How to partition a billion-node graph.” In 2014 IEEE 30th International Conference on Data Engineering, pp. 568-579. IEEE, 2014 [herein “Wang”].
As per claim 8, Bokam does not specifically teach “setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm.”
However, in the same field of endeavor namely partitioning node graphs, Wang teaches “setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm.” (Pg. 572 Sect. IV, “Initially, each vertex is assigned a unique label, which indicates the partition it belongs to” [setting each of the nodes as a single preliminary partition]. “In the end, the entire graph will have k labels, and each label has the same number of vertices” [based on a balanced graph partitioning algorithm]. Pg. 570 Sect. II, “we update the vertex label iteratively. In each iteration, a vertex takes the label that is prevalent in its neighborhood as its own label” [merging the preliminary partition]. “The process terminates when labels no longer change. Vertices that have the same label belong to the same partition” [until a number of final partitions]. Pg. 571, Sect. III, “Given k machines, we expect the graph equally distributed over machines, i.e., each machine has approximately [|V|/k] vertices” [e.g., becomes less than a number of cores]. Further see Sect II-IV. The examiner has interpreted that assigning each vertex a unique label identifying its partition, updating the vertex label where the vertex takes the label of its neighborhood as its own label to belong to the same partition, and terminating the iterative labeling process when the labels do not change and where each machine a greater number of vertices as setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “setting each of the nodes as a single preliminary partition; and merging the preliminary partition until a number of final partitions becomes less than a number of cores, based on a balanced graph partitioning algorithm” as conceptually seen from the teaching of Wang, into that of Bokam because this modification of combining partitions based on the number of cores for the advantageous purpose of creating a balanced load across the computing environment (Wang, Pg. 571 Sect. III). Further motivation to combine be that Bokam and Wang are analogous art to the current claim are directed to partitioning node graphs.
As per claim 9, Bokam teaches “wherein the generating of the trace information comprises assigning the plurality of partitions to the cores [to make communication overhead between the plurality of partitions equal to or lesser than a threshold].” (Para. 0050, “the system can: partition the input tensor of a layer and the weight tensor of a layer to generate a set of input partitions and a set of weight partitions; and generate a graph representing compute and data transfer operations for transforming these input partitions and weight partitions into output partitions according to calculations defined by the layer type” [wherein the generating of the trace information comprises the plurality of partitions]. Para. 0077, “Generally, upon generating a graph representing execution of a layer of the network on the multicore processor, the system can convert this graph into a schedule assigning (or allocating) each of the operations represented by nodes of the graph to individual compute resources and data-transfer resources of the network via a DAG scheduling algorithm, as shown in FIG. 6. More specifically the system can, for each layer in the set of layers, generate a schedule for the layer based on the graph for the layer, the schedule assigning the set of compute nodes to the set of processor cores and assigning the set of data transfer nodes to the set of direct memory access cores in Block S140” [assigning the plurality of partitions to the cores]. Further see Para. 0051, 0066, and 0077. The examiner has interpreted that generating a graph into weighted partitions that execute node data transfer operations of layers that are assigned to processor cores as wherein the generating of the trace information comprises assigning the plurality of partitions to the cores.)
Bokam does not specifically teach “assigning the plurality of partitions to the cores to make communication overhead between the plurality of partitions equal to or lesser than a threshold.”
However, Wang teaches “assigning the plurality of partitions to the cores to make communication overhead between the plurality of partitions equal to or lesser than a threshold.” (Pg. 571 Sect. III, “Besides edge cut or communication volume, we measure the goodness of a partitioning by its balance. A partitioning is balanced if each partition has more or less the same amount of nodes. This is desired in a distributed environment for load balance. Given k machines, we expect the graph equally distributed over machines, i.e., each machine has approximately [|V|/k] vertices” [e.g., assigning the plurality of partitions to the cores]. Pg. 576 Sect. V, “The block size |S| determines the memory usage and communication overheads. The larger |S| is, the more memory will be consumed and the fewer total communications will be produced. |S| has also another indirect influence on the overall performance. When |S| is quite large, too many messages will be sent to other machines, which in turn will overload these machines and degrade their performance. Hence, |S| is critical for the balance between the message generating speed and consuming speed, and the tradeoff between memory usage and communication volume. In general, the optimal block size depends on CPU speed, parallelism efficiency, network speed, and memory size” [e.g., optimize make communication overhead]. Pg. 578 Sect. VI, “As shown in Figure 8(a), the number of messages increases with the number of blocks. We also show ec and cv of the partitioning. We can see that, when there is only one block, the system produces a minimal number of messages (which is close to cv). On the other hand, when the number of blocks is very large, many redundant messages are generated and the total number of messages is close the theoretical worst case of ec”. Fig 8(a), which has been enlarged and annotated below, shows that when number of blocks is equal to 1 then its number of messages equal the minimal amount of messages, computation volume (cv), as represented by the dash-dot line, and Fig 8(a) also shows when for number of blocks equal to 1, 4, 16, 64, 256, then the number of messages are less than the amount of messages for the edge cut (ec), as represented by the dash line; both of these, e.g., make communication overhead between the plurality of partitions equal to or lesser than a threshold. Further see Sect. III, V, and VI. The examiner has interpreted that partitioning number of nodes to be distributed into machines that produces the minimal number of messages and fewer total communications for the communication overheads being equal to the number of messages produced by the computational volume as assigning the plurality of partitions to the cores to make communication overhead between the plurality of partitions equal to a threshold.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “assigning the plurality of partitions to the cores to make communication overhead between the plurality of partitions equal to or lesser than a threshold” as conceptually seen from the teaching of Wang, into that of Bokam because this modification of reducing the amount of communication overhead for the advantageous purpose of improving the performance of the machines and increasing the overall time to execute the network (Wang, Pg. 576 Sect. V). Further motivation to combine be that Bokam and Wang are analogous art to the current claim are directed to partitioning node graphs.
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Figure 1: Fig 8(a) Performance of partitioning algorithms from Wang
As per claim 10, Bokam does not specifically teach “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information.”
However, Wang teaches “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information”. (Pg. 571 Sect. III, “Besides edge cut or communication volume, we measure the goodness of a partitioning by its balance. A partitioning is balanced if each partition has more or less the same amount of nodes. This is desired in a distributed environment for load balance. Given k machines, we expect the graph equally distributed over machines, i.e., each machine has approximately [|V|/k] vertices” [e.g., assigning the plurality of partitions to the cores]. Pg. 569 Sect. I, “For example, graph exploration, i.e., following links from one vertex to its neighbors, is implemented by MapReduce iterations. Each iteration requires large amount of disk space and network I/O” [large amount of communication to adjacent cores]. Pg. 575 Sect. V, “We divide a sub-graph into a set of disjoint blocks so that each block is small enough to fit in the memory of a single machine. A block contains a set of vertices and their adjacent lists. During computation, we load the blocks into memory one by one. For each block, we need to ensure we can carry out the following computation when no other blocks is in memory: each vertex in the block sends its label to all of its neighbors, receives messages from its neighbors, and finally updates its label. This allows us to pipeline the process to improve the usage of the CPU, disk I/O, and network communication” [e.g., mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information]. Further see Sect. I, III, and V. The examiner has interpreted that partitioning amount of nodes to be distributed into machines through iterations that require a large amount of disk space and where the blocks fit into the memory of the machine that contain the set of vertices and their adjacent lists to be send to its respective neighbors and for receiving messages as wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the assigning of the plurality of partitions comprises mapping partitions having a large amount of communication to adjacent cores, based on accelerator topology information included in the hardware information” as conceptually seen from the teaching of Wang, into that of Bokam because this modification of mapping partition to neighboring cores for the advantageous purpose of improving the usage of the CPU, disk I/O, and network communication (Wang, Pg. 575, Sect. V). Further motivation to combine be that Bokam and Wang are analogous art to the current claim are directed to partitioning node graphs.
As per claim 11, Bokam teaches “wherein the generating of the trace information comprises generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core.” (Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [generating trace information comprising operation timing information for each core]. Para. 0064, “Other compute operations can include: executing a 1D convolution step on an input partition and a weight partition stored in the register file; executing a 2D convolution step on an input partition and a weight partition stored in the register file; loading bits into a shift register to obtain a shifted section of an input partition; performing matrix operations on 1D or 2D data stored in the register files; or any other instructions executable by a processor. In examples in which the processor includes multiple heterogenous cores with variable capabilities, the system can define operations corresponding to each core in the instructions set of each core such that the fixed schedule resulting from these instructions is executable by all cores of the processor” [e.g., generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core]. Further see Para. 0040 and 0064. The examiner has interpreted that defining the time of each function of the computing resources of the multicore processor when generating the schedule of the processor operations that are defined in instructions to be executed by each core as wherein the generating of the trace information comprises generating trace code comprising the operation timing information for each core to execute the plurality of partitions that are assigned to the each core.)
As per claim 12, Bokam teaches “wherein the generating of the trace code comprises generating the trace code that comprises at least one of a read/write command comprising a memory address and a data size, data movement information between the cores, or operation timing information performed in each core.” (Para. 0040, “the system accesses a cost model for the multicore processor that defines the time (in number of cycles) and the energy consumed by each function of the set of compute resources of the multicore processor in order to minimize the cost of these operations while generating the static schedule” [operation timing information for each core]. Para. 0064, “Other compute operations can include: executing a 1D convolution step on an input partition and a weight partition stored in the register file; executing a 2D convolution step on an input partition and a weight partition stored in the register file; loading bits into a shift register to obtain a shifted section of an input partition; performing matrix operations on 1D or 2D data stored in the register files; or any other instructions executable by a processor. In examples in which the processor includes multiple heterogenous cores with variable capabilities, the system can define operations corresponding to each core in the instructions set of each core such that the fixed schedule resulting from these instructions is executable by all cores of the processor” [e.g., generating trace code that comprises a read/write command comprising operation timing information performed in each core]. Further see Para. 0040 and 0064. The examiner has interpreted that defining the time of each function of the computing resources of the multicore processor when generating the schedule of the processor operations that are defined in instructions to be executed by each core as wherein the generating of the trace code comprises generating the trace code that comprises at least one of a read/write command comprising a memory address and a data size, data movement information between the cores, or operation timing information performed in each core.)
Claims 13 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Bokam in view of Hestness, Joel, Boris Grot, and Stephen W. Keckler. “Netrace: dependency-driven trace-based network-on-chip simulation.” In Proceedings of the Third International Workshop on Network on Chip Architectures, pp. 31-36. 2010 [herein “Hestness”].
As per claim 13, Bokam teaches “wherein the calculating of the execution time of the neural network [comprises executing a network on chip (NoC) simulator by decoding the trace information].” (Para. 0048, “the system can calculate a time value to each node in the graph based on the operation represented by the node, the cost model, and the set of processor characteristics or the set of DMA characteristics” [calculating the execution time of the neural network based on the trace information]. Further see Para. 0048. The examiner has interpreted that calculating a time value of each node in the graph based on the cost model and operations of the node including a data transfer as calculating the execution time of the neural network.)
Bokam does not specifically teach “comprises executing a network on chip (NoC) simulator by decoding the trace information”.
However, in the same field of endeavor namely modeling the execution time of network cores, Hestness teaches “comprises executing a network on chip (NoC) simulator by decoding the trace information.” (Pg. 2 Sect. 2, “As such, they fail to offer the designer application-level performance insights, such as memory access time or end-to-end runtime” [execution time of network]. Pg. 35, Sect. 6, “we compare application-level performance metrics between M5 full-system simulation and trace-based NOC simulation”… “We then use a custom NOC simulator to test three network topologies” [calculating of the execution time comprises executing a network on chip (NoC) simulator]. Pg. 34 Sect. 4, “Our post-processing application first syntactically parses the simulation trace to build network packets that include the injection cycle, source and destination node, and others. The second phase inspects a window of packets from the previous 1,000,000 trace cycles to detect and track dependencies between them” [by decoding the trace information]. Further Pg. 32 Sect. 2, “We propose a new evaluation methodology for trace-based NOC simulation that captures and obeys the dependencies between messages. Our approach is to construct a directed acyclic graph (DAG) between network messages based on the ordering and dependencies among memory transactions recorded during full-system simulation. The dependency information is stored along with packet data in the network trace. By enforcing the ordering constraints in a network simulator, the proposed technique can greatly increase the fidelity of trace driven evaluation with little impact on simulation speed” [decoding the trace information]. Further see Sect. 2 and 6. The examiner has interpreted that using a custom network on chip simulation to test network topologies in comparing the memory access time and end-to-end runtime by detecting and tracking messages dependencies through parsing simulation traces to build network packets as comprises executing a network on chip (NoC) simulator by decoding the trace information.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “comprises executing a network on chip (NoC) simulator by decoding the trace information” as conceptually seen from the teaching of Hestness, into that of Bokam because this modification of determining trace information with a NoC for the advantageous purpose of increasing the fidelity of the evaluation of the traces with little impact to the simulation speed (Hestness, Pg. 32, Sect. 2). Further motivation to combine be that Bokam and Hestness are analogous art to the current claim are directed to modeling the execution time of network cores.
As per claim 16, Bokam does not specifically teach “generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router.”
However, Hestness teaches “generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router.” (Pg. 33 Sect. 3, “When the L2 receives a packet i containing new data, it may trigger a writeback of the old data via a message to a memory controller” [generating a write packet and transmitting the write packet]. Pg. 34 Sect. 4, “Actual network latencies are dependent on the amount of contention in the network at a given time, as well as the network implementation, such as the number of routers between source and destination of a message” [through a router]. Pg. 34 Sect. 4, “This allows us to concentrate the L2 and memory traffic through a single point, simplifying trace post-processing and eliminating variable access time to physically distinct components” [based on the trace information]. Pg. 33 Sect. 3, “Architectural dependencies arise as a result of architectural component interaction, such as messages between cores, caches, and memory controllers. For our target system, there are 3 types of architectural dependencies: request-request, request-response and response-response. Each of these different types is depicted in Figure 3. For instance, request-request dependencies occur when a request for data causes a miss in the L2 and thus, a subsequent request to the memory controller for the data. Analogously, when the response comes back on-chip,” [e.g., to/by a network controller] “it first returns to the L2 before being forwarded to the requesting L1. Request-response dependencies occur when an architectural component can service a request, so after it receives the request, it can send the response data. In this target system, the L2 and memory controllers can service requests” [transmitting a read request to a target core to generate a read packet, and receiving the read packet]. Further see Sect. 3-4 and Figures 2-3. The examiner has interpreted that triggering a writeback via a message to eh memory controller through a single point router for simplifying trace post-processing, generating a response to go on/off chip to supply and receive a request for the sending of response data in a target system contain cores as generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “generating a write packet based on the trace information, and transmitting the write packet through a router, transmitting a read request to a network controller, based on the trace information; transmitting, by the network controller, the read request to a target core to generate a read packet, and receiving the read packet through the router” as conceptually seen from the teaching of Hestness, into that of Bokam because this modification of monitoring network traffic for the advantageous purpose of generating insight into the network- and application-level performances and bottlenecking in the system (Hestness, Pg. 31, Sect. 1). Further motivation to combine be that Bokam and Hestness are analogous art to the current claim are directed to modeling the execution time of network cores.
Response to Arguments
Applicant's arguments filed on February 4, 2026 have been fully considered but they are not persuasive.
Applicant argues that the amended claims are patent eligible under 35 U.S.C. § 101 without providing any additional rational or evidence (See Applicant’s response, Pg. 8-9).
While the examiner recognizes that the applicant has referred to a quotation from the Ex parte Desjardins, Appeal 2024-000567, the applicant has not made a clear link to any specifics of the decision with regards to aspects of the instant application.
The examiner recommends drawing a clear link of the claims of the instant application to this decision and with respect to Enfish (see MPEP § 2106.06(b)) in the arguments for comparison in the improvement integrating the claims into a practical application as whole for further consideration.
Therefore, for at least the reasons set forth in the provided above with respect to the rejection under 35 U.S.C. § 101, the claims are directed to judicial exception, an abstract idea, and the rejection is maintained.
Applicant argues that the amended claims are patent eligible under 35 U.S.C. § 101 because the claims do not recite mathematical relations, formulas, or calculations (See Applicant’s response, Pg. 9-12).
MPEP 2106.04(a)(2)(I)(C) recites that a “claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the ‘mathematical concepts’ grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number”.
The examiner has provided the rational for the claim limitations that are being directed to a mathematical concept in the rejection above. For example, the claim 1 limitation “calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information”, involves determining the time for a neural network to complete a series of operations, such as nodes accessing data in memory (see Para. 0089, “the memory manager 320 according to an example may calculate memory access time according to the memory address and a size, and reflect the calculated memory access time in the execution time”). As component of the execution time of a neural network, the time required each node in a layer within the neural network to complete all tasks includes summing the time required for the node to access the data required for the each of the tasks of the layer (see Para. 0014, “The determining of the estimated execution time may include determining the estimated execution time for a single-core accelerator to execute the layers. The generating of the weighted node graph may include generating the weighed node graph by adding the estimated execution time for the each layer as a node weight of the node graph”). Therefore, since memory access time is a component of the execution time and the sum of the times of layer, e.g., summing the memory access times to generate the execution time, it is a variable in the calculation of the execution time, e.g., a mathematical operation to determine a number.
As such, this limitation would fall under a mathematical concept in step 2A Prong 1 of analysis above. The examiner has properly identified that the claims recite a mathematical concept as provided in the rejection above under the framework provided in the 2019 Patent Eligibility Guidance and MPEP 2106.04(a)(2)(I)(C). The claims are directed to judicial exception, an abstract idea.
Applicant argues that the amended claims features are patent eligible under 35 U.S.C. § 101 because the claims do not recite mental processes as they are complex operation that cannot be performed in the human mind (See Applicant’s response, Pg. 12).
MPEP § 2106.04(a)(2)(III)(A) recites “claims do recite a mental process when they contain limitations that can practically be performed in the human mind, including for example, observations, evaluations, judgments, and opinions”, “claims can recite a mental process even if they are claimed as being performed on a computer”, and “in evaluating whether a claim that requires a computer recites a mental process, examiners should carefully consider the broadest reasonable interpretation of the claim in light of the specification. For instance, examiners should review the specification to determine if the claimed invention is described as a concept that is performed in the human mind and applicant is merely claiming that concept performed 1) on a generic computer, or 2) in a computer environment, or 3) is merely using a computer as a tool to perform the concept. In these situations, the claim is considered to recite a mental process.”
The examiner has provided the rational for the claim limitations that are being directed to a mental process in the rejection above. For example, the limitation of claim 1 “generating trace information comprising operation timing information for each core of the multi-core accelerator by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer” can be conducted by a person mentally or drawn with pen and paper since a person can create a weighted node graph of the nodes of a neural network and divide the weighted node graph based on data shared between the nodes and time required to complete a set of tasks. Then, a person can create a data log that includes information such as when cores of a multiple core accelerator would access a memory, what data is accessed to perform tasks, and when the cores leave the memory based on the divided weighted node graph that was. Furthermore, the limitation of claim 1 “calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information” can be conducted by a person mentally or drawn with pen and paper since a person can use the data log which shows the operations of the neural network to determine the time to complete all tasks by adding up the accessing memory time and time taken to exchange memory between cores of the layer. This is simple addition guided by the data log to included the sum of the access memory time in the tasks of the nodes.
The examiner has properly identified that the claims recite a mental concept as provided in the rejection above is proper under the framework provided in the 2019 Patent Eligibility Guidance and MPEP § 2106.04(a)(2)(III)(C). The claims are directed to judicial exception, an abstract idea.
Applicant argues that the claims are patent eligible under 35 U.S.C. § 101 since dependent claim 7 was not rejected under 35 U.S.C. § 101 (See Applicant’s response, Pg. 12-13).
Claim 7 was rejected under 35 U.S.C. § 101 in the previous Office Action (see Pg. 13-14 of Non-Final mailed November 4, 2025) and does not integrate claims in to a practical application. The examiner recommends providing rationale as to why the applicant believes that the claim 7 limitation is not an abstract idea but is an additional element that is an improvement to the technology.
Therefore, for at least the reasons set forth in the provided above with respect to the rejection under 35 U.S.C. § 101, the claims are directed to judicial exception, an abstract idea, and the rejection is maintained.
Applicant argues that claim features are patent eligible under 35 U.S.C. § 101 because the claim is integrated into a practical application as claim features recite improvements to another technology or technical field through meaningful limitation when the claims are viewed as a whole (See Applicant’s response, Pg. 13-16).
MPEP § 2106.05(I) recites “An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself." Genetic Techs. Ltd. v. Merial LLC, 818 F.3d 1369, 1376, 118 USPQ2d 1541, 1546 (Fed. Cir. 2016)”; MPEP § 2106.04(I) “Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 1151, 120 USPQ2d 1473, 1483 (Fed. Cir. 2016) ("a new abstract idea is still an abstract idea")”; MPEP § 2106.05(a) recites “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.”; and MPEP § 2106.04(d)(II) recites “examiners evaluate integration into a practical application by: (1) identifying whether there are any additional elements recited in the claim beyond the judicial exception(s); and (2) evaluating those additional elements individually and in combination to determine whether they integrate the exception into a practical application” (emphasis added).
The examiner has provided the rational for the independent claim limitations that are being directed to a mental process and mathematical concepts in the rejection above. While the applicant has cited that “present claims improve the technical fields of artificial intelligence (Al), neural networks (NNs), and AI/NN-specific hardware such as accelerators, neural processors, and/or neural processing units (NPUs)” (see Pg. 14), the claims do not recite this improvement. For example, the limitation of “calculating the execution time of the neural network reflecting communication overhead between cores of the multi-core accelerator and memory access time for each core of the cores, based on the trace information” is a method for a more accurate calculation of an execution time for a neural network (Para. 0049-0050 “The conventional technique of estimating execution time of a neural processing unit (NPU) accelerator has limitations such as an absence of considering memory access time, an absence of considering communication overhead between cores in a many-core or multi-core accelerator (e.g., an NPU), and an absence of reflection of performance change according to a compiler optimization. As a scale of a deep neural network (DNN) application increases, input data and weight data may need to be stored in an external memory (e.g., dynamic random-access memory (DRAM)). Since the conventional system assumes that all data exists in a local memory, performance overhead according to an external memory access may not be reflected”). Therefore, the claims are not directed to improvements to AI/NN, but improvements in a calculation of the run time of an AI/NN, e.g., an abstract idea, which cannot provide the inventive concept for integration into a practical application. Integration into a practical application comes from the individual additional elements or the additional elements when viewed as a whole with the claim. The additional elements are “A processor-implemented method of estimating execution time of a neural network in a multi-core accelerator”, “A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1”, “An apparatus comprising: a compiler”, and “a simulator” which are merely using the generic computer components and functions being used as a tool to perform the abstract idea. Therefore, there are no additional element limitations in the independent claims which can integrate the abstract idea into a practical application by improvements to the technology as listed in MPEP § 2106.04(d)(I). Furthermore, the examiner has also provided the rational for the dependent claim limitations that are being directed to a mental process or a mathematical concept in the rejection above. With the exception of the additional element limitations in the dependent claims which are merely using the generic computer components and functions being used as a tool to perform the abstract idea and insignificant extra-solution data gathering and data outputting activities, there are no additional limitations in the dependent claims which can integrate the abstract idea into a practical application by improvements to the technology or through the use of meaningful limitations.
Therefore, the examiner has properly identified that the claims recite mental processes, mathematical concepts, and limitations that merely use the computer as a tool to perform the abstract idea and insignificant extra-solution activities.
Applicant argues that reference does not teach each and every limitation in the amended claims 1 and 18 because cited reference fails to teach “generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer” (See Applicant’s response, Pg. 16-21).
MPEP § 2143.03 recites “All words in a claim must be considered in judging the patentability of that claim against the prior art” and “Examiners must consider all claim limitations when determining patentability of an invention over the prior art.”
As provided above in claim 1, Bokam discloses “generating trace information comprising operation timing information for each core of the multi-core accelerator, by partitioning a weighted node graph corresponding to the neural network based on an estimated execution time for each layer of layers of the neural network and a size of input and output data between nodes of the each layer” as defining the time of each function of the computing resources of the multicore processor when generating the schedule of the processor operations in the execution of the artificial neural network by generating a graph representing compute and data transfer operations for weighted partitions of each layer and dividing the weights into chucks for the processor and using properties of processor based on sizes of the input, weight, and output tensors of each layer of the network. While the applicant points out that tensor dimensions are partitioned, the examiner has relied on the partition of weights of the layer that are divided into chucks for the processors as the partitioning of the weighted node graph as provided in the updated citations which have been added to the mapping in the rejection above to the amended limitation. Furthermore, the calculation of the time for the computing resource of the processor operations is based on the partitions sizes and tensors input and output into the network. Thus, the claimed limitation is taught.
Therefore, all of the limitations of the amended claims 1 and 18 are disclosed in Bokam. Therefore, applicant’s arguments are not persuasive and the rejection of claim 1 and 18 as anticipate by Bokam is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,188,454 B2 Ishizaki, Kazuaki teaches determining a graph representation of a set of neural network training operations to minimize an amount of memory allocated at any one time where the graph is built based on memory usage, execution time for each operation, and weights of the neural network
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner’s Note: The examiner has cited particular columns and line numbers in the reference that applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. In the case of amending the claimed invention, the applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for the proper interpretation and also to verify and ascertain the metes and bound of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Simeon P Drapeau whose telephone number is (571)-272-1173. The examiner can normally be reached Monday - Friday, 8 a.m. - 5 p.m. ET.
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/SIMEON P DRAPEAU/Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188
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