DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/17/2022 and 10/18/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of the Claims
In the claim dated 08/17/2022, claims 1-20 are pending.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claims 1 and 11 recite the limitation: “a first bonding device and a second bonding device … configured to receive the wafers from the first wafer supplier and perform bonding” being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder “device” that is coupled with functional language “receive the wafers from the first wafer supplier and perform bonding” without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Claims 4, 6, 10, 14, 16 and 20 recite the limitation: “the pretreatment device being configured to pretreat and activate the plurality of substrate wafers” being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder “device” that is coupled with functional language “pretreat and activate the plurality of substrate wafers” without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
With regards to the corresponding structure of the claimed “first bonding device and a second bonding device” , Applicant’s Specification, pub.para.0066 discloses: “each of the first bonding device 200A and the second bonding device 200B may include a picker 210, a bonder 220, and a pre-annealing oven 230.”
With regards to the corresponding structure of the claimed “pretreatment device”, Applicant’s Specification, pub.para.0117 discloses: “the first pretreatment device 600A may activate the surface of the substrate wafer W2 by using plasma”. Therefore, the pretreatment device comprises a plasma.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 10, 11, 18 and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ko (US 20060266792 A1)
Regarding claim 1, Ko discloses
A bonding apparatus (see abstract: “multi-chip die bonder”) comprising:
a first wafer supplier (combo 12, 72 and 92, see fig.3) comprising a plurality of load ports (12, 72 and 92) configured to store wafers (11, 74 and 76, see fig.3) having different sizes (see para.0064, 0039: “a substrate 11 in the substrate loading box 12”, “The wafer transfer 70 may transfer the different types of the wafers 73, 75, 93 and 95 from the first wafer cassette 72 and/or the second wafer cassette 92 to the first wafer table 71 and/or the second wafer table 91”. See figs. 3-4, the dies 74-76 and substrate 11 have different sizes),
the wafers (11, 74 and 76, see fig.3) comprising a plurality of substrate wafers (11, see fig.3) and a plurality of die supply wafers (74 and 76, see fig.3) ;
a first transferer (combo 30 and 48, see fig.3) adjacent to the first wafer supplier (combo 12, 72 and 92, see fig.3, at least item 30 (of the combo 30 and 48) is adjacent to the item 12 (of the combo 12, 72 and 92)) and configured to transfer the wafers (11, 74 and 76, see fig.3, see fig.3 and para.0027: “The second transfer unit 48 may transfer the shuttle 50 from the final supplier conveyor 20”) ;
a first bonding device (67, see fig.3) and a second bonding device (87, see fig.3) facing the first wafer supplier (combo 12, 72 and 92) and configured to receive the wafers (11, 74 and 76) from the first wafer supplier (combo 12, 72 and 92) and perform bonding (see figs.2-3 and para.0039: “The first die bonder 67 may separate the first and the third dies 74 and 94 from the first and the third wafers 73 and 93, respectively, and may bond the first and the third dies 74 and 94 to the first adhesive 62 of the substrate 11” and see para.0070: “The second die attaching process may proceed in a similar manner as the first die attaching process. Here, the second die 76 may be attached to the first die 74 using a second die bonder 87 of the second die attaching unit 80. The second die 76 may be attached to an active surface of the first die 74 and located between chip pads 74a of the first die 74”); and
a first cleaner (46, see fig.3) comprising a plurality of cleaning areas (see cleaning areas in annotated fig.3 below), each of which is configured to receive the plurality of substrate wafers (11, see fig.3) and the plurality of die supply wafers (74 and 76) by the first transferer (combo 30 and 48, see fig.3 and para.0078: “the shuttle 50 may be transferred from the fourth area 39 of the first substrate conveyor 30 to the starting section of the second substrate conveyor 20 by the second transfer unit 48. The unloader 44 may separate the substrate 11 from the shuttle 50 and may transfer the substrate 11 to the substrate receiving box 42. A second cleaner 46 may clean the substrate 11 using plasma”. As shown in fig.3, the substrate 11 (“substrate wafers”) bonding to the dies 74, 76, (“die supply wafers”) is cleaned by the plurality of cleaning areas of second cleaner 46) , and clean the plurality of substrate wafers (11) and the plurality of die supply wafers (74 and 76, See fig.3 and para.0078).
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Annotated fig.3 of Ko
Regarding claim 8, Ko further discloses the first wafer supplier (combo 12, 72 and 92, see fig.3) and the first cleaner (46) are on a first side (See first side in annotated fig.3 below) of the bonding apparatus (100, see fig.3) with respect to the first transferer (combo 30 and 38, see fig.3. The item 12 (combo 12, 72 and 92) and the item 46 are on the first side as shown in the annotated fig.3 below), wherein the bonding apparatus (100) further comprises a second wafer supplier (42, see fig.3) facing the first wafer supplier (combo 12, 72 and 92 ) with the first cleaner (46, see fig.3) therebetween, the second wafer supplier (42, see fig.3) comprising a plurality of load ports (see load ports in annotated fig.3 below) configured to store the plurality of substrate wafers (11, see fig.3) and the plurality of die supply wafers (74 and 76) having different sizes (See fig.3), wherein the first bonding device (67, see fig.3) faces the first wafer supplier (12, 72 and 92) with respect to the first transferer (30 and 38, see fig.3, the item 12 (of the combo 12, 72 and 92) faces item 67 with respect to the first transferer 30/38 ), and wherein the second bonding device (87) faces the second wafer supplier (42) with respect to the first transferer (30 and 38, see fig.3).
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Annotated fig.3 of Ko
Regarding claim 10, Ko further discloses a pretreatment device (88, See fig.3) between the first bonding device (67, see fig.3) and the second bonding device (87, see fig.3 and para.0076), the pretreatment device (81, See fig.3) being configured to pretreat and activate the plurality of bonded substrate wafers (see bonded substrate wafers in annotated fig.3 below. see para.0076: “the first and the second adhesive providing units 61 and 81 used in bonding the third and the fourth dies 94 and 96 may be … a tape provider 88 according to the condition of an attaching process”. Thus, the tape provider 88 treats the surface of 94 with the adhesive tape 82 and activates the bonding of the dies 74 and 76) ;
a first maintenance area (See first maintenance area in annotated fig.3 below) in which the first bonding device (67) is spaced apart from the pretreatment device (88) by a predetermined distance (see fig.3); and
a second maintenance area (See second maintenance area in annotated fig.3 below) in which the second bonding device (87) is spaced apart from the pretreatment device (88) by a predetermined distance (see fig.3).
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Annotated fig.3 of Ko
Regarding claim 11, Ko discloses
A bonding apparatus (see abstract: “multi-chip die bonder”) comprising:
a first wafer supplier (combo 12, 72 and 92, see fig.3) comprising a plurality of load ports (12, 72 and 92) configured to store wafers (11, 74 and 76, see fig.3) having different sizes (see para.0064, 0039: “a substrate 11 in the substrate loading box 12”, “The wafer transfer 70 may transfer the different types of the wafers 73, 75, 93 and 95 from the first wafer cassette 72 and/or the second wafer cassette 92 to the first wafer table 71 and/or the second wafer table 91”. See figs. 3-4, the dies 74-76 and substrate 11 have different sizes),
the wafers (11, 74 and 76, see fig.3) comprising a plurality of substrate wafers (11, see fig.3) and a plurality of die supply wafers (74 and 76, see fig.3) ;
a first transferer (combo 30 and 48, see fig.3) adjacent to the first wafer supplier (combo 12, 72 and 92, see fig.3, at least item 30 (of the combo 30 and 48) is adjacent to the item 12 (of the combo 12, 72 and 92)) and configured to transfer the wafers (11, 74 and 76, see fig.3, see fig.3 and para.0027: “The second transfer unit 48 may transfer the shuttle 50 from the final section of the first substrate conveyor 30 to the starting section of the second substrate conveyor 20”) ;
a first bonding device (67, see fig.3) and a second bonding device (87, see fig.3) facing the first wafer supplier (combo 12, 72 and 92) and configured to receive the wafers (11, 74 and 76) from the first wafer supplier (combo 12, 72 and 92) and perform bonding (see figs.2-3 and para.0039: “The first die bonder 67 may separate the first and the third dies 74 and 94 from the first and the third wafers 73 and 93, respectively, and may bond the first and the third dies 74 and 94 to the first adhesive 62 of the substrate 11” and see para.0070: “The second die attaching process may proceed in a similar manner as the first die attaching process. Here, the second die 76 may be attached to the first die 74 using a second die bonder 87 of the second die attaching unit 80. The second die 76 may be attached to an active surface of the first die 74 and located between chip pads 74a of the first die 74”);
a first cleaner a first cleaner (46, see fig.3) comprising a plurality of cleaning areas (see cleaning areas in annotated fig.3 below), each of which is configured to receive the plurality of substrate wafers (11, see fig.3) and the plurality of die supply wafers (74 and 76) by the first transferer (combo 30 and 48, see fig.3 and para.0078: “the shuttle 50 may be transferred from the fourth area 39 of the first substrate conveyor 30 to the starting section of the second substrate conveyor 20 by the second transfer unit 48. The unloader 44 may separate the substrate 11 from the shuttle 50 and may transfer the substrate 11 to the substrate receiving box 42. A second cleaner 46 may clean the substrate 11 using plasma”. As shown in fig.3, the substrate 11 (“substrate wafers”) bonding to the dies 74, 76, (“die supply wafers”) is cleaned by the plurality of cleaning areas of second cleaner 46) , and clean the plurality of substrate wafers (11) and the plurality of die supply wafers (74 and 76, See fig.3 and para.0078),
and a second wafer supplier (50, see fig.3, which supplies the wafers to the substrate receiving box 42 (see para.0078) . See second wafer supplier in annotated fig.3 below) facing the first cleaner (46, see fig.3) and comprising a plurality of load ports (see load ports in annotated fig.3 below) configured to store the plurality of substrate wafers (11, see fig.3) and the plurality of die supply wafers ((74 and 76, see fig.3) having different sizes (See fig.3).
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Annotated fig.3 of Ko
Regarding claim 18, Ko further discloses the first wafer supplier (12, 72 and 92) and the first cleaner (46, see fig.3) are on a first side (see first side in annotated fig.3 below) of the bonding apparatus (100) with respect to the first transferer (combo 30 and 38), wherein the first bonding device (67) faces the first wafer supplier with respect to the first transferer (30 and 38, see fig.3, the item 12 (of the combo 12, 72 and 92) faces item 67 with respect to the first transferer 30/38 ), and wherein the second bonding device (87), and wherein the second bonding device (87) faces the second wafer supplier (see second wafer in annotated fig.3 above in rejection of claim 11) with respect to the first transferer (30 and 38, see fig.3).
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Annotated fig.3 of Ko
Regarding claim 20, Ko further discloses a pretreatment device (88, See fig.3) between the first bonding device (67, see fig.3) and the second bonding device (87, see fig.3 and para.0076), the pretreatment device (81, See fig.3) being configured to pretreat and activate the plurality of bonded substrate wafers (see bonded substrate wafers in annotated fig.3 below. see para.0076: “the first and the second adhesive providing units 61 and 81 used in bonding the third and the fourth dies 94 and 96 may be … a tape provider 88 according to the condition of an attaching process”. Thus, the tape provider 88 treats the surface of 94 with the adhesive tape 82 and activates the bonding of the dies 74 and 76) ;
a first maintenance area (See first maintenance area in annotated fig.3 below) in which the first bonding device (67) is spaced apart from the pretreatment device (88) by a predetermined distance (see fig.3); and
a second maintenance area (See second maintenance area in annotated fig.3 below) in which the second bonding device (87) is spaced apart from the pretreatment device (88) by a predetermined distance (see fig.3).
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Annotated fig.3 of Ko
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4, 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koi in view of Yoon (US20040211665A1)
Regarding claim 2, Ko further discloses each of the first bonding device (67, see figs.2-3) and the second bonding device (87, see figs.2-3) comprises:
a bonder (67/87) configured to bond dies (74 or 76) from the plurality of die supply wafers (74 and 76) to the plurality of substrate wafers (11, see fig.3 and para.0051: “the first die 74 and the second die 76 may be stacked on the substrate 11”), respectively (see fig.3 and para.0051).
Ko does not expressly disclose a pre-annealing oven configured to pre-anneal the plurality of bonded substrate wafers, and wherein the first transferer is configured to transfer the plurality of pre-annealed substrate wafers to an annealing chamber for secondary annealing.
However, Yoon discloses the fabrication of semiconductor devices, comprising:
a pre-annealing oven ( 36, see para.0108) configured to pre-anneal the plurality of bonded substrate wafers (“see para.0108: “the metal layer … deposited on a silicon substrate in chamber 36, annealed at a first temperature for a first period of time”. Thus, in the modification of Ko in view of Yoon, the first anneal chamber of Yoon configured to pre-anneal the plurality of bonded substrate wafers of Ko ), and wherein the first transferer (transfer robot 49/51, see fig.1) is configured to transfer the plurality of pre-annealed substrate wafers to an annealing chamber for secondary annealing (see para.0108 of Yoon: “the metal layer … deposited on a silicon substrate in chamber 36, annealed at a first temperature for a first period of time, transferred to a second chamber, for example chamber 41, in the system 35, and annealed at a second temperature for a second period of time “).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Ko to incorporate the pre-annealing oven and first transferer of Yoon so as the “pre-annealing oven configured to pre-anneal the plurality of bonded substrate wafers, and wherein the first transferer is configured to transfer the plurality of pre-annealed substrate wafers to an annealing chamber for secondary annealing” as claimed. Doing so allows to create strong, reliable bonds by removing contaminants, relieving stress, and ensuring the bonded wafers function correctly.
Regarding claim 4, Ko further discloses a pretreatment device (88, See fig.2) between the first bonding device (67, see fig.2) and the second bonding device (87, see fig.2 and para.0076), the pretreatment device (81, See fig.2) being configured to pretreat and activate the plurality of substrate wafers (see para.0076: “the first and the second adhesive providing units 61 and 81 used in bonding the third and the fourth dies 94 and 96 may be … a tape provider 88 according to the condition of an attaching process”. Thus, the tape provider 88 treats the surface of 94 with the adhesive tape 82 and activates the bonding of the dies 74 and 76).
Regarding claim 12, Ko further discloses each of the first bonding device (67, see figs.2-3) and the second bonding device (87, see figs.2-3) comprises:
a bonder (67/87) configured to bond dies (74 or 76) from the plurality of die supply wafers (74 and 76) to the plurality of substrate wafers (11, see fig.3 and para.0051: “the first die 74 and the second die 76 may be stacked on the substrate 11”), respectively (see fig.3 and para.0051).
Ko does not expressly disclose
a pre-annealing oven configured to pre-anneal the plurality of bonded substrate wafers, and wherein the first transferer is configured to transfer the plurality of pre-annealed substrate wafers to an annealing chamber for secondary annealing.
However, Yoon discloses the fabrication of semiconductor devices, comprising:
a pre-annealing oven ( 36, see para.0108) configured to pre-anneal the plurality of bonded substrate wafers (“see para.0108: “the metal layer … deposited on a silicon substrate in chamber 36, annealed at a first temperature for a first period of time”. Thus, in the modification of Ko in view of Yoon, the first anneal chamber of Yoon configured to pre-anneal the plurality of bonded substrate wafers of Ko ), and wherein the first transferer (transfer robot 49/51, see fig.1) is configured to transfer the plurality of pre-annealed substrate wafers to an annealing chamber for secondary annealing (see para.0108 of Yoon: “the metal layer … deposited on a silicon substrate in chamber 36, annealed at a first temperature for a first period of time, transferred to a second chamber, for example chamber 41, in the system 35, and annealed at a second temperature for a second period of time “).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified Ko to incorporate the pre-annealing oven and first transferer of Yoon so as the “pre-annealing oven configured to pre-anneal the plurality of bonded substrate wafers, and wherein the first transferer is configured to transfer the plurality of pre-annealed substrate wafers to an annealing chamber for secondary annealing” as claimed. Doing so allows to create strong, reliable bonds by removing contaminants, relieving stress, and ensuring the bonded wafers function correctly.
Regarding claim 14, Ko further discloses a pretreatment device (88, See fig.2) between the first bonding device (67, see fig.2) and the second bonding device (87, see fig.2 and para.0076), the pretreatment device (81, See fig.2) being configured to pretreat and activate the plurality of substrate wafers (see para.0076: “the first and the second adhesive providing units 61 and 81 used in bonding the third and the fourth dies 94 and 96 may be … a tape provider 88 according to the condition of an attaching process”. Thus, the tape provider 88 treats the surface of 94 with the adhesive tape 82 and activates the bonding of the dies 74 and 76).
Claims 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koi in view of Baek (US 20220344196 A1)
Regarding claim 5, Ko further discloses the first wafer supplier (combo 50, 71 and 91) is on a first side (see first side in annotated fig.3 below) of the bonding apparatus (100, see fig.2) with respect to the first transferer (combo 30 and 48, see fig.2), and the first bonding device (67) and the second bonding device (87) are on a second side (see second side in annotated fig.3 below) of the bonding apparatus (100) opposite to the first side (see first side in annotated fig.3 below), wherein the bonding apparatus (100) further comprises a second transferer (70, see fig.2) spaced apart from the first transferer (combo 30 and 48, see fig.2), wherein the first cleaner (46, see fig.3) is on a first side with respect to the second transferer (see first side with respect to the second transferer in annotated fig.3 below), and wherein the bonding apparatus (100) further comprises a second wafer supplier (42, see fig.3) facing the first cleaner (46, see fig.3), and comprising a plurality of load ports (see load ports in annotated fig.3 below) configured to store the plurality of substrate wafers (12) and the plurality of die supply wafers (74 and 76) having different sizes (See fig.3 and para.0035: “ The substrate 11 may be transferred from the shuttle 50 to the substrate receiving box 42 by the unloader 44”).
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Ko discloses the second transferer (70, see fig.2) and the first transferer (combo 30 and 48, see figs.2-3).
However, Ko does not expressly disclose
the second transferer comprising a mobile robot connected to mobile robots included in the first transferer.
Baek discloses a wafer processing apparatus and a wafer processing method, comprising:
the second transferer (500 on the left side, see fig.1) comprising a mobile robot (500) connected to mobile robots (500 on the right side, see fig.1) included in the first transferer (500 on the right side, see fig.1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the first and second transferers of Ko to have mobile robot(s) as taught by Baek so as “the second transferer comprising a mobile robot connected to mobile robots included in the first transferer”. as taught by Baek. Doing so provides vibration-free handling, preventing chipping, cracking, or misalignment of fragile wafers.
Regarding claim 15, Ko further discloses the first wafer supplier (combo 50, 71 and 91) is on a first side (see first side in annotated fig.3 below) of the bonding apparatus (100, see fig.2) with respect to the first transferer (combo 30 and 48, see fig.2), and the first bonding device (67) and the second bonding device (87) are on a second side (see second side in annotated fig.3 below) of the bonding apparatus (100) opposite to the first side (see first side in annotated fig.3 below), wherein the bonding apparatus (100) further comprises a second transferer (70, see fig.2) spaced apart from the first transferer (combo 30 and 48, see fig.2), wherein the first cleaner (46, see fig.3) is on a first side with respect to the second transferer (see first side with respect to the second transferer in annotated fig.3 below).
except the second transferer comprising a mobile robot connected to mobile robots included in the first transferer.
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Ko discloses the second transferer (70, see fig.2) and the first transferer (combo 30 and 48, see figs.2-3).
However, Ko does not expressly disclose
the second transferer comprising a mobile robot connected to mobile robots included in the first transferer.
Baek discloses a wafer processing apparatus and a wafer processing method, comprising:
the second transferer (500 on the left side, see fig.1) comprising a mobile robot (500) connected to mobile robots (500 on the right side, see fig.1) included in the first transferer (500 on the right side, see fig.1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the first and second transferers of Ko to have mobile robot(s) as taught by Baek so as “the second transferer comprising a mobile robot connected to mobile robots included in the first transferer”. as taught by Baek. Doing so provides vibration-free handling and prevents chipping, cracking, or misalignment of fragile wafers.
Claims 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koi in view of Harris (US 20220262653 A1)
Regarding claim 6, the modification discloses substantially all the claimed limitations as set forth, except a pretreatment device adjacent to the first cleaner and facing the second wafer supplier, and configured to pretreat and activate the plurality of bonded substrate wafers.
Harris discloses Methods and apparatus for bonding chiplets to substrates, comprising:
a pretreatment device (130a/b, see fig.2) adjacent to the first cleaner (122a/b, see fig.2) and facing the second wafer supplier (102, see fig.2), and configured to pretreat and activate the plurality of bonded substrate wafers (bonded substrate wafers of Ko. see para.0058 of Harris).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the pretreatment device of Harris into the combo Ko and Baek so as the “pretreatment device adjacent to the first cleaner and facing the second wafer supplier, and configured to pretreat and activate the plurality of bonded substrate wafers” as taught by Harris. Doing so allows to perform a plasma etch process to remove unwanted material from the substrates (see para.0060 of Harris).
Regarding claim 16, the modification discloses substantially all the claimed limitations as set forth, except a pretreatment device adjacent to the first cleaner and facing the second wafer supplier, and configured to pretreat and activate the plurality of bonded substrate wafers.
Harris discloses Methods and apparatus for bonding chiplets to substrates, comprising:
a pretreatment device (130a/b, see fig.2) adjacent to the first cleaner (122a/b, see fig.2) and facing the second wafer supplier (102, see fig.2), and configured to pretreat and activate the plurality of bonded substrate wafers (bonded substrate wafers of Ko. see para.0058 of Harris).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the pretreatment device of Harris into the combo Ko and Baek so as the “pretreatment device adjacent to the first cleaner and facing the second wafer supplier, and configured to pretreat and activate the plurality of bonded substrate wafers” as taught by Harris. Doing so allows to perform a plasma etch process to remove unwanted material from the substrates (see para.0060 of Harris).
Allowable Subject Matter
Claims 3, 7, 9, 13, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20220052017 A1 discloses A die bonding apparatus includes: a driven body; and a table for driving the driven body. The table includes: a base; a linear motor having a first mover that moves the driven body, and a stator; a first linear motion guide that is provided between the base and the stator and capable of freely moving the stator; a second linear motion guide that is provided between the base and the first mover and capable of freely moving the first mover; a second mover provided in the form of being fixed to the base; and a control device for controlling the first mover and the second mover. The control device is configured to move the stator along the first linear motion guide using the second mover.
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/TIFFANY T TRAN/ Primary Examiner, Art Unit 3761