DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 2, as shown in FIG. 6B, and which encompass claims 11-25 in the reply filed on 04/29/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 and 19 recites “the entire display device” lack antecedent basis. It is unclear and indefinite the entire display device is one OLED, or pixel array of an array of pixel array?
Claims 11 and 19 recites “uniform pitch”, the term “uniform” is a relative term which renders the claim indefinite. The term “uniform” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Note that uniformity has a defined specification of average +/3 sigma. As such the claim is unclear and indefinite.
Claim 11 recites “uniform pitch”, the term “uniform” is a relative term which renders the claim indefinite. The term “uniform” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Note that uniform has a defined specification of average +/3 sigma. As such the claim is unclear and indefinite.
Claim19 recites “non-uniform spacing”, the term “non-uniform” is a relative term which renders the claim indefinite. The term “non-uniform” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Note that non-uniformity has a defined specification of average +/3 sigma. As such the claim is unclear and indefinite.
Claim 12 recites “the plurality of pads” lacks antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 13-15, 17-22 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. 20090033597 in view of Martin et al. 20080128698.
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Regarding claim 11, figs. 1-4 of Sung discloses a method of fabricating an organic light-emitting diode (OLED) display device, the method comprising: fabricating a plurality of pixel arrays (fig. 4 above and fig. 1 an array) on a substrate 1000, wherein the plurality of pixel arrays defines a backplane pixel array that includes at least one stitching boundary 1100 (see fig. 4 showing 1100 which is a scribe line which is a boundary that stitches the pixel in arrays of fig. 4) residing between at least two pixel arrays of the plurality of pixel arrays; and
forming an OLED emitter array (OLED - see par [0020], [0021], [0039] and fig. 1 showing for each of 150 which has an OLED and fig. 1 forms an emitter array) on the backplane pixel array,
wherein each OLED emitter of the OLED emitter array is electrically connected to a different pixel circuit [each OLED is connected to a driving TFT and see par [0034] – TFT and see claims 14 and 19 of Sung] of the backplane pixel array, and
wherein the OLED emitter array has uniform pitch (the distance between each 150 is pitch as claimed) across the entire display device (display region 102 in fig. 1).
Sung does not disclose of providing a reticle that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit.
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However, fig. 2 of Martin discloses a method of fabricating Many Million Pixel Image Sensor, the method comprising providing a reticle (fig. 1 Mask and fig. 2 reticle) that includes a primary sub-block (pixel core shown in fig. 1 of Martin) for forming a pixel array, each pixel of the array including a pixel circuit and fabricating a plurality of pixel arrays on a substrate (wafer) using the reticle.
Note that producing fig. 4 of Sung would require forming a reticle of that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit and stepping and repeating as taught by Martin.
In view of such teaching, it would have been obvious to form a method of Sung further comprising providing a reticle that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit and fabricating a plurality of pixel arrays on a substrate using the reticle such as taught by Martin in order to mass produce OLED display device instead of just one.
Regarding claim 19 (see rejection of claim 1 above), Sung discloses a method of fabricating an organic light-emitting diode (OLED) display device, the method comprising:
fabricating a plurality of pixel arrays on a substrate, wherein the plurality of pixel arrays defines a backplane pixel array that includes at least one stitching boundary residing between at least two pixel arrays of the plurality of pixel arrays such that the pixels of the backplane pixel array are arranged with non-uniform spacing (the spacing diagonally is different from left to right and different from top to bottom in fig. 1 of Sung) across the display device; and
forming an OLED emitter array on the backplane pixel array,
wherein each OLED emitter of the OLED emitter array is electrically connected to the first thin-film transistor of a different pixel circuit of the backplane pixel array, and
wherein the OLED emitter array has uniform pitch across the entire display device.
Sung does not discloses of providing a reticle that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit that includes a first thin-film transistor for driving an OLED.
However, fig. 2 of Martin discloses a method of fabricating Many Million Pixel Image Sensor, the method comprising providing a reticle (fig. 1 Mask and fig. 2 reticle) that includes a primary sub-block (pixel core shown in fig. 1 of Martin) for forming a pixel array, each pixel of the array including a pixel circuit and fabricating a plurality of pixel arrays on a substrate (wafer) using the reticle.
Note that producing fig. 4 of Sung would require forming a reticle of that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit that includes a first thin-film transistor for driving an OLED and stepping and repeating as taught by Martin.
In view of such teaching, it would have been obvious to form a method of Sung further comprising providing a reticle that includes a primary sub-block for forming a pixel array, each pixel of the array including a pixel circuit that includes a first thin-film transistor for driving an OLED and fabricating a plurality of pixel arrays on a substrate using the reticle such as taught by Martin in order to mass produce OLED display device instead of just one.
Regarding claims 13 and 21, Sung discloses wherein the pixel array is configured in an active matrix.
Regarding claim 14, it would have been obvious to form a method comprising wherein the reticle is used to define the pixel array and a plurality of wiring pads in order to form interconnection to the array.
Regarding claim 20, Sung discloses further comprising: two secondary sub-blocks 210/220; an interconnect region 104 having a sub-pixel driving array (array of 210/210) on the substrate using the two secondary sub-blocks, wherein the sub-pixel driving array includes two or more metal layers (The gate electrode 114a and the inspection signal line 114c can be formed of polysilicon or metal) and a plurality of sub-pixel drivers; and attaching the plurality of pads 120 to the two or more metal layers.
As such it would have been obvious to form a method further comprising providing the reticle such that it includes two secondary sub-blocks; fabricating an interconnect region having a sub-pixel driving array on the substrate using the two secondary sub-blocks of the reticle, wherein the sub-pixel driving array includes two or more metal layers and a plurality of sub-pixel drivers; and attaching the plurality of pads to the two or more metal layers in order to form drivers and interconnection to the pixels/pixel array.
Regarding claim 15, it would have been obvious to form a method comprising wherein the pixel array includes two transistors in order have transistor per array and it would have been obvious to form a method comprising an inverted organic light-emitting diode stack in order that a metal cathode is formed on the substrate and an anode is formed above the organic light emitting materials.
Regarding claim 22, it would have been obvious to form a method wherein each OLED of the OLED emitter array is formed such that it is configured as an inverted organic light-emitting diode stack in order that a metal cathode is formed on the substrate and an anode is formed above the organic light emitting materials.
Regarding claims 17 and 24, it would have been obvious to form a method wherein the pixel array has a resolution of at least 2,000 pixels per inch in order to have a higher resolution display.
Regarding claims 18 and 25, it would have been obvious to form a method comprising wherein the display device has a panel size of at least 35 mm per side in order to meet the applicant’s device size specification.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sung and Martin in view of Applicant prior Art (figs. 1-2).
Regarding claim 12, Sung discloses further comprising: two secondary sub-blocks 210/220; an interconnect region 104 having a sub-pixel driving array (array of 210/210) on the substrate using the two secondary sub-blocks, wherein the sub-pixel driving array includes two or more metal layers (The gate electrode 114a and the inspection signal line 114c can be formed of polysilicon or metal) and a plurality of sub-pixel drivers; and attaching the plurality of pads 120 to the two or more metal layers.
As such it would have been obvious to form a method further comprising providing the reticle such that it includes two secondary sub-blocks; fabricating an interconnect region having a sub-pixel driving array on the substrate using the two secondary sub-blocks of the reticle, wherein the sub-pixel driving array includes two or more metal layers and a plurality of sub-pixel drivers; and attaching the plurality of pads to the two or more metal layers in order to form drivers and interconnection to the pixels/pixel array.
Sung and Martin do not disclose by the anisotropic conductive film.
However, FIGS. 1A and 1B of applicant illustrates a conventional mobile display panel 100 used in virtual reality applications. The panel 100 consists of a polysilicon thin-film-transistor (TFT) 104 on glass backplane 102, with an OLED layer 106 deposited on top. Preferably, the OLED layer 106 is a side-by-side color architecture with each color stack evaporated through a fine metal mask. Separate driver integrated circuits (ICs) 108 are attached to the glass substrate using an anisotropic adhesive film (ACF) layer 110. Separate flexible printed circuits (FPCs) 112 are attached to the glass substrate using an anisotropic adhesive film (ACF) layer 114.
As such it would have been obvious to form a method further comprising attaching the plurality of pads to the two or more metal layers by the anisotropic conductive film in order to make electrical connection.
Claims 16 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Sung and Martin in view of ROH 20140307004.
Regarding claims 16 and 23, Sung and Martin do not discloses wherein at least one transistor is a high voltage n-channel metal-oxide silicon (NMOS) device or a lateral double-diffused metal-oxide-silicon (LDMOS) device.
However, par [0058] In brief, the OLED display 100 having the demultiplexing structure may allow for a sufficient driving time during which respective source voltages corresponding to respective data signals are changed by controlling the data driving unit 130 to begin outputting the data signals (e.g., the first data signal and the third data signal) before one horizontal period (1H) begins. On this basis, the OLED display 100 may display a high-quality image. Although it is illustrated in FIG. 2 that the first through fourth switches T1, T2, T3, and T4 are implemented by p-type metal-oxide semiconductor (PMOS) transistors, an implementation of the first through fourth switches T1, T2, T3, and T4 is not limited thereto. For example, the first through fourth switches T1, T2, T3, and T4 may be implemented by various transistors such as n-type metal-oxide semiconductor (NMOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, etc. In another embodiment, at least one of the switches T1-T4 can be a junction FET (JFET), a metal-semiconductor FET (MESFET), a modulation-doped FET (MODFET), a metal-oxide-semiconductor FET (MOSFET), an n-channel MOSFET (NMOSFET), a p-channel MOSFET (PMOSFET) and an organic FET (OFET). At least one of the switches T1-T4 may also include bipolar transistors. At least one of the switches T1-T4 may further include other switching devices such as digital or analog switches or a relay.
As such it would have been obvious to form a method comprising wherein at least one transistor is a high voltage n-channel metal-oxide silicon (NMOS) device such as taught by ROH in order to form a switching transistor requiring higher driving voltage
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893