DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The amendment filed 3/9/26 has been filed. Claims 1-19 and 21 are pending.
3. In view of the amendment, the 101 rejection has been removed.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. §102 and §103 (or as subject to pre-AIA 35 U.S.C. §102 and §103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. §102(b)(2)(C) for any potential 35 U.S.C. §102(a)(2) prior art against the later invention.
Claims 1-4, 9-10, 12-14, 18, and 21 are rejected under 35 U.S.C. §103 as being unpatentable over Jung et al. (US 2022/0114427), hereinafter Jung, and further in view of Ito et al. (US 2023/0176818), hereinafter Ito.
Claim 1
“A device, comprising: input circuitry; weight operation circuitry electrically connected to the input circuitry” Jung [0044], [0052], [0059], [0070], [0074], [0078] teach a neural network operation comprising memory cells and resistances corresponding to the weights, when voltage corresponding to an input activation is applied to each of the plurality of word lines and transistors can be turned on or turned off to control the supply of current to the variable resistance element, as well as other word and column line input circuitry; Jung [0042], [0043], [0052], [0060] teach at least weight filters which are physical circuits and weighted channel circuitry such as through resistance circuits, which are connected to channel input lines.
“bias operation circuitry electrically connected to the weight operation circuitry” Jung [0078] teaches a neural network operation comprising memory cells and resistances corresponding to weights, currents are output from memory cells arranged along one column circuit, summation currents and output along the plurality of bit lines; Jung [0052], [0053] teach bias connection valves and channel bias which connect with the weighted channel lines.
“storage circuitry electrically connected to the weight operation circuitry and the bias operation circuitry” Jung [0089] teaches when the neural network operation is performed, the column circuit may be connected to one the bit line and output the summation current and a weight value stored in each memory cell; Jung Figure 8, [0060], [0072], [0091], [0111] further teach column circuits and memory circuits for storing weight values and which are connected to [weighted] channel lines.
“activation function circuitry electrically connected to the bias operation circuitry” Jung [0053], [0054] teach activation function channel lines which connect to the channel bias.
Jung does not explicitly teach “wherein at least the weight operation circuitry, the bias operation circuitry, and the storage circuitry are located on a same chip” Ito [0077], [[0111], [0120], [0294], [0295] teach a System on Chip semiconductor chip integrated circuit. The integrated circuit includes storage, bias, and weight operation circuits. See also Ito [0059-0062] which show the storage circuit with switching circuits (including product-sum operation circuits) capable of bias and weight functions.
Jung and Ito disclose analogous art. Jung teaches weight, bias, storage, and activation function circuitries and Ito shows “weight, bias, and storage operation circuitry on one chip” as explained above. Hence, it would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to have the weight operation circuitry, the bias operation circuitry, and the storage circuitry all located on the same chip, because it would provide and efficient way to interconnect and process the circuitry together. Doing so using the technique of Ito would also reduce power consumption needs (Ito [0294]).
Claim 2
“wherein the weight operation circuitry comprises first weight operation circuitry and second weight operation circuitry” Jung [0078][0113] teaches spreading the weight value of one memory cell to the remaining memory cells, when data “1” and “0” is stored in the first memory cell, current may flow in the direction of an arrow that data “1” can be stored in the first memory cell, the weight value stored in the second memory cell may be stored in the third memory cell and the fourth memory cell in the same manner,
“wherein the storage circuitry comprises first storage circuitry electrically connected to the first weight operation circuitry, second storage circuitry electrically connected to the second weight operation circuitry, and third storage circuitry electrically connected to the bias operation circuitry” Jung [0078][0113] teaches the first weight and the second weight connected, and second and third storage connected to summation operation circuit.
Claim 3
“wherein the weight operation circuitry comprises first weight operation circuitry and second weight operation circuitry, and wherein the storage circuitry is electrically connected to the first weight operation circuitry, the second weight operation circuitry, and the bias operation circuitry” Jung [0078][0113] teaches the first weight and the second weight connected, and second and third storage connected to summation operation circuit.
Claim 4
“wherein the storage circuitry comprises one or more storage bits” Jung [0078] teaches a neural network operation comprising memory cells and resistances corresponding to the weights, currents are output from memory cells arranged along one column circuit, summation currents and output along the plurality of bit lines.
Claim 9
“wherein the device comprises a hardware neuron in an artificial neural network” Jung [0050] shows the neuron channel processing elements that are hardware implemented nodes of the neural network.
Claim 10
“output circuitry electrically connected to the activation function circuitry” Jung [0078] teaches a neural network operation comprising memory cells and resistances corresponding to the weights, when voltage corresponding to an input activation is applied to each of the plurality of word lines and resistances corresponding to weights, currents are output from memory cells arranged along one column circuit, summation currents and output along the plurality of bit lines.
Claims 12-14 & 18
Claims 12-14, and 18 are rejected for the similar rationale given for claims 1-3, and 10 respectively.
Claim 21
Claim 21 is rejected for the similar rationale given for claim 1. Additionally, note that Jung [0044], [0052], [0059], [0070], [0074], [0078] teach the multiple/plurality of input activation and column line input circuitry, and Jung [0042], [0043], [0052], [0060] teach a plurality of weight filters which are physical circuits and weighted channel circuitry such as through resistance circuits, which are connected to channel input lines.
Claims 5-6 and 15-16 are rejected under 35 U.S.C. §103 as being unpatentable over Jung et al. (US 2022/0114427), hereinafter Jung, and further in view of Ito et al. (US 2023/0176818), hereinafter Ito, and Shainline (US 2020/0301874), hereinafter Shainline.
Claim 5
“wherein the one or more storage bits each comprise one or more resistive elements and a voltage amplifier” Shainline [0031][0037] teaches dendritic integration resistor and superconducting voltage amplifier in communication with dendritic integrated current.
Jung, Ito, and Shainline disclose analogous art. Jung teaches weight, bias, storage, and activation function circuitries. Ito teaches locating all circuitries on a same chip. However, Jung in combination with Ito does not teach the “resistive elements and a voltage amplifier” feature as recited above. Said feature is taught in Shainline. Hence, it would have been obvious to one ordinary skilled in the art at the time the present invention was made to incorporate said feature of Shainline into Jung in combination with Ito to enhance its storage functions with more resistive elements and a voltage amplifier.
Claim 6
“wherein the one or more resistive elements comprise at least four resistive elements, wherein at least two first resistive elements are electrically connected in series and at least two second resistive elements are electrically connected in series, wherein the at least two first resistive elements are electrically connected in parallel to the at least two second resistive elements” Shainline Figure 10 illustrates resistive elements connected in series 201 and more than one synapse connected in parallel;
“wherein an input of the voltage amplifier is electrically connected to a first electrode between the at least two first resistive elements and to a second electrode between the at least two second resistive elements” Shainline Figure 9 & [0037] teaches amplifier 480 connected to electronic dendrite 342 output signal.
Claims 15-16
Claims 15 and 16 are rejected for the similar rationale given for claims 5 and 6 respectively.
Claim 7 is rejected under 35 U.S.C. §103 as being unpatentable over Jung et al. (US 2022/0114427), hereinafter Jung, and in view of Ito et al. (US 2023/0176818), hereinafter Ito, and further in view of Shainline (US 2020/0301874), hereinafter Shainline, and Woo et al. (US 2022/0359617), hereinafter Woo.
Claim 7
“wherein each of the one or more resistive elements comprise a magnetic tunnel junction (MTJ)” Woo [0003] teaches a magnetic tunnel junction(MTJ) structure of a resistive memory device.
Jung, Ito, Shainline, and Woo disclose analogous art. Jung teaches weight, bias, storage, and activation function circuitries. Ito teaches locating all circuitries on a same chip. Shainline teaches resistive elements and a voltage amplifier. However, Jung in combination with Ito and Shainline does not teach the “magnetic tunnel junction” as recited above. Said feature is taught in Woo. Hence, it would have been obvious to one ordinary skilled in the art at the time the present invention was made to incorporate said feature of Woo into Jung in combination with Ito and Shainline to further enhance its storage functions with a magnetic tunnel junction as one of the resistive elements.
Claims 8, 11, 17, and 19 rejected under 35 U.S.C. §103 as being unpatentable over Jung et al. (US 2022/0114427), hereinafter Jung, and in view of Ito et al. (US 2023/0176818), hereinafter Ito, and further in view of Woo et al. (US 2022/0359617), hereinafter Woo.
Claim 8
“wherein the one or more storage bits are included in a single array of bits” Woo [0030][0031] teaches multiple control lines including source lines and bit lines, and various blocks connected in the 2D array of RPU cells, which are configured to perform vector-matrix multiply functions.
Jung, Ito, and Woo disclose analogous art. Jung teaches weight, bias, storage, and activation function circuitries. Ito teaches locating all circuitries on a same chip. However, Jung in combination with Ito does not teach the “one or more storage bits included in a single array of bits” feature as recited above. Said feature is taught in Shainline. Hence, it would have been obvious to one ordinary skilled in the art at the time the present invention was made to incorporate said feature of Woo into Jung in combination with Ito to further enhance its storage functions with array of bit lines control operations.
Claim 11
“wherein each of the one or more storage bits comprises: a first set of resistive elements and a second set of resistive elements, first read circuitry electrically connected to the first set of resistive elements and second read circuitry electrically connected to the second set of resistive elements, cross-coupled inverter circuitry electrically connected to the first read circuitry and the second read circuitry, and third read circuitry electrically connected to the cross-coupled inverter circuitry” Jung [0063], [0078], [0091] show the sets of resistive elements connected with the read line circuitry. Jung does not teach the cross-coupled inverter circuitry. Woo [0020], [0026] teaches a circuit structure with inverters with cross-points, and read/sensing operations, e.g., read a weight value of given RPU cell. It would have been obvious to one ordinary skilled in the art at the time the present invention was made to incorporate the inverter circuitry of Woo into Jung in combination with Ito, because it would efficiently implement high speed read operation using resistive elements.
Claims 17 & 19
Claims 17 and 19 are rejected for the similar rationale given for claims 8 and 11 respectively.
Response to Arguments
5. Applicant's arguments filed 3/9/26 have been fully considered but they are not persuasive. Applicant argues that paragraphs 78 and 89 of Jung do not show the claimed features of weight operation circuitry electrically connected to the input circuitry; bias operation circuitry electrically connected to the weight operation circuitry; storage circuitry electrically connected to the weight operation circuitry and the bias operation circuitry; and activation function circuitry electrically connected to the bias operation circuitry. However, in response the Action now cites several different paragraphs of Jung and explains how those paragraphs teach the claimed features. The cited paragraphs show how the circuitries connect, for example through the channel lines and column lines. Please note that the Action now explains how Jung additionally teaches the activation function circuitry. Applicant argues that Ito does not show the multiple switching circuits but note besides showing what is called a switching circuit, Ito also shows a product-sum operation circuit which is a type of switching circuit.
Conclusion
6. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
a) Sudo (US 2019/0238092 A1) shows an integrated circuit with input, bias, storage, and activation function circuitry.
b) Timofejevs (WO 2021259482 A1) shows integrated circuit hardware for neural networks containing input, bias, storage, and activation function circuitry, and which also uses inverter circuitry.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN PAUL SAX whose telephone number is (571)272-4072. The examiner can normally be reached Monday - Friday, 9:30 - 6:00 Est.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Usmaan Saeed, can be reached at 571-272-4046. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN P SAX/ Primary Examiner, Art Unit 2146
Prosecution Insights