DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 05/20/2026.
Claim Objections
Claim 23 is objected to because of the following informalities: Claim 23, line 7 recites “the first power input”, which should be -- the second power input – because in this way is supported in Figures 4 and 5, parts 402/502 and based on the next claimed limitation of claim 24.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 9,859,883), in view of Hashim (US 2020/0144925).
Regarding claim 1, Huang discloses (see figures 1-7) an apparatus (figure 2) comprising: a first transistor (figure 2, part 51) having first and second terminals and a control terminal (figure 2, part 51; terminals), the first terminal of the first transistor (figure 2, part 51; upper terminal) coupled to a switching terminal (figure 2, part switching terminal at upper terminal of 51); a second transistor (figure 2, part 52) having first and second terminals and a control terminal (figure 2, part 52; terminals), the first terminal of the second transistor (figure 2, part 52; upper terminal) coupled to the second terminal of the first transistor (figure 2, part 51; lower terminal), the second terminal of the second transistor (figure 2, part 52; lower terminal) coupled to a first voltage terminal (figure 2, part first voltage terminal at lower terminal of 52); a first driver (figure 2, part 10) having an input (figure 2, part 10; left input), a supply terminal (figure 2, part 10; upper supply terminal), a reference terminal (figure 2, part 10; lower reference terminal), and an output (figure 2, part 10; output terminal), the output of the first driver (figure 2, part 10; right output) coupled to the control terminal of the first transistor (figure 2, part 51; control terminal) (column 4; lines 40-51; The driver circuit 10 includes a comparator 12, a level shift circuit 14, a pre-driving circuit 16 and an inverter 18. The comparator 12 receives the driving input signal SU and determines a logic level of the driving input signal SU. The level shift circuit 140 is coupled to an output of the comparator 12. The pre-driving circuit 16 is coupled to an output of the level shift circuit 14. The inverter 18 is coupled to the pre-driving circuit 16, the capacitor CB and the switch unit 40. The inverter 18 generates the driving signal UG to control the first switch 51 in response to the output of the comparator through the level shift circuit 14 and the pre-driving circuit 16); a second driver (figure 2, part 20) having an input (figure 2, part 20; left input) and an output (figure 2, part 20; right output), the output of the second driver (figure 2, part 20; right output) coupled to the control terminal of the second transistor (figure 2, part 52; control terminal) (column 4; lines 52-56; The driver circuit 20 includes a comparator 22, a pre-driving circuit 26 and an inverter 28); and circuitry (figure 2, part circuitry generated by 30A and 40) having a control input (figure 2, part circuitry generated by 30A and 40; right control input connected to SL) coupled to the input of the second driver (figure 2, part 20; left input; at SL), a first power input (figure 2, part circuitry generated by 30A and 40; right power input from VCC), and an output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40), the output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40) coupled to the supply terminal of the first driver (figure 2, part 10; upper supply terminal), the circuitry (figure 2, part circuitry generated by 30A and 40) configurable to, responsive to the control input having a first state (figure 2, part circuitry generated by 30A and 40; right control input connected to SL at first state), provide power at the output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40) responsive to a signal at the first power input (figure 2, part circuitry generated by 30A and 40; right power input from VCC), and responsive to the control input having a second state (figure 2, part circuitry generated by 30A and 40; right control input connected to SL at second state) (column 4; lines 29-39; The timing control circuit 30A receives the driving input signal SL associated with the second switch 52 and performs timing control to the driving input signal SL to generate a first control signal VG and a second control signal VG2. The switch unit 40 enables the working voltage VCC to charge the capacitor CB through the switch unit 40 according to the first control signal VG and the second control signal VG2).
Huang does not expressly disclose a second power input, and an output, the output coupled to the supply terminal of the first driver, the circuitry configurable to, responsive to the control input having a first state, provide power at the output responsive to a first signal at the first power input, and responsive to the control input having a second state, provide power at the output responsive to a second signal at the second power input.
Hashim teaches (see figures 1-9) circuitry (figure 4, part circuitry generated by 402, D3, M1, M2 and D4) having a control input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; control input from 404), a first power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; first power input from BIAS), a second power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; second power input from VIN), and an output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412), the output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412) coupled to the supply terminal of the first driver (figure 4, part upper supply terminal of 412), the circuitry (figure 4, part circuitry generated by 402, D3, M1, M2 and D4) configurable to, responsive to the control input having a first state (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; control input from 404 at first state), provide power at the output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412) responsive to a first signal at the first power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; first power input from BIAS; through D4 and M2), and responsive to the control input having a second state (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; control input from 404 at second state), provide power at the output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412) responsive to a second signal at the second power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; second power input from VIN; through M1) (paragraphs [0027]-[0030]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the circuitry of Huang with the circuitry features (more specific the dual power inputs) as taught by Hashim and obtain an apparatus comprising: a first transistor having first and second terminals and a control terminal, the first terminal of the first transistor coupled to a switching terminal; a second transistor having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the second terminal of the first transistor, the second terminal of the second transistor coupled to a first voltage terminal; a first driver having an input, a supply terminal, a reference terminal, and an output, the output of the first driver coupled to the control terminal of the first transistor; a second driver having an input and an output, the output of the second driver coupled to the control terminal of the second transistor; and circuitry having a control input coupled to the input of the second driver, a first power input, a second power input, and an output, the output coupled to the supply terminal of the first driver, the circuitry configurable to, responsive to the control input having a first state, provide power at the output responsive to a first signal at the first power input, and responsive to the control input having a second state, provide power at the output responsive to a second signal at the second power input, because it provides more efficient driver operation with power consumption reduction (paragraph [0034]).
Regarding claim 14, Huang and Hashim teach everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-7) the circuitry (figure 2, part circuitry generated by 30A and 40) includes a third transistor (figure 2, part 41) having first and second terminals (figure 2, part 41; terminals), the first terminal (figure 2, part 41; lower terminal) coupled to the first power input of the circuitry (figure 2, part circuitry generated by 30A and 40; power input connected to VCC), and the second terminal (figure 2, part 41; upper terminal) coupled to the output of the circuitry (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40).
Claims 17 and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 9,859,883), in view of Hashim (US 2020/0144925), and further in view of Reusch et al. (US 2019/0028094), hereinafter Reusch.
Regarding claim 17, Huang discloses (see figures 1-7) a voltage converter (figure 2), comprising: a third transistor (figure 2, part 51) having first and second terminals and a control terminal (figure 2, part 51; terminals), the first terminal of the third transistor (figure 2, part 51; upper terminal) coupled to the switching terminal (figure 2, part switching terminal at upper terminal of 51); a third driver (figure 2, part 10) having a supply terminal (figure 2, part 10; upper supply terminal), a reference terminal (figure 2, part 10; lower reference terminal), and an output (figure 2, part 10; output terminal), the reference terminal of the third driver (figure 2, part 10; lower reference terminal) coupled to the second terminal of the third transistor (figure 2, part 51; lower terminal), and the output of the third driver (figure 2, part 10; output terminal) coupled to the control terminal of the third transistor (figure 2, part 51; control terminal) (column 4; lines 40-51; The driver circuit 10 includes a comparator 12, a level shift circuit 14, a pre-driving circuit 16 and an inverter 18. The comparator 12 receives the driving input signal SU and determines a logic level of the driving input signal SU. The level shift circuit 140 is coupled to an output of the comparator 12. The pre-driving circuit 16 is coupled to an output of the level shift circuit 14. The inverter 18 is coupled to the pre-driving circuit 16, the capacitor CB and the switch unit 40. The inverter 18 generates the driving signal UG to control the first switch 51 in response to the output of the comparator through the level shift circuit 14 and the pre-driving circuit 16); a fourth transistor (figure 2, part 52) having first and second terminals and a control terminal (figure 2, part 52; terminals), the first terminal of the fourth transistor (figure 2, part 52; upper terminal) coupled to the second terminal of the third transistor (figure 2, part 51; lower terminal), the second terminal of the fourth transistor (figure 2, part 52; lower terminal) coupled to a ground terminal (figure 2, part ground); a fourth driver (figure 2, part 20) having an input (figure 2, part 20; left input), a supply terminal (figure 2, part 20; upper supply terminal) and an output (figure 2, part 20; right output), the supply terminal of the fourth driver (figure 2, part 20; upper supply terminal) coupled to a second supply voltage terminal (figure 2, part second supply voltage terminal at VCC), and the output of the fourth driver (figure 2, part 20; right output) coupled to the control terminal of the fourth transistor (figure 2, part 52; control terminal) (column 4; lines 52-56; The driver circuit 20 includes a comparator 22, a pre-driving circuit 26 and an inverter 28); and circuitry (figure 2, part circuitry generated by 30A and 40) having a control input (figure 2, part circuitry generated by 30A and 40; right control input connected to SL) coupled to the input of the fourth driver (figure 2, part 20; left input; at SL), a first power input (figure 2, part circuitry generated by 30A and 40; right power input from VCC), and an output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40), the output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40) coupled to the supply terminal of the third driver (figure 2, part 10; upper supply terminal), the circuitry (figure 2, part circuitry generated by 30A and 40) configurable to, responsive to the control input having a first state (figure 2, part circuitry generated by 30A and 40; right control input connected to SL at first state), provide power at the output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40) responsive to a first signal at the first power input (figure 2, part circuitry generated by 30A and 40; right power input from VCC), and responsive to the control input having a second state (figure 2, part circuitry generated by 30A and 40; right control input connected to SL at second state) (column 4; lines 29-39; The timing control circuit 30A receives the driving input signal SL associated with the second switch 52 and performs timing control to the driving input signal SL to generate a first control signal VG and a second control signal VG2. The switch unit 40 enables the working voltage VCC to charge the capacitor CB through the switch unit 40 according to the first control signal VG and the second control signal VG2).
Huang does not expressly disclose a first transistor having first and second terminals and a control terminal, the first terminal of the first transistor coupled to an input voltage terminal; a first driver having a supply terminal, a reference terminal, and an output, the supply terminal of the first driver coupled to a first supply voltage terminal, the reference terminal of the first driver coupled to the second terminal of the first transistor, and the output of the first driver coupled to the control terminal of the first transistor; a second transistor having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the second terminal of the first transistor, the second terminal of the second transistor coupled to a switching terminal; a second driver having a supply terminal, a reference terminal, and an output, the reference terminal of the second driver coupled to the switching terminal, the output of the second driver coupled to the control terminal of the second transistor; a bootstrap circuit coupled between the first supply voltage terminal and the reference terminal of the second driver; a second power input, and an output, the output coupled to the supply terminal of the first driver, the circuitry configurable to, responsive to the control input having a first state, provide power at the output responsive to a first signal at the first power input, and responsive to the control input having a second state, provide power at the output responsive to a second signal at the second power input.
Hashim teaches (see figures 1-9) circuitry (figure 4, part circuitry generated by 402, D3, M1, M2 and D4) having a control input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; control input from 404), a first power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; first power input from BIAS), a second power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; second power input from VIN), and an output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412), the output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412) coupled to the supply terminal of the first driver (figure 4, part upper supply terminal of 412), the circuitry (figure 4, part circuitry generated by 402, D3, M1, M2 and D4) configurable to, responsive to the control input having a first state (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; control input from 404 at first state), provide power at the output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412) responsive to a first signal at the first power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; first power input from BIAS; through D4 and M2), and responsive to the control input having a second state (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; control input from 404 at second state), provide power at the output (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; output connected to 412) responsive to a second signal at the second power input (figure 4, part circuitry generated by 404, 402, D3, M1, M2 and D4; second power input from VIN; through M1) (paragraphs [0027]-[0030]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the circuitry of Huang with the circuitry features (more specific the dual power inputs) as taught by Hashim, because it provides more efficient driver operation with power consumption reduction (paragraph [0034]).
Reusch teaches (see figures 1-13) a voltage converter (figure 11, part 1100), comprising: a first transistor (figure 11, part QTN) having first and second terminals and a control terminal (figure 11, part QTN; terminals), the first terminal of the first transistor (figure 11, part QTN; upper terminal) coupled to an input voltage terminal (figure 11, part VBUS terminal); a first driver (figure 11, part first driver generated by 210N and 1102N) having a supply terminal (figure 11, part first driver generated by 210N and 1102N; upper supply terminal), a reference terminal (figures 4 and 11, part first driver generated by 210N and 1102N; lower reference terminal at GRtn), and an output (figure 11, part first driver generated by 210N and 1102N; output terminal), the supply terminal of the first driver (figure 11, part first driver generated by 210N and 1102N; upper supply terminal) coupled to a first supply voltage terminal (figure 11, part a first supply voltage terminal at upper terminal of 1102N), the reference terminal of the first driver (figures 4 and 11, part first driver generated by 210N and 1102N; lower reference terminal at GRtn) coupled to the second terminal of the first transistor (figure 11, part QTN; lower terminal), and the output of the first driver (figure 11, part first driver generated by 210N and 1102N; output terminal) coupled to the control terminal of the first transistor (figure 11, part QTN; control terminal); a second transistor (figure 11, part QT2) having first and second terminals and a control terminal (figure 11, part QT2; terminals), the first terminal of the second transistor (figure 11, part QT2; upper terminal) coupled to the second terminal of the first transistor (figure 11, part QTN; lower terminal), the second terminal of the second transistor (figure 11, part QT2; lower terminal) coupled to a switching terminal (figure 11, part switching terminal between QT2 and QT1); a second driver (figure 11, part 210B) having a supply terminal (figure 11, part 210B; upper supply terminal), a reference terminal (figure 11, part 210B; lower reference terminal at GRt2), and an output (figure 11, part 210B; output), the reference terminal of the second driver (figure 11, part 210B; lower reference terminal at GRt2) coupled to the switching terminal (figure 11, part switching terminal between QT2 and QT1), the output of the second driver (figure 11, part 210B; output) coupled to the control terminal of the second transistor (figure 11, part QT2; control terminal); a third transistor (figure 11, part QT1) having first and second terminals and a control terminal (figure 11, part QT1; terminals), the first terminal (figure 11, part QT1; upper terminal) coupled to the switching terminal (figure 11, part switching terminal between QT2 and QT1); a third driver (figure 11, part third driver inside of 210A that control QT1) having a supply terminal (figure 11, part third driver inside of 210A that control QT1; upper supply terminal) and an output (figure 11, part third driver inside of 210A that control QT1; output terminal), the output (figure 11, part third driver inside of 210A that control QT1; output terminal) coupled to the control terminal of the third transistor (figure 11, part QT1; control terminal); a fourth transistor (figure 11, part QTL) having first and second terminals and a control terminal (figure 11, part QTL; terminals), the first terminal (figure 11, part QTL; upper terminal) coupled to the second terminal of the third transistor (figure 11, part QT1; lower terminal), the second terminal (figure 11, part QT1; lower terminal) coupled to a ground terminal (figure 11, part ground); a fourth driver (figure 11, part fourth driver inside of 210A that control QTL) having an input (figures 4 and 11, part fourth driver inside of 210A that control QTL; input), a supply terminal (figure 11, part fourth driver inside of 210A that control QTL; upper supply terminal) and an output (figure 11, part fourth driver inside of 210A that control QTL; right output terminal), the supply terminal (figure 11, part fourth driver inside of 210A that control QTL; upper supply terminal) coupled to a second supply voltage terminal (figure 11, part second supply voltage terminal from 1102B), and the output (figure 11, part fourth driver inside of 210A that control QTL; right output terminal) coupled to the control terminal of the fourth transistor (figure 11, part QTL; control terminal); a bootstrap circuit (figure 11, part bootstrap circuit generated by 1102B and CB2) coupled between the first supply voltage terminal (figure 11, part a first supply voltage terminal at upper terminal of 1102N; through 1006N and RDRN) and the reference terminal of the second driver (figure 11, part 210B; lower reference terminal at GRt2).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the combination of Huang and Hashim to the voltage converter as taught by Reusch and obtain a voltage converter, comprising: a first transistor having first and second terminals and a control terminal, the first terminal of the first transistor coupled to an input voltage terminal; a first driver having a supply terminal, a reference terminal, and an output, the supply terminal of the first driver coupled to a first supply voltage terminal, the reference terminal of the first driver coupled to the second terminal of the first transistor, and the output of the first driver coupled to the control terminal of the first transistor; a second transistor having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the second terminal of the first transistor, the second terminal of the second transistor coupled to a switching terminal; a second driver having a supply terminal, a reference terminal, and an output, the reference terminal of the second driver coupled to the switching terminal, the output of the second driver coupled to the control terminal of the second transistor; a third transistor having first and second terminals and a control terminal, the first terminal of the third transistor coupled to the switching terminal; a third driver having a supply terminal, a reference terminal, and an output, the reference terminal of the third driver coupled to the second terminal of the third transistor, and the output of the third driver coupled to the control terminal of the third transistor; a fourth transistor having first and second terminals and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor, the second terminal of the fourth transistor coupled to a ground terminal; a fourth driver having an input, a supply terminal and an output, the supply terminal of the fourth driver coupled to a second supply voltage terminal, and the output of the fourth driver coupled to the control terminal of the fourth transistor; a bootstrap circuit coupled between the first supply voltage terminal and the reference terminal of the second driver; and circuitry having a control input coupled to the input of the fourth driver, a first power input, a second power input, and an output, the output coupled to the supply terminal of the third driver, the circuitry configurable to, responsive to the control input having a first state, provide power at the output responsive to a first signal at the first power input, and responsive to the control input having a second state, provide power at the output responsive to a second signal at the second power input, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Regarding claim 28, Huang, Reusch and Reusch teach everything claimed as applied above (see claim 17). However, Huang does not expressly disclose a capacitor coupled between the reference terminal of the first driver and a reference terminal of the third driver.
Reusch teaches (see figures 1-13) a capacitor (figures 4 and 11, part CBN) coupled between the reference terminal of the first driver (figures 4 and 11, part first driver generated by 210N and 1102N; lower reference terminal at GRtn) and a reference terminal of the third driver (figures 4 and 11, part third driver inside of 210A that control QT1; lower reference terminal at GR1; through RBDN/2, QBSTN/2 and CB1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the combination of Huang and Hashim to the voltage converter as taught by Reusch, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Regarding claim 29, Huang, Reusch and Reusch teach everything claimed as applied above (see claim 17). However, Huang does not expressly disclose a charge circuit coupled between the reference terminal of the first driver and the reference terminal of the third driver.
Reusch teaches (see figures 1-13) a charge circuit (figure 11, part charge circuit generated by 208A, 1006B, Rdb2, 1006N, Rbdn and 208N) coupled between the reference terminal of the first driver (figures 4 and 11, part first driver generated by 210N and 1102N; lower reference terminal at GRtn) and the reference terminal of the third driver (figures 4 and 11, part third driver inside of 210A that control QT1; lower reference terminal at GR1; through RBDN/2, QBSTN/2 and CB1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the combination of Huang and Hashim to the voltage converter as taught by Reusch, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Regarding claim 30, Huang, Hashim and Reusch teach everything claimed as applied above (see claim 17). Further, Huang discloses (see figures 1-7) the circuitry (figure 2, part circuitry generated by 30A and 40) includes: a first voltage source circuit (figure 2, part 40), including: a fifth transistor (figure 2, part 41) having first and second terminals (figure 2, part 41; terminals), the first terminal of the fifth transistor (figure 2, part 41; lower terminal) coupled to the first power input (figure 2, part circuitry generated by 30A and 40; right power input from VCC), and the second terminal of the fifth transistor (figure 2, part 41; upper terminal) coupled to the output of circuitry (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40).
Allowable Subject Matter
Claims 23-27 and 31-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 36-40 are allowed.
The following is an examiner’s statement of reasons for allowance: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 23, the control input is a first control input, and the circuitry has a second control input coupled to the output of the second driver, and the circuitry includes: a first voltage source circuit including: a fourth transistor having first and second terminals and a control terminal, the first terminal of the fourth transistor coupled to the output of the circuitry, the second terminal of the fourth transistor coupled to the second power input (based on objection presented above); an inverter having an input and an output, the input of the inverter coupled to the second control input of the circuitry; and a logic gate having a first and second inputs and an output, the first input of the logic gate coupled to the output of the inverter, the second input of the logic gate coupled to the first control input of the circuitry, and the output of the logic gate coupled to the control terminal of the fourth transistor;
Regarding claims 24-27, these claims are dependent claims of claim 23, therefore, are objected for the same reason presented above.
Regarding claim 31, the control input is a first control input, the circuitry has a second control input coupled to the output of the fourth driver and the circuitry includes: a second voltage source circuit, including: a sixth transistor having first and second terminals and a control terminal, the first terminal of the sixth transistor coupled to the output of the circuitry, the second terminal of the sixth transistor coupled to the second power input; an inverter having an input and an output, the input of the inverter coupled to the second control input of the circuitry; and a logic gate having first and second inputs and an output, the first input of the logic gate coupled to the output of the inverter, the second input of the logic gate coupled to the first control input of the circuitry, and the output of the logic gate coupled to the control terminal of the sixth transistor;
Regarding claims 32-35, these claims are dependent claims of claim 31, therefore, are objected for the same reason presented above.
Regarding claim 36, a first transistor having first and second terminals and a gate, the first terminal of the first transistor coupled to a switching terminal; a second transistor having first and second terminals and a gate, the first terminal of the second transistor coupled to the second terminal of the first transistor, the second terminal of the second transistor coupled to a first supply voltage terminal; a first driver having a supply terminal and an output, the output of the first driver coupled to the gate of the first transistor; a second driver having an input and an output, the output of the second driver coupled to the gate of the second transistor; a third transistor having first and second terminals and a gate, the first terminal of the third transistor coupled to a second supply voltage terminal, the second terminal of the third transistor coupled to the supply terminal of the first driver; a fourth transistor having first and second terminals and a gate, the first terminal of the fourth transistor coupled to the supply terminal of the first driver; and a gate control circuit having first, second, and third terminals, the first terminal of the gate control circuit coupled to the output of the second driver, the second terminal of the gate control circuit coupled to the input of the second driver, the third terminal of the gate control circuit coupled to the gate of the fourth transistor;
Regarding claims 37-40, these claims are dependent claims of claim 36, therefore, are allowed for the same reason presented above.
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights