DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Request for Continued Examination (RCE) on 01/15/2026.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1, last line recites “the input of the circuitry”, which should be – the control input of the circuitry – because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 17 is objected to because of the following informalities: Claim 17, last line recites “the input of the circuitry”, which should be – the control input of the circuitry – because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 30 is objected to because of the following informalities: Claim 30, lines 4-5 recites “the first voltage supply terminal”, which should be – the first supply voltage terminal – because in this way was previously presented this term in the claim. Claim 30, last line recites “output of circuitry”, which should be – output of the circuitry – because this term was previously presented in the claim.
Appropriate correction is required.
Claim 34 is objected to because of the following informalities: Claim 30, lines 15-16 recites “the first voltage supply terminal”, which should be – the first supply voltage terminal – because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 39 is objected to because of the following informalities: Claim 39, line 9 recites “a fifth transistor having first and second terminals and a, the first terminal and control terminal”, which appears a typographical error of – a fifth transistor having first and second terminals and a control terminal, the first terminal and the control terminal –.
Appropriate correction is required.
Claim 40 is objected to because of the following informalities: Claim 40, line 7 recites “a switch”, which should be – the fourth transistor – because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Huang (US 9,859,883).
Regarding claim 1, Huang discloses (see figures 1-7) an apparatus (figure 2) comprising: a first transistor (figure 2, part 51) having first and second terminals and a control terminal (figure 2, part 51; terminals), the first terminal (figure 2, part 51; upper terminal) coupled to a switching terminal (figure 2, part switching terminal at upper terminal of 51); a second transistor (figure 2, part 52) having first and second terminals and a control terminal (figure 2, part 52; terminals), the first terminal (figure 2, part 52; upper terminal) coupled to the second terminal of the first transistor (figure 2, part 51; lower terminal), the second terminal (figure 2, part 52; lower terminal) coupled to a first voltage terminal (figure 2, part first voltage terminal at lower terminal of 52); a first driver (figure 2, part 10) having an input (figure 2, part 10; left input), a supply terminal (figure 2, part 10; upper supply terminal), and an output (figure 2, part 10; output terminal), the output of the first driver (figure 2, part 10; right output) coupled to the control terminal of the first transistor (figure 2, part 51; control terminal) (column 4; lines 40-51; The driver circuit 10 includes a comparator 12, a level shift circuit 14, a pre-driving circuit 16 and an inverter 18. The comparator 12 receives the driving input signal SU and determines a logic level of the driving input signal SU. The level shift circuit 140 is coupled to an output of the comparator 12. The pre-driving circuit 16 is coupled to an output of the level shift circuit 14. The inverter 18 is coupled to the pre-driving circuit 16, the capacitor CB and the switch unit 40. The inverter 18 generates the driving signal UG to control the first switch 51 in response to the output of the comparator through the level shift circuit 14 and the pre-driving circuit 16); a second driver (figure 2, part 20) having an input (figure 2, part 20; left input) and an output (figure 2, part 20; right output), the output (figure 2, part 20; right output) coupled to the control terminal of the second transistor (figure 2, part 52; control terminal) (column 4; lines 52-56; The driver circuit 20 includes a comparator 22, a pre-driving circuit 26 and an inverter 28); and circuitry (figure 2, part circuitry generated by 30A and 40) having a control input (figure 2, part circuitry generated by 30A and 40; right control input connected to SL) coupled to the input of the second driver (figure 2, part 20; left input; at SL) and an output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40) coupled to the supply terminal of the first driver (figure 2, part 10; upper supply terminal), the circuitry (figure 2, part circuitry generated by 30A and 40) configurable to provide a voltage at the supply terminal (figure 2, part 10; upper supply terminal from 40) responsive to a state of the input of the circuitry (figure 2, part circuitry generated by 30A and 40; right control input connected to SL) (column 4; lines 29-39; The timing control circuit 30A receives the driving input signal SL associated with the second switch 52 and performs timing control to the driving input signal SL to generate a first control signal VG and a second control signal VG2. The switch unit 40 enables the working voltage VCC to charge the capacitor CB through the switch unit 40 according to the first control signal VG and the second control signal VG2).
Regarding claim 14, Huang discloses everything claimed as applied above (see claim 1). Further, Huang discloses (see figures 1-7) the circuitry (figure 2, part circuitry generated by 30A and 40) has a power input (figure 2, part circuitry generated by 30A and 40; power input connected to VCC) and includes a third transistor (figure 2, part 41) having first and second terminals (figure 2, part 41; terminals), the first terminal (figure 2, part 41; lower terminal) coupled to the power input of the circuitry (figure 2, part circuitry generated by 30A and 40; power input connected to VCC), and the second terminal (figure 2, part 41; upper terminal) coupled to the output of the circuitry (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 9,859,883), in view of Reusch et al. (US 2019/0028094), hereinafter Reusch.
Regarding claim 17, Huang discloses (see figures 1-7) a voltage converter (figure 2), comprising: a third transistor (figure 2, part 51) having first and second terminals and a control terminal (figure 2, part 51; terminals), the first terminal (figure 2, part 51; upper terminal) coupled to the switching terminal (figure 2, part switching terminal at upper terminal of 51); a third driver (figure 2, part 10) having a supply terminal (figure 2, part 10; upper supply terminal) and an output (figure 2, part 10; output terminal), the output (figure 2, part 10; output terminal) coupled to the control terminal of the third transistor (figure 2, part 51; control terminal) (column 4; lines 40-51; The driver circuit 10 includes a comparator 12, a level shift circuit 14, a pre-driving circuit 16 and an inverter 18. The comparator 12 receives the driving input signal SU and determines a logic level of the driving input signal SU. The level shift circuit 140 is coupled to an output of the comparator 12. The pre-driving circuit 16 is coupled to an output of the level shift circuit 14. The inverter 18 is coupled to the pre-driving circuit 16, the capacitor CB and the switch unit 40. The inverter 18 generates the driving signal UG to control the first switch 51 in response to the output of the comparator through the level shift circuit 14 and the pre-driving circuit 16); a fourth transistor (figure 2, part 52) having first and second terminals and a control terminal (figure 2, part 52; terminals), the first terminal (figure 2, part 52; upper terminal) coupled to the second terminal of the third transistor (figure 2, part 51; lower terminal), the second terminal (figure 2, part 52; lower terminal) coupled to a ground terminal (figure 2, part ground); a fourth driver (figure 2, part 20) having an input (figure 2, part 20; left input), a supply terminal (figure 2, part 20; upper supply terminal) and an output (figure 2, part 20; right output), the supply terminal (figure 2, part 20; upper supply terminal) coupled to a second supply voltage terminal (figure 2, part second supply voltage terminal at VCC), and the output (figure 2, part 20; right output) coupled to the control terminal of the fourth transistor (figure 2, part 52; control terminal) (column 4; lines 52-56; The driver circuit 20 includes a comparator 22, a pre-driving circuit 26 and an inverter 28); and circuitry (figure 2, part circuitry generated by 30A and 40) having a control input (figure 2, part circuitry generated by 30A and 40; right control input connected to SL) coupled to the input of the fourth driver (figure 2, part 20; left input; at SL) and an output (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40) coupled to the supply terminal of the third driver (figure 2, part 10; upper supply terminal), the circuitry (figure 2, part circuitry generated by 30A and 40) configurable to provide a voltage at the supply terminal (figure 2, part 10; upper supply terminal from 40) responsive to a state of the input of the circuitry (figure 2, part circuitry generated by 30A and 40; right control input connected to SL) (column 4; lines 29-39; The timing control circuit 30A receives the driving input signal SL associated with the second switch 52 and performs timing control to the driving input signal SL to generate a first control signal VG and a second control signal VG2. The switch unit 40 enables the working voltage VCC to charge the capacitor CB through the switch unit 40 according to the first control signal VG and the second control signal VG2).
Huang does not expressly disclose a first transistor having first and second terminals and a control terminal, the first terminal coupled to an input voltage terminal; a first driver having a supply terminal and an output, the supply terminal coupled to a first supply voltage terminal, and the output coupled to the control terminal of the first transistor; a second transistor having first and second terminals and a control terminal, the first terminal coupled to the second terminal of the first transistor, the second terminal coupled to a switching terminal; a second driver having a supply terminal and an output, the output coupled to the control terminal of the second transistor; a bootstrap circuit coupled to the first supply voltage terminal and the supply terminal of the second driver.
Reusch teaches (see figures 1-13) a voltage converter (figure 11, part 1100), comprising: a first transistor (figure 11, part QTN) having first and second terminals and a control terminal (figure 11, part QTN; terminals), the first terminal (figure 11, part QTN; upper terminal) coupled to an input voltage terminal (figure 11, part VBUS terminal); a first driver (figure 11, part first driver generated by 210N and 1102N) having a supply terminal (figure 11, part first driver generated by 210N and 1102N; upper supply terminal) and an output (figure 11, part first driver generated by 210N and 1102N; output terminal), the supply terminal (figure 11, part first driver generated by 210N and 1102N; upper supply terminal) coupled to a first supply voltage terminal (figure 11, part a first supply voltage terminal at upper terminal of 1102N), and the output (figure 11, part first driver generated by 210N and 1102N; output terminal) coupled to the control terminal of the first transistor (figure 11, part QTN; control terminal); a second transistor (figure 11, part QT2) having first and second terminals and a control terminal (figure 11, part QT2; terminals), the first terminal (figure 11, part QT2; upper terminal) coupled to the second terminal of the first transistor (figure 11, part QTN; lower terminal), the second terminal (figure 11, part QT2; lower terminal) coupled to a switching terminal (figure 11, part switching terminal between QT2 and QT1); a second driver (figure 11, part 210B) having a supply terminal (figure 11, part 210B; upper supply terminal) and an output (figure 11, part 210B; output), the output (figure 11, part 210B; output) coupled to the control terminal of the second transistor (figure 11, part QT2; control terminal); a third transistor (figure 11, part QT1) having first and second terminals and a control terminal (figure 11, part QT1; terminals), the first terminal (figure 11, part QT1; upper terminal) coupled to the switching terminal (figure 11, part switching terminal between QT2 and QT1); a third driver (figure 11, part third driver inside of 210A that control QT1) having a supply terminal (figure 11, part third driver inside of 210A that control QT1; upper supply terminal) and an output (figure 11, part third driver inside of 210A that control QT1; output terminal), the output (figure 11, part third driver inside of 210A that control QT1; output terminal) coupled to the control terminal of the third transistor (figure 11, part QT1; control terminal); a fourth transistor (figure 11, part QTL) having first and second terminals and a control terminal (figure 11, part QTL; terminals), the first terminal (figure 11, part QTL; upper terminal) coupled to the second terminal of the third transistor (figure 11, part QT1; lower terminal), the second terminal (figure 11, part QT1; lower terminal) coupled to a ground terminal (figure 11, part ground); a fourth driver (figure 11, part fourth driver inside of 210A that control QTL) having an input (figures 4 and 11, part fourth driver inside of 210A that control QTL; input), a supply terminal (figure 11, part fourth driver inside of 210A that control QTL; upper supply terminal) and an output (figure 11, part fourth driver inside of 210A that control QTL; right output terminal), the supply terminal (figure 11, part fourth driver inside of 210A that control QTL; upper supply terminal) coupled to a second supply voltage terminal (figure 11, part second supply voltage terminal from 1102B), and the output (figure 11, part fourth driver inside of 210A that control QTL; right output terminal) coupled to the control terminal of the fourth transistor (figure 11, part QTL; control terminal); a bootstrap circuit (figure 11, part bootstrap circuit generated by 1102B and CB2) coupled to the first supply voltage terminal (figure 11, part a first supply voltage terminal at upper terminal of 1102N; through 1006N and RDRN) and the supply terminal of the second driver (figure 11, part 210B; upper supply terminal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the converter of Huang to the voltage converter as taught by Reusch and obtain a voltage converter, comprising: a first transistor having first and second terminals and a control terminal, the first terminal coupled to an input voltage terminal; a first driver having a supply terminal and an output, the supply terminal coupled to a first supply voltage terminal, and the output coupled to the control terminal of the first transistor; a second transistor having first and second terminals and a control terminal, the first terminal coupled to the second terminal of the first transistor, the second terminal coupled to a switching terminal; a second driver having a supply terminal and an output, the output coupled to the control terminal of the second transistor; a third transistor having first and second terminals and a control terminal, the first terminal coupled to the switching terminal; a third driver having a supply terminal and an output, the output coupled to the control terminal of the third transistor; a fourth transistor having first and second terminals and a control terminal, the first terminal coupled to the second terminal of the third transistor, the second terminal coupled to a ground terminal; a fourth driver having an input, a supply terminal and an output, the supply terminal coupled to a second supply voltage terminal, and the output coupled to the control terminal of the fourth transistor; a bootstrap circuit coupled to the first supply voltage terminal and the supply terminal of the second driver; and circuitry having a control input coupled to the input of the fourth driver and an output coupled to the supply terminal of the third driver, the circuitry configurable to provide a voltage at the supply terminal responsive to a state of the input of the circuitry, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Regarding claim 28, Huang and Reusch teach everything claimed as applied above (see claim 17). However, Huang does not expressly disclose a capacitor having first and second terminals, the first terminal coupled to the first supply voltage terminal, and the second terminal coupled to a third supply voltage terminal, which is coupled to the second terminal of the first transistor.
Reusch teaches (see figures 1-13) a capacitor (figure 11, part CBN) having first and second terminals (figure 11, part CBN; terminals), the first terminal (figure 11, part CBN; upper terminal) coupled to the first supply voltage terminal (figure 11, part a first supply voltage terminal at upper terminal of 1102N), and the second terminal (figure 11, part CBN; lower terminal) coupled to a third supply voltage terminal (figure 11, part terminal GRtn at 210N), which is coupled to the second terminal of the first transistor (figure 11, part QTN; lower terminal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the converter of Huang to the voltage converter as taught by Reusch, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Regarding claim 29, Huang and Reusch teach everything claimed as applied above (see claim 17). However, Huang does not expressly disclose a charge circuit, having a first and second terminal, the first terminal coupled to the second terminal of the first transistor, and the second terminal coupled to the second terminal of the third transistor.
Reusch teaches (see figures 1-13) a charge circuit (figure 11, part charge circuit generated by 208A, 1006B, Rdb2, 1006N, Rbdn and 208N), having a first and second terminal (figure 11, part charge circuit generated by 208A, 1006B, Rdb2, 1006N, Rbdn and 208N; terminals), the first terminal (figure 11, part charge circuit generated by 208A, 1006B, Rdb2, 1006N, Rbdn and 208N; first terminal at lower side of 208N) coupled to the second terminal of the first transistor (figure 11, part QTN; lower terminal), and the second terminal (figure 11, part charge circuit generated by 208A, 1006B, Rdb2, 1006N, Rbdn and 208N; second terminal at lower side of 208A) coupled to the second terminal of the third transistor (figure 11, part QT1; lower terminal).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the converter of Huang to the voltage converter as taught by Reusch, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Regarding claim 30, Huang and Reusch teach everything claimed as applied above (see claim 17). Further, Huang discloses (see figures 1-7) the circuitry (figure 2, part circuitry generated by 30A and 40) includes: a first voltage source circuit (figure 2, part 40), including: a fifth transistor (figure 2, part 41) having first and second terminals (figure 2, part 41; terminals), the first terminal (figure 2, part 41; lower terminal) coupled to the supply terminal (figure 2, part VCC terminal), and the second terminal (figure 2, part 41; upper terminal) coupled to the output of circuitry (figure 2, part circuitry generated by 30A and 40; upper output at upper terminal of 40). However, Huang does not expressly disclose the first voltage supply terminal.
Reusch teaches (see figures 1-13)the first supply voltage terminal (figure 11, part a first supply voltage terminal at upper terminal of 1102N).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the circuitry features of the converter of Huang to the voltage converter as taught by Reusch, because the combination results in more efficient gate driver circuit with circuit losses reduction for multi-level converters (paragraph [0042]).
Allowable Subject Matter
Claims 23-27 and 31-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 36-38 are allowed. Claims 39 and 40 are objected, but would be allowable upon overcoming the objection set forth in this action.
The following is an examiner’s statement of reasons for allowance: The closest prior art (which has been made of record) fail to disclose (by themselves or in combination):
Regarding claim 23, the control input is a first control input, and the circuitry has a second control input coupled to the output of the second driver, and the circuitry includes: a first voltage source circuit including: a fourth transistor having first and second terminals and a control terminal, the first terminal coupled to the output of the circuitry; an inverter having an input and an output, the input coupled to the second control input of the circuitry; and a logic gate having a first and second inputs and an output, the first input coupled to the output of the inverter, the second input coupled to the first control input of the circuitry, and the output coupled to the control terminal of the fourth transistor;
Regarding claims 24-27, these claims are dependent claims of claim 23, therefore, are objected for the same reason presented above.
Regarding claim 31, the control input is a first control circuit, the circuitry has a second control input coupled to the output of the fourth driver and the circuitry includes: a second voltage source circuit, including: a sixth transistor having first and second terminals and a control terminal, the first terminal coupled to the output of the circuitry, the second terminal coupled to an output of the voltage converter; an inverter having an input and an output, the input coupled to the second control input of the circuitry; and a logic gate having first and second inputs and an output, the first input coupled to the output of the inverter, the second input coupled to the first control input of the circuitry, and the output coupled to the control terminal of the sixth transistor;
Regarding claims 32-35, these claims are dependent claims of claim 31, therefore, are objected for the same reason presented above.
Regarding claim 36, a first transistor having first and second terminals and a gate, the first terminal coupled to a switching terminal; a second transistor having first and second terminals and a gate, the first terminal coupled to the second terminal of the first transistor, the second terminal coupled to a first supply voltage terminal; a first driver having a supply terminal and an output, the output coupled to the gate of the first transistor; a second driver having an input and an output, the output coupled to the gate of the second transistor; a third transistor having first and second terminals and a gate, the first terminal coupled to a second supply voltage terminal, the second terminal coupled to the supply terminal of the first driver; a fourth transistor having first and second terminals and a gate, the first terminal coupled to the supply terminal of the first driver; and a gate control circuit having first, second, and third terminals, the first terminal coupled to the output of the second driver, the second terminal coupled to the input of the second driver, the third terminal coupled to the gate of the fourth transistor;
Regarding claims 37-38, these claims are dependent claims of claim 36, therefore, are allowed for the same reason presented above.
Regarding claims 39 and 40, these claims are dependent claims of claim 36, therefore, are objected for the same reason presented above.
In combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838