CTNF 17/895,107 CTNF 81485 DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. The Response to Election/Restriction filed has been received and considered. Claims 21-23 are withdrawn from further consideration. Claims 1-20 are elected without traverse and presented for examination. 07-30-03-h AIA Claim Interpretation Office personnel are to give claims their "broadest reasonable interpretation" in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Limitations appearing in the specification but not recited in the claim are not read into the claim. In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541,550-551(CCPA 1969). See *also In re Zletz, 893 F.2d 319,321-22, 13 USPQ2d 1320, 1322(Fed. Cir. 1989) ("During patent examination the pending claims must be interpreted as broadly as their terms reasonably allow").... The reason is simply that during patent prosecution when claims can be amended, ambiguities should be recognized, scope and breadth of language explored, and clarification imposed.... An essential purpose of patent examination is to fashion claims that are precise, clear, correct, and unambiguous. Only in this way can uncertainties of claim scope be removed, as much as possible, during the administrative process. Claims recite "and/or". The claims reciting "and/or" were interpreted as “or”. 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the manufacturing modeler configured to. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. As to the previously identified/above means for limitations a corresponding structure in the specification reads: '[0012] The terms "processor" or "controller" as, for example, used herein may be understood as any kind of technological entity that allows handling of data. The data may be handled according to one or more specific functions executed by the processor or controller. Further, a processor or controller as used herein may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor or a controller may thus be or include an analog circuit, digital circuit, mixed-signal circuit, logic circuit, processor, microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU)' Claim Objections Claims refer to the terms “the real package substrate stack” and “the package substrate stack”, it would be better to uniquify to avoid any possible antecedent issues. 07-05-06 AIA Claim 15 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 14 . When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 706.03(k). Appropriate correction or clarification is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. As to claim 1, lines 4 and 6, the cited feature "model, configured to" makes the claim indefinite because it fails to point out the precise meaning of the cited feature. It is unclear if models can be configured to do anything, because simulation models are software representations of objects. Simulation models are software executed by processors. Claim 7 recites the limitation "the first trace width" in line(s) 3. There is insufficient antecedent basis for this limitation in the claim. There is no "first trace width" anteceding this limitation in the claim. Claim 7 recites the limitation "the second trace width" in line(s) 3. There is insufficient antecedent basis for this limitation in the claim. There is no "second trace width" anteceding this limitation in the claim. As to claim 12, it is objected for a similarly deficiency. Claim 12 recites the limitation "the fourth trace width" in line(s) 2. There is insufficient antecedent basis for this limitation in the claim. There is no "fourth trace width" anteceding this limitation in the claim. Claim 13 recites the limitation "the stack model" in line(s) 1. There is insufficient antecedent basis for this limitation in the claim. There is no "stack model" anteceding this limitation in the claim. Claim 13 recites the limitation "the real manufacture of the layer design" in line(s) 2. There is insufficient antecedent basis for this limitation in the claim. There is no "real manufacture of the layer design" anteceding this limitation in the claim. Dependent claims inherit the defect of the claim from which they depend. Claim Rejections -35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected because the claimed invention is directed to a judicial exception without significantly more. Independent claim 1, Step 1: a package substrate stack modeler – system (system = 2019 PEG Step 1 = yes) Independent claim 1, Step 2A, Prong One: claim recites: determine a signal integrity of a metal trace of the real package substrate stack… determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model The limitations are substantially drawn to mental concepts. The limitations, as drafted and under their broadest reasonable interpretation, cover performance of the limitations in the mind but for the recitation of generic computer components. Information and/or data also fall within the realm of abstract ideas because information and data are intangible. See Electric Power Group 1 ( Electric Power hereinafter): “Information… is an intangible”. As to the limitations "determine a signal integrity of a metal trace of the real package substrate stack… determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable", determinations are mental in nature. These activities can be characterized as entailing a user analyzing (observations, evaluations) and deciding/determining (judgments), i.e., processing information and/or data, that can be performed in the human mind or by a human using a pen and paper. As to the limitations "determine a signal integrity of a metal trace of the real package substrate stack", the claimed invention further reads “15… wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace, cross talk between the metal trace and another metal trace, or insertion loss of the metal trace". As to the limitations "determine a yield of the real package substrate stack", Examiner notes that the Specification reads '[0002]… yield (Y) (e.g. cost)'. As to the limitations "select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model", under its broadest reasonable interpretation, “selecting” is a mental concept. Examiner notes that both the claimed invention and the specification are mute about how selections are made. Selections are mental in nature (mental processes including a judgment, opinion). If a claim limitation, under its broadest reasonable interpretation, covers mental processes, then it falls within the "(c) Mental processes" grouping of abstract ideas (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes, (c) Mental processes—concepts performed in the human mind (including an observation, evaluation, judgment, opinion) . Independent claim 1, Step 2A, Prong two: The claim recites the additional elements a manufacturing modeler configured to and a processor as performing generic computer functions routinely used in computer applications. As to the limitations "a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack" and "a signal integrity model, configured to… a yield model, configured to", these limitations represent no more than just “apply it” limitations, because they recite only the idea of a solution or outcome, i.e. these claim limitations fail to recite details of how a solution to a problem is accomplished. This judicial exception is not integrated into a practical application (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial exception/Abstract idea into a practical application? = NO) . Independent claim 1, Step 2B: As discussed with respect to Step 2A, claim 1 recites the additional elements a manufacturing modeler configured to (see Claim Interpretation above) and a processor. Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system. The use of a computer to implement the abstract idea of a mathematical or mental algorithm has not been held by the courts to be enough to qualify as “significantly more”. The implementation on a computing system is described in the specification (underline emphasis added): '[0012] The terms " processor " or "controller" as, for example, used herein may be understood as any kind of technological entity that allows handling of data . The data may be handled according to one or more specific functions executed by the processor or controller. Further, a processor or controller as used herein may be understood as any kind of circuit, e.g., any kind of analog or digital circuit. A processor or a controller may thus be or include an analog circuit, digital circuit, mixed-signal circuit, logic circuit, processor, microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU) ' As discussed with respect to Step 2A, Prong two, limitations reciting only the idea of a solution or outcome are just “apply it” limitations, because these claim limitations fail to recite details of how a solution to a problem is accomplished. See MPEP 2106.05(f)(1). As to the limitations "a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack", the limitations are so broad that little is known about how the claimed generation of a model is performed. As to the limitations "a signal integrity model, configured to… a yield model, configured to", it is unclear if models can be configured to do anything, because models are representations of objects. Models are software executed by processors. (See 112 Rejection above). Taken alone the individual additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as an ordered combination adds nothing that is not already present when looking at the additional elements taken individually. There is no indication that their combination improves the functioning of a computer itself or improves any other technology (underline emphasis added). Therefore, the claim does not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO) . Independent claim 17, Step 1: a computer readable medium (manufacture = 2019 PEG Step 1 = yes) Independent claim 17, Step 2A, Prong One: claim recites: determine a signal integrity of a metal trace of the real package substrate stack, wherein the metal trace comprises a first value of a trace variable; determine a yield of the real package substrate stack; and select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield The limitations are substantially drawn to mental concepts. The limitations, as drafted and under their broadest reasonable interpretation, cover performance of the limitations in the mind but for the recitation of generic computer components. Information and/or data also fall within the realm of abstract ideas because information and data are intangible. See Electric Power . As to the limitations "determine a signal integrity of a metal trace of the real package substrate stack, wherein the metal trace comprises a first value of a trace variable; determine a yield of the real package substrate stack", determinations are mental in nature. (See Independent claim 1, Step 2A Prong One above). As to the limitations "select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield", under its broadest reasonable interpretation, “selecting” is a mental concept. (See Independent claim 1, Step 2A Prong One above). If a claim limitation, under its broadest reasonable interpretation, covers mental processes, then it falls within the "(c) Mental processes" grouping of abstract ideas (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes, (c) Mental processes—concepts performed in the human mind (including an observation, evaluation, judgment, opinion) . Independent claim 17, Step 2A, Prong two: The claim recites the additional element a computer readable medium as performing generic computer functions routinely used in computer applications. As to the limitations "generate a model of a real package substrate stack based on an ideal design of the package substrate stack", they represent no more than just “apply it” limitations, because they recite only the idea of a solution or outcome, i.e. these claim limitations fail to recite details of how a solution to a problem is accomplished. This judicial exception is not integrated into a practical application (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial exception/Abstract idea into a practical application? = NO) . Independent claim 17, Step 2B: As discussed with respect to Step 2A, claim 17 recites the additional element a computer readable medium. Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system. (See Independent claim 1, Step 2B above). As discussed with respect to Step 2A, Prong two, limitations reciting only the idea of a solution or outcome are just “apply it” limitations, because these claim limitations fail to recite details of how a solution to a problem is accomplished. (See Independent claim 1, Step 2B above). Taken alone the individual additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as an ordered combination adds nothing that is not already present when looking at the additional elements taken individually. There is no indication that their combination improves the functioning of a computer itself or improves any other technology (underline emphasis added). Therefore, the claim does not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO) . Dependent claims, Prong One: The claim limitations further the mental concepts of their independent claims. (See Independent claims, Step 2A, Prong One above). As to the limitations "2… select the second value of the trace variable based on the determined signal integrity and the determined yield", "3… select the second value of the trace variable based on the model of the real package substrate stack", "8… select a fourth trace width of the second trace portion based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model", "9… select the fourth trace width based on the determined signal integrity of the metal trace and the determined yield of the package substrate stack model", "10… select the fourth trace width based on the model of the real package substrate stack", "12… select the second trace width and/or the fourth trace width as a function of the signal integrity and the yield", "18… select the second value of the trace variable based on the determined signal integrity and the determined yield", "19… select the second value of the trace variable based on the model of the real package substrate stack", under its broadest reasonable interpretation, “selecting” is a mental concept. Examiner notes that both the claimed invention and the specification are mute about how selections are made. Selections are mental in nature (mental processes including a judgment, opinion). As to the limitations "6… wherein generating the model of the real package substrate stack comprises determining one or more deviations from the ideal design of the package substrate stack resulting from one or more manufacturing processes", "14… wherein determining the signal integrity of the metal trace comprising determining any of impedance of the metal trace, cross talk between the metal trace and another metal trace, or insertion loss of the metal trace", "15… wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace, cross talk between the metal trace and another metal trace, or insertion loss of the metal trace", and "16… wherein determine the yield of the real package substrate stack comprises determining an amount of yield loss of the real package substrate stack", determinations are mental in nature. These activities can be characterized as entailing a user analyzing (observations, evaluations) and deciding/determining (judgments), i.e., processing information and/or data, that can be performed in the human mind or by a human using a pen and paper. If a claim limitation, under its broadest reasonable interpretation, covers abstract ideas, then it falls within groupings of abstract ideas (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes) . Dependent claims, Step 2A, Prong two: As to the limitations "7… change the trace width of the model of the real package substrate stack or the ideal design of the package substrate stack from the first trace width to the second trace width", "11… change the third trace width of the model of the package substrate stack or the ideal design of the package substrate stack from the third trace width to the fourth trace width", and "13… wherein the stack model is configured to generate the model of the real manufacture of the layer design by spatially resolving substrate manufacturing stacks", these limitations represent no more than just “apply it” limitations, because they recite only the idea of a solution or outcome, i.e. these claim limitations fail to recite details of how a solution to a problem is accomplished. This judicial exception is not integrated into a practical application of the exception (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial exception/Abstract idea into a practical application? = NO) . Dependent claims, Step 2B: As discussed with respect to Step 2A, Prong two, limitations reciting only the idea of a solution or outcome are just “apply it” limitations, because these claim limitations fail to recite details of how a solution to a problem is accomplished. See MPEP 2106.05(f)(1). The limitations are so broad that little is known about how the claimed trace width is changed or how to spatially resolve substrate manufacturing stacks. The claims do not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23 AIA The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Examiner would like to point out that any reference to specific figures, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention. 07-21 AIA Claim s 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Chang et al., (Chang hereinafter), International Pub. No. EP0597087, taken in view of Douglas Elmer Wallace, Jr. , (Wallace hereinafter), U.S. Patent 6,968,300 . As to claim 1, Chang discloses a package substrate stack (see "[0018]… computer aided design and electrical performance prediction of multilevel device interconnects in VLSI integrated circuits, as well as PCB and MCM technologies"; "[0015]… packaging categories (i.e., IC processes, metal capacitance models (MCM), printed circuit boards (PCB)") modeler (see "[0021]… complete SPICE subcircuit/circuit generation and simulation for an interconnect structure design, including the layer assignment, risetime, width/spacing, and coupling length, can be generated and simulated automatically") , comprising: a manufacturing modeler, configured to (see [0087] Thus, this invention provides an interconnect modeling system") generate a model (see "[0021]… complete SPICE subcircuit/circuit generation and simulation for an interconnect structure design, including the layer assignment, risetime, width/spacing, and coupling length, can be generated"; "[0070] When the user selects SPICE CREATE… read the equation file 406 and generate parameterized three-line π3 circuit models for distributed R,C circuit simulation. The resulting SPICE deck is written to a parameterized model file") of a real package substrate stack (see "[0065]… An evaluation panel is provided for users to do stackup design. Stackup design involves assigning signal or reference planes to each layer of an interconnect construction. Once a user specifies layer assignment for a selected construction, the invention can determine layer models for each layer. Furthermore, on-line performance evaluation can be done for each signal layer given an arbitrary trace width and spacing within the interpolation range") based on an ideal design of the package substrate stack (see "[0018]… computer aided design and electrical performance prediction of multilevel device interconnects in VLSI integrated circuits, as well as PCB and MCM technologies… Four subsystems are integrated: (b) an interactive design package with performance browsing, goal-directed synthesis, and on-line performance evaluation") ; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack (see "[0021]… complete SPICE subcircuit/circuit generation and simulation for an interconnect structure design, including the layer assignment, risetime, width/spacing, and coupling length, can be generated and simulated automatically for signal integrity analysis") ; a yield model, configured to (see [0087] Thus, this invention provides an interconnect modeling system") determine a yield of the real package substrate stack (see "yield" as "cost… and manufacturability", "[0025]… selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadsheets provided by the invention, designers can customize the operation of the invention for other variables such as reliability, thermal effects, and cost effects"; "[0085]… analyze and optimize interconnect designs in an interactive way. There are other design constraints, such as cost… and manufacturability, that determine the final choice of a certain technology") ; wherein the metal trace comprises a first value of a trace variable; further comprising a processor (see [0087] Thus, this invention provides an interconnect modeling system") , configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model (see "trace variable" as "trace width and/or trace spacing", "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). About Examiner's interpretation of "yield" as "cost… and manufacturability", Examiner notes that the Specification reads '[0002]… yield (Y) (e.g. cost)'. About Examiner's interpretation of "trace variable" as "trace width and/or trace spacing", Examiner notes that as per dependent claim "5… wherein the trace variable is any one of trace width, trace-to-trace distance, distance to a next trace above the trace, or distance to a next trace below the trace". While Chang discloses signal integrity, Chang does not disclose signal integrity of a metal trace. Wallace discloses signal integrity of a metal trace (see "for simulations in designs of trace impedances and topologies for electrical signal integrity of a circuit of a printed circuit board, such as a computer system motherboard. Exemplary parameters or variables may include trace width" in col. 4, lines 47-51). Chang and Wallace are analogous art because they are related to trace simulations. Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Wallace with Chang, because Wallace discloses "signal integrity simulations with stochastic techniques" (see col. 2, lines 55-56), and as a result, Wallace reports that "[t]rend line equations (i.e., fitting of respective data points to corresponding equations) for each of the MC and QMC data simulations were generated. The trend line equations, shown in FIG. 4, illustrate that the MC method has a classic 1/√N error decrease, (the exponent of x is approximately -0.5), whereas, the QMC error drops much faster. For instance, an average QMC simulation of 80 points is equivalently accurate to an MC simulation using 320 points. Accordingly, the QMC method of the present disclosure provides an advantage in reducing simulation time" (see col. 4, lines 32-42). As to claim 2, Chang discloses wherein the processor is configured to select the second value of the trace variable based on the determined signal integrity (see "signal integrity" as "impedance", "[0061]… Goal-directed interconnect synthesis helps users to narrow down possible interconnect designs quickly. The domain of search is all processes/technologies that have been simulated in the batch mode. The invention extracts a subset of designs that satisfy multiple performance goals, such as impedance… specified by the user") and the determined yield (see "yield" as "cost… and manufacturability", "[0025]… selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadsheets provided by the invention, designers can customize the operation of the invention for other variables such as reliability, thermal effects, and cost effects") . About Examiner's interpretation of "signal integrity" as "impedance", see dependent claim "15… wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace…". As to claim 3, Chang discloses wherein the processor is further configured to select the second value of the trace variable based on the model of the real package substrate stack (see "real package substrate stack" as "layer assignments for the chosen MCM technology", "[0084]… specifying layer assignments for the chosen MCM technology. Arbitrary choices of trace width/spacing, coupling length, and risetime can be specified, and performance information can subsequently be derived"; "[0015]… packaging categories (i.e., IC processes, metal capacitance models (MCM), printed circuit boards (PCB)"). As to claim 4, Chang discloses wherein the trace variable is trace width (see "trace width", "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). As to claim 5, Chang discloses wherein the trace variable is any one of trace width, trace-to-trace distance, distance to a next trace above the trace, or distance to a next trace below the trace (see "trace variable" as "trace width and/or trace spacing", "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). As to claim 6, Chang discloses wherein generating the model of the real package substrate stack comprises determining one or more deviations from the ideal design of the package substrate stack resulting from one or more manufacturing processes (see "[0062]… The user can also look at the effect of changing trace width/spacing on any performance variable… This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). As to claim 7, Chang discloses wherein the processor is further configured to change the trace width of the model of the real package substrate stack or the ideal design of the package substrate stack from the first trace width to the second trace width (see "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). As to claim 8, Chang discloses wherein the metal trace comprises a first trace portion and a second trace portion; wherein the first trace width is a trace width of the first portion, the second trace width is an amended trace width of the first portion; wherein the second trace portion comprises a third trace width (see "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables") ; and wherein the processor is further configured to select a fourth trace width of the second trace portion based on the determined signal integrity of the metal trace (see "signal integrity" as "impedance", "[0061]… Goal-directed interconnect synthesis helps users to narrow down possible interconnect designs quickly. The domain of search is all processes/technologies that have been simulated in the batch mode. The invention extracts a subset of designs that satisfy multiple performance goals, such as impedance… specified by the user") or the determined yield of the package substrate stack model . About Examiner's interpretation of "signal integrity" as "impedance", see dependent claim "15… wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace…". As to claim 9, Chang discloses wherein the processor is configured to select the fourth trace width based on the determined signal integrity of the metal trace (see "signal integrity" as "impedance", "[0061]… Goal-directed interconnect synthesis helps users to narrow down possible interconnect designs quickly. The domain of search is all processes/technologies that have been simulated in the batch mode. The invention extracts a subset of designs that satisfy multiple performance goals, such as impedance… specified by the user") and the determined yield of the package substrate stack model (see "yield" as "cost… and manufacturability", "[0025]… selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadsheets provided by the invention, designers can customize the operation of the invention for other variables such as reliability, thermal effects, and cost effects"). About Examiner's interpretation of "signal integrity" as "impedance", see dependent claim "15… wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace…". As to claim 10, Chang discloses wherein the processor is further configured to select the fourth trace width based on the model of the real package substrate stack (see "real package substrate stack" as "layer assignments for the chosen MCM technology", "[0084]… specifying layer assignments for the chosen MCM technology. Arbitrary choices of trace width/spacing, coupling length, and risetime can be specified, and performance information can subsequently be derived"; "[0015]… packaging categories (i.e., IC processes, metal capacitance models (MCM), printed circuit boards (PCB)"). As to claim 11, Chang discloses wherein the processor is further configured to change the third trace width of the model of the package substrate stack or the ideal design of the package substrate stack from the third trace width to the fourth trace width (see "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). As to claim 12, Chang discloses wherein the processor is configured to select the second trace width and/or the fourth trace width as a function of the signal integrity (see "signal integrity" as "impedance", "[0061]… Goal-directed interconnect synthesis helps users to narrow down possible interconnect designs quickly. The domain of search is all processes/technologies that have been simulated in the batch mode. The invention extracts a subset of designs that satisfy multiple performance goals, such as impedance… specified by the user") and the yield (see "yield" as "cost… and manufacturability", "[0025]… selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadsheets provided by the invention, designers can customize the operation of the invention for other variables such as reliability, thermal effects, and cost effects") . About Examiner's interpretation of "signal integrity" as "impedance", see dependent claim "15… wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace…". As to claim 13, Chang discloses wherein the stack model is configured to generate the model of the real manufacture of the layer design by spatially resolving substrate manufacturing stacks (see "[0028]… The batch mode 100 is used to prepare data files for a new VLSI chip/MGM/PCB construction technique"). As to claims 14 & 15, Chang discloses wherein determining the signal integrity of the metal trace comprises determining any of impedance of the metal trace, cross talk between the metal trace and another metal trace, or insertion loss of the metal trace (see "[0083]… To use the invention to optimize the design in this case, first, a user runs batch-mode simulations for possible interconnect design configurations… The result of the batch-mode simulation is the interconnect R,L,C, impedance…and crosstalk information") . As to claim 16, Chang discloses wherein determine the yield of the real package substrate stack comprises determining an amount of yield loss of the real package substrate stack (see "yield" as "cost… and manufacturability", "[0085]… analyze and optimize interconnect designs in an interactive way. There are other design constraints, such as cost… and manufacturability, that determine the final choice of a certain technology. For this application example, an open-ended termination coupler has less power consumption than a well-terminated coupler. The cost of 9.0 dielectric material is less than that of 4.0 dielectric material, and the cheaper material may satisfy performance requirements as well"). As to claim 17, Chang discloses a non-transitory computer readable medium, comprising instructions which, if executed by one or more processors, are configured to cause the one or more processors (see "[0087]… interconnect modeling system") to: generate a model (see "[0021]… complete SPICE subcircuit/circuit generation and simulation for an interconnect structure design, including the layer assignment, risetime, width/spacing, and coupling length, can be generated"; "[0070] When the user selects SPICE CREATE… read the equation file 406 and generate parameterized three-line π3 circuit models for distributed R,C circuit simulation. The resulting SPICE deck is written to a parameterized model file") of a real package substrate stack (see "[0065]… An evaluation panel is provided for users to do stackup design. Stackup design involves assigning signal or reference planes to each layer of an interconnect construction. Once a user specifies layer assignment for a selected construction, the invention can determine layer models for each layer. Furthermore, on-line performance evaluation can be done for each signal layer given an arbitrary trace width and spacing within the interpolation range") based on an ideal design of the package substrate stack (see "[0018]… computer aided design and electrical performance prediction of multilevel device interconnects in VLSI integrated circuits, as well as PCB and MCM technologies… Four subsystems are integrated: (b) an interactive design package with performance browsing, goal-directed synthesis, and on-line performance evaluation") ; determine a signal integrity of a metal trace of the real package substrate stack (see "[0021]… complete SPICE subcircuit/circuit generation and simulation for an interconnect structure design, including the layer assignment, risetime, width/spacing, and coupling length, can be generated and simulated automatically for signal integrity analysis") , wherein the metal trace comprises a first value of a trace variable (see "first value" as original value of "trace width and/or trace spacing" and "trace variable" as "trace width and/or trace spacing", "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable") ; determine a yield of the real package substrate stack (see "yield" as "cost… and manufacturability", "[0025]… selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadsheets provided by the invention, designers can customize the operation of the invention for other variables such as reliability, thermal effects, and cost effects"; "[0085]… analyze and optimize interconnect designs in an interactive way. There are other design constraints, such as cost… and manufacturability, that determine the final choice of a certain technology") ; and select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield (see "trace variable" as "trace width and/or trace spacing", "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). While Chang discloses signal integrity, Chang does not disclose signal integrity of a metal trace. Wallace discloses signal integrity of a metal trace (see "for simulations in designs of trace impedances and topologies for electrical signal integrity of a circuit of a printed circuit board, such as a computer system motherboard. Exemplary parameters or variables may include trace width" in col. 4, lines 47-51). As to claim 18, Chang discloses wherein the instructions are further configured to cause the one or more processors to select the second value of the trace variable based on the determined signal integrity (see "signal integrity" as "impedance", "[0061]… Goal-directed interconnect synthesis helps users to narrow down possible interconnect designs quickly. The domain of search is all processes/technologies that have been simulated in the batch mode. The invention extracts a subset of designs that satisfy multiple performance goals, such as impedance… specified by the user") and the determined yield (see "yield" as "cost… and manufacturability", "[0025]… selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadsheets provided by the invention, designers can customize the operation of the invention for other variables such as reliability, thermal effects, and cost effects") . As to claim 19, Chang discloses wherein the instructions are further configured to cause the one or more processors to select the second value of the trace variable based on the model of the real package substrate stack (see "real package substrate stack" as "layer assignments for the chosen MCM technology", "[0084]… specifying layer assignments for the chosen MCM technology. Arbitrary choices of trace width/spacing, coupling length, and risetime can be specified, and performance information can subsequently be derived"; "[0015]… packaging categories (i.e., IC processes, metal capacitance models (MCM), printed circuit boards (PCB)"). As to claim 20, Chang discloses wherein the trace variable is trace width (see "trace width", "[0062]… user can also look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneously visualize trade-offs for different trace width/spacing designs as well as their impact on several performance variables"). Response to Arguments Regarding the Election/Restrictions, Applicant affirms election without traverse to prosecute Group I. Conclusion Examiner would like to point out that any reference to specific figures, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN CARLOS OCHOA whose telephone number is (571)272-2625. The examiner can normally be reached Mondays, Tuesdays, Thursdays, and Fridays 9:30AM - 7:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Chavez can be reached at 571-270-1104. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JUAN C OCHOA/Primary Examiner, Art Unit 2186 Application/Control Number: 17/895,107 Page 2 Art Unit: 2186 Application/Control Number: 17/895,107 Page 3 Art Unit: 2186 Application/Control Number: 17/895,107 Page 4 Art Unit: 2186 Application/Control Number: 17/895,107 Page 5 Art Unit: 2186 Application/Control Number: 17/895,107 Page 6 Art Unit: 2186 Application/Control Number: 17/895,107 Page 7 Art Unit: 2186 Application/Control Number: 17/895,107 Page 8 Art Unit: 2186 Application/Control Number: 17/895,107 Page 9 Art Unit: 2186 Application/Control Number: 17/895,107 Page 10 Art Unit: 2186 Application/Control Number: 17/895,107 Page 11 Art Unit: 2186 Application/Control Number: 17/895,107 Page 12 Art Unit: 2186 Application/Control Number: 17/895,107 Page 13 Art Unit: 2186 Application/Control Number: 17/895,107 Page 14 Art Unit: 2186 Application/Control Number: 17/895,107 Page 15 Art Unit: 2186 Application/Control Number: 17/895,107 Page 16 Art Unit: 2186 Application/Control Number: 17/895,107 Page 17 Art Unit: 2186 Application/Control Number: 17/895,107 Page 18 Art Unit: 2186 Application/Control Number: 17/895,107 Page 19 Art Unit: 2186 Application/Control Number: 17/895,107 Page 20 Art Unit: 2186 Application/Control Number: 17/895,107 Page 21 Art Unit: 2186 Application/Control Number: 17/895,107 Page 22 Art Unit: 2186 Application/Control Number: 17/895,107 Page 23 Art Unit: 2186 Application/Control Number: 17/895,107 Page 24 Art Unit: 2186 Application/Control Number: 17/895,107 Page 25 Art Unit: 2186 1 Electric Power Group , LLC v. Alstom S.A., 119 USPQ2d 1739 Fed. Cir. 2016
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