Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7 - 9, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and further in view of US20090278222A1 (Chadwick).
In regards to claim 1 (Reith) shows a method of designing a layout of a semiconductor device, the method comprising:
a plurality of decoupling capacitor cells, a plurality of filler cells; Reith [Column 3 Lines 65 - Column 4 Lines 5] teaches deep trench lithographic fill patterns can be used to form decoupling capacitors for lower voltage power supplies and gate filler or GC and diffusion filler AA could be combined to form plate or FET-capacitors. Reith [Column 4 Lines 10-20] teaches different kinds of decoupling capacitors for different power supplies can be automatically generated in irregular empty spaces demonstrating plurality of decoupling capacitor cells and plurality of filler cells.
a plurality of power wirings, a plurality of ground wirings; Reith [Column 4 Lines 25-40] teaches the bottom plate is contacted by the first group of metal studs which are later linked by metal wiring and the top plate is contacted by a second group of metal studs and will be later linked by metal wire demonstrating multiple wiring connections for power and ground. Reith [Column 3 Lines 55-65] teaches the closest power-supply nets get extracted and all power-supplies and their combinations are sorted in a connection table.
setting a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells; Reith [Column 3 Lines 50 - 65] teaches when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool and then the closest power-supply nets get extracted by using another layout checking tool. Reith [Column 4 Lines 10 - 20] teaches the empty spaces are assigned the appropriate decoupling capacitances and in the spine area 55 of the DRAM chip there are many irregular empty spaces 81, 82, 83, 84, 85, 86 where different kinds of decoupling capacitors for different power supplies can be automatically generated.
Reith differs from the claimed invention in that it does not explicitly disclose receiving input data defining the semiconductor device; wherein the first layout includes a plurality of blocks, a plurality of standard cells; a plurality of clock wirings, and a plurality of non-clock signal wirings; obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data; obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region.
Wang teaches receiving input data defining the semiconductor device; Wang [0036] teaches net list is data describing connection information of semiconductor circuits formed on a semiconductor substrate and library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region. Wang [0043] teaches the interface part 11 obtains a net list, library information, floor plan information and technology information as input data defining the semiconductor device.
Wang teaches wherein the first layout includes a plurality of blocks, a plurality of standard cells; Wang [0037] teaches the term block refers to a region containing multiple standard cells and macrocells logically related to one another where multiple blocks are placed in an placement region. Wang [0036] teaches library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region.
Wang teaches a plurality of clock wirings, and a plurality of non-clock signal wirings; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where routing is performed to connect circuit elements. It would be obvious to a person of ordinary skill in the art that any functional semiconductor device inherently requires both clock distribution networks to provide timing synchronization signals and non-clock signal networks to transmit data and control signals between circuit elements, making plurality of clock wirings and plurality of non-clock signal wirings an obvious and necessary aspect of semiconductor layout design that standard P&R tools would accommodate.
Wang teaches obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans in response to input data including net list, library information, and floor plan information.
Reith differs from the claimed invention in that it does not explicitly disclose obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region.
Chadwick teaches obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region; Chadwick [0031], [0034], [0035], and [0037] teach that decoupling capacitor cells are selected from predefined decoupling capacitor cells in an ASIC cell library and laid out in blocks, and that a block containing a first decoupling capacitor cell is reconfigured by replacing that decoupling capacitor cell with a substitute decoupling capacitor cell having a different size, a different aspect ratio and/or serpentined edges. Chadwick [0037] teaches that to adjust a block one or more decoupling capacitors in that block are replaced with one or more substitute decoupling capacitors, for example replacing one large decoupling capacitor with one or more banks of smaller decoupling capacitors, directly teaching obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the input data, blocks, standard cells, and automated layout generation that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
In regards to claim 2 (Reith modified by Wang) does not show: replacing the first decoupling capacitor cell having a first structure with the second decoupling capacitor cell having a second structure different from the first structure;
Chadwick teaches replacing the first decoupling capacitor cell having a first structure with the second decoupling capacitor cell having a second structure different from the first structure; Chadwick [0035], [0037], and [0039] teach that a first decoupling capacitor cell having a first structure is replaced with a substitute decoupling capacitor cell having the same decoupling capacitance but a different size, a different aspect ratio and/or serpentined edges, such that the reconfigured block has different polysilicon shapes than the original block. Chadwick [0037] teaches replacing a lower aspect ratio decoupling capacitor with a higher aspect ratio decoupling capacitor and replacing one large decoupling capacitor with banks of smaller decoupling capacitors, and Chadwick [0039] teaches selecting a substitute decoupling capacitor cell from amongst the predefined decoupling capacitor cells in an ASIC cell library, directly teaching replacing the first decoupling capacitor cell having a first structure with a second decoupling capacitor cell having a second structure different from the first structure.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the input data, blocks, standard cells, and automated layout generation that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
In regards to claim 7 (Reith) shows the method of claim 1, wherein the setting of the target region on the first layout includes:
setting the target region on a partial region of the semiconductor device; Reith [Column 3 Lines 50 - 65] teaches all remaining empty space on the chip gets identified by a layout tool and the empty spaces are assigned the appropriate decoupling capacitances where the target regions are set on partial regions of the semiconductor device that contain unused or empty areas. Reith [Column 4 Lines 10 - 25] teaches the spine area 55 of the DRAM chip has many irregular empty spaces where different kinds of decoupling capacitors can be automatically generated demonstrating setting target regions on partial regions.
In regards to claim 8 (Reith) shows the method of claim 7, wherein the setting of the target region on the partial region of the semiconductor device includes:
setting a first region included in the semiconductor device as the target region, wherein the plurality of blocks and the plurality of standard cells are not disposed in the first region; Reith [Column 3 Lines 50-65] teaches that all remaining empty space on the chip gets identified by a layout tool and then the empty spaces are assigned the appropriate decoupling capacitances, which shows setting empty regions without functional elements as target regions. Reith [Column 4 Lines 10-25] teaches that in the spine area of the DRAM chip there are many irregular empty spaces where different kinds of decoupling capacitors can be automatically generated, which shows specific regions where blocks and standard cells are not disposed becoming target regions for capacitor placement.
In regards to claim 9 (Reith) shows the method of claim 8:
wherein the first region is proximate to at least one of a corner of the semiconductor device, an edge portion of the semiconductor device, and a center portion of the semiconductor device; Reith [Column 2 Lines 55 - 65] teaches it is common to form dummy patterns around the edge of a semiconductor chip array to avoid problems associated with non-uniform patterns which form along the edges of an array. Reith [Column 4 Lines 10 - 25] teaches in the spine area 55 of the DRAM chip there are many irregular empty spaces indicating regions near center portions and edges where decoupling capacitors can be formed.
In regards to claim 19 (Reith) shows a design system for a semiconductor device, the design system comprising:
a plurality of decoupling capacitor cells, a plurality of filler cells; Reith [Column 3 Lines 65 - Column 4 Lines 5] teaches deep trench lithographic fill patterns can be used to form decoupling capacitors for lower voltage power supplies and gate filler or GC and diffusion filler AA could be combined to form plate or FET-capacitors. Reith [Column 4 Lines 10-20] teaches different kinds of decoupling capacitors for different power supplies can be automatically generated in irregular empty spaces demonstrating plurality of decoupling capacitor cells and plurality of filler cells.
a plurality of power wirings, a plurality of ground wirings; Reith [Column 4 Lines 25-40] teaches the bottom plate is contacted by the first group of metal studs which are later linked by metal wiring and the top plate is contacted by a second group of metal studs and will be later linked by metal wire demonstrating multiple wiring connections for power and ground. Reith [Column 3 Lines 55-65] teaches the closest power-supply nets get extracted and all power-supplies and their combinations are sorted in a connection table.
set a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells; Reith [Column 3 Lines 50 - 65] teaches when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool and then the closest power-supply nets get extracted by using another layout checking tool. Reith [Column 4 Lines 10 - 20] teaches the empty spaces are assigned the appropriate decoupling capacitances and in the spine area 55 of the DRAM chip there are many irregular empty spaces 81, 82, 83, 84, 85, 86 where different kinds of decoupling capacitors for different power supplies can be automatically generated.
Reith differs from the claimed invention in that it does not explicitly disclose a storage device configured to store information including procedures; a processor configured to access the storage device and execute the procedures; obtain a first layout of the semiconductor device by performing a placement and routing in response to the input data; wherein the procedures include a design module configured to: receive input data defining the semiconductor device; the first layout including a plurality of blocks, a plurality of standard cells; a plurality of clock wirings, and a plurality of non-clock signal wirings; obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region.
Wang teaches a storage device configured to store information including procedures; Wang [0033] teaches the semiconductor layout design apparatus includes a processor 1, a display device 2, a net list memory device 3, a library information memory device 4, a floor plan information memory device 5, a technology information memory device 6, and a floor plan evaluation result memory device 7 where the processor 1 and memory devices are interconnected through a network line 8. Wang [0036] teaches library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region.
Wang teaches a processor configured to access the storage device and execute the procedures; Wang [0033] teaches the semiconductor layout design apparatus includes a processor 1 and memory devices interconnected through a network line 8. Wang [0034] teaches the processor 1 includes an interface part 11, an inter-block connection information extracting part 12, a cell initial placement part 13, a candidate floor plan generating part 14, a floor plan evaluation value calculating part 15, a floor plan selecting part 16, an placement optimizing part 17, and a verifying part 18.
Wang teaches obtain a first layout of the semiconductor device by performing a placement and routing in response to the input data; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans in response to input data including net list, library information, and floor plan information.
Wang teaches wherein the procedures include a design module configured to: receive input data defining the semiconductor device; Wang [0034] teaches the processor 1 includes an interface part 11, an inter-block connection information extracting part 12, a cell initial placement part 13, a candidate floor plan generating part 14, a floor plan evaluation value calculating part 15, a floor plan selecting part 16, an placement optimizing part 17, and a verifying part 18. Wang [0035] teaches the interface part 11 performs processing for retrieving a net list, library information, floor plan information, and technology information from the respective memory devices.
Wang teaches the first layout including a plurality of blocks, a plurality of standard cells; Wang [0037] teaches the term block refers to a region containing multiple standard cells and macrocells logically related to one another where multiple blocks are placed in an placement region. Wang [0036] teaches library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region.
Wang teaches a plurality of clock wirings, and a plurality of non-clock signal wirings; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where routing is performed to connect circuit elements, where standard placement and routing tools inherently route both clock distribution networks for timing synchronization and non-clock signal networks for data transmission to circuit modules, thereby rendering obvious plurality of clock wirings and plurality of non-clock signal wirings.
Reith differs from the claimed invention in that it does not explicitly disclose obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region.
Chadwick teaches obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region; Chadwick [0031], [0035], and [0037] - [0039] teach that the design system, implemented on a processor and storage device, reconfigures a block by replacing a first decoupling capacitor cell with a substitute decoupling capacitor cell selected from predefined decoupling capacitor cells in an ASIC cell library and having a structure different from the first. The design module of the combined system is thereby configured to obtain the second layout by changing the first decoupling capacitor cell to a second decoupling capacitor cell in the target region.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design system by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's processor and storage device architecture provides the system-level implementation that Reith's decoupling capacitor placement methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) as applied to claim 1 above, and further in view of US20180365363A1 (Heilprin).
In regards to claim 5 (Reith modified by Wang and Chadwick) does not show the method of claim 1, wherein the obtaining of the second layout includes: generating a first modified decoupling capacitor cell by adding at least one additional wiring to the first decoupling capacitor cell while otherwise maintaining a structure of the first decoupling capacitor cell;
Heilprin teaches generating a first modified decoupling capacitor cell by adding at least one additional wiring to the first decoupling capacitor cell while otherwise maintaining a structure of the first decoupling capacitor cell; Heilprin [0086] and [0092] teach that a decoupling capacitor cell is a two-terminal capacitor hooked to the relevant power supply on one terminal and to the respective ground on the other terminal, and that placing a decoupling capacitor in a certain location requires a cell routing change in Metal-1 in order to both accommodate and route the cell appropriately. This adds at least one additional wiring to the decoupling capacitor cell while the decoupling capacitor cell itself is maintained, directly teaching generating a first modified decoupling capacitor cell by adding at least one additional wiring to the first decoupling capacitor cell while otherwise maintaining a structure of the first decoupling capacitor cell.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
The motivation to combine Reith, Wang, Chadwick, and Heilprin at the effective filing date of the invention is that Heilprin teaches adding routing wiring to a decoupling capacitor cell in place while maintaining the cell, which the other references do not explicitly address. A person of ordinary skill in the art would have recognized that applying Heilprin's in-place wiring modification to the combined design flow enables targeted decoupling capacitor optimization without full cell replacement, with a reasonable expectation of success.
In regards to claim 6 (Reith modified by Wang and Chadwick) does not show the method of claim 5, wherein the generating of the first modified decoupling capacitor cell includes: arranging at least one of an additional power wiring and an additional ground wiring in relation to the first decoupling capacitor cell in the target region; electrically connecting the first decoupling capacitor cell to the at least one of the additional power wiring and the additional ground wiring;
Heilprin teaches arranging at least one of an additional power wiring and an additional ground wiring in relation to the first decoupling capacitor cell in the target region; Heilprin [0086] and [0092] teach that decoupling capacitor cells are two-terminal capacitors hooked to the relevant power supply on one terminal and to the respective ground on the other terminal, and that inserting a decoupling capacitor requires a cell routing change to accommodate and route the power and ground connections appropriately in the target region, demonstrating arranging additional power and ground wiring in relation to the first decoupling capacitor cell in the target region.
Heilprin teaches electrically connecting the first decoupling capacitor cell to the at least one of the additional power wiring and the additional ground wiring; Heilprin [0086] teaches that the two-terminal decoupling capacitor is hooked to the relevant power supply on one terminal and to the respective ground on the other terminal, demonstrating electrically connecting the decoupling capacitor cell to additional power and ground wiring.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
The motivation to combine Reith, Wang, Chadwick, and Heilprin at the effective filing date of the invention is that Heilprin teaches adding routing wiring to a decoupling capacitor cell in place while maintaining the cell, which the other references do not explicitly address. A person of ordinary skill in the art would have recognized that applying Heilprin's in-place wiring modification to the combined design flow enables targeted decoupling capacitor optimization without full cell replacement, with a reasonable expectation of success.
Claims 3, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) as applied to claim 1 above, and further in view of US20060190892A1 (Haridass).
In regards to claim 3 (Reith) shows the method of claim 2:
wherein the target region further includes a first filler cell; Reith [Column 3 Lines 65 - Column 4 Lines 5] teaches deep trench lithographic fill patterns can be used to form decoupling capacitors for lower voltage power supplies and gate filler or GC and diffusion filler AA could be combined to form plate or FET-capacitors where filler cells are present in target regions that contain decoupling capacitors.
electrically connecting the second decoupling capacitor cell with at least one of a second power wiring and a second ground wiring disposed external to the target region; Reith [Column 3 Lines 55 - 65] teaches the closest power-supply nets get extracted by using another layout checking tool and all power-supplies and their combinations are sorted in a connection table which determines the appropriate type of capacitances once the power-supply nets closest to the empty spaces are extracted from the layout where electrical connections are established between decoupling capacitors and external power supply networks.
Reith differs from the claimed invention in that it does not explicitly disclose the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes; removing at least one of a first power wiring and a first ground wiring from at least one of the first decoupling capacitor cell and the first filler cell; arranging the second decoupling capacitor cell in the target region.
Chadwick teaches the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes; arranging the second decoupling capacitor cell in the target region; Chadwick [0035] and [0037] teach that replacing a first decoupling capacitor cell with a substitute decoupling capacitor cell comprises arranging the substitute decoupling capacitor cell in the reconfigured block in place of the original decoupling capacitor cell, directly teaching that the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes arranging the second decoupling capacitor cell in the target region.
Chadwick differs from the claimed invention in that it does not explicitly disclose removing at least one of a first power wiring and a first ground wiring from at least one of the first decoupling capacitor cell and the first filler cell.
Haridass teaches removing at least one of a first power wiring and a first ground wiring from at least one of the first decoupling capacitor cell and the first filler cell; Haridass [0047] teaches that adding or removing decoupling capacitors may also require minor changes to the power wiring as well, directly teaching that replacing a decoupling capacitor cell requires removing associated power or ground wiring from the first decoupling capacitor cell or filler cell.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
The motivation to combine Reith, Wang, Chadwick, and Haridass at the effective filing date of the invention is that Haridass teaches that removing a decoupling capacitor requires corresponding changes to the power wiring, which Chadwick does not explicitly address. A person of ordinary skill in the art would have recognized that when replacing a decoupling capacitor cell, associated power and ground wiring must be removed as taught by Haridass, with a reasonable expectation of success.
In regards to claim 10 (Reith modified by Wang and Chadwick) does not show the method of claim 7, wherein the setting of the target region on the partial region of the semiconductor device includes: upon determining that a wiring density of a first region included in the semiconductor device is less than a reference wiring density, setting the first region as the target region;
Haridass teaches upon determining that a wiring density of a first region included in the semiconductor device is less than a reference wiring density, setting the first region as the target region; Haridass [0025], [0027], [0041], [0044], and [0048] teach a mechanism for determining required decoupling capacitance for portions of an integrated circuit and identifying the location for decoupling capacitor insertion. Haridass [0041] teaches that the power grid description analyzed per region contains wiring geometry information including line width, height, and spacing that impacts wiring and propagation properties. Haridass [0044] teaches collecting wiring capacitance per region and Haridass [0048] teaches subdividing the chip into cells for per-region analysis. By analyzing wiring properties per region relative to predetermined thresholds to identify regions requiring decoupling capacitor modification, Haridass teaches determining that a wiring density of a first region is less than a reference wiring density and setting that region as the target region.
The motivation to combine Reith, Wang, Chadwick, and Haridass at the effective filing date of the invention is that Haridass provides per-region wiring density analysis to identify target regions for decoupling capacitor modification, which Reith, Wang, and Chadwick do not teach. A person of ordinary skill in the art would have recognized that applying Haridass's wiring density framework within the combined Reith/Wang/Chadwick design flow produces more targeted decoupling capacitor optimization with a reasonable expectation of success.
In regards to claim 12 (Reith modified by Wang and Chadwick) does not show the method of claim 7, wherein the setting of the target region on the partial region of the semiconductor device includes: upon determining that a width of wirings disposed in a first region included in the semiconductor device is less than a reference width, setting the first region as the target region.
Haridass teaches upon determining that a width of wirings disposed in a first region included in the semiconductor device is less than a reference width, setting the first region as the target region; Haridass [0041] teaches that the power grid description analyzed per region contains wiring geometry information including line width, which is identified as a parameter that impacts wiring and propagation properties. The per-region analysis of wiring line width as a criterion for identifying target regions for decoupling capacitor modification directly teaches determining that a width of wirings in a first region is less than a reference width and setting that region as the target region.
The motivation to combine Reith, Wang, Chadwick, and Haridass at the effective filing date of the invention is that Haridass provides per-region wiring geometry analysis including line width to identify target regions for decoupling capacitor modification, which Reith, Wang, and Chadwick do not teach. A person of ordinary skill in the art would have recognized that applying Haridass's wiring width analysis within the combined design flow produces more targeted decoupling capacitor optimization with a reasonable expectation of success.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) as applied to claims 2 and 1 respectively above, and further in view of US20130248957A1 (Kito).
In regards to claim 4 (Reith modified by Wang and Chadwick) does not show the method of claim 2, wherein the second decoupling capacitor cell includes: a first power wiring and a first ground wiring in a first wiring layer among a plurality of vertically stacked wiring layers, wherein the first power wiring and the first ground wiring extend in a first direction; a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer, wherein the second power wiring and the second ground wiring extend in a second direction intersecting the first direction; a first via electrically connecting the first power wiring and the second power wiring; and a second via electrically connecting the first ground wiring and the second ground wiring;
Kito teaches a first power wiring and a first ground wiring in a first wiring layer among a plurality of vertically stacked wiring layers, wherein the first power wiring and the first ground wiring extend in a first direction; Kito [0057] and [0075] teach that the second decoupling capacitor includes decoupling capacitor members 31a and 31b constituted by a first layer of metal extending in a plane direction of the semiconductor substrate, and power rails 40a and 40b constituted by a second layer of metal on the semiconductor substrate facing portions of the decoupling capacitor members. Kito [0075] confirms that the decoupling capacitor members are constituted by first layer metal and the power rails are constituted by second layer metal, directly teaching first and second vertically adjacent wiring layers with power and ground wirings extending in respective directions.
Kito teaches a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer, wherein the second power wiring and the second ground wiring extend in a second direction intersecting the first direction; Kito [0057] and [0075] teach that power rails 40a and 40b are constituted by a second layer of metal on the semiconductor substrate that faces portions of the decoupling capacitor members in the first layer, directly teaching a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer extending in a second direction intersecting the first direction.
Kito teaches a first via electrically connecting the first power wiring and the second power wiring; and a second via electrically connecting the first ground wiring and the second ground wiring; Kito [0053] and [0057] teach that a contact (reference numeral 81) is provided in the decoupling capacitor cell and that the power rails 40a and 40b constituted by the second layer of metal face and are electrically connected to portions of the decoupling capacitor members 31a and 31b constituted by the first layer of metal, thereby providing a first via electrically connecting the first and second power wirings and a second via electrically connecting the first and second ground wirings between the adjacent wiring layers.
The motivation to combine Reith, Wang, and Chadwick at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that Chadwick's technique of replacing a first decoupling capacitor cell with a structurally different substitute decoupling capacitor cell directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
The motivation to combine Reith, Wang, Chadwick, and Kito at the effective filing date of the invention is that Kito provides an explicit two-layer metal decoupling capacitor structure with vertically stacked wiring layers and inter-layer connections, which Chadwick does not detail. A person of ordinary skill in the art would have recognized that applying Kito's multi-layer wiring structure to the second decoupling capacitor cell produced by the combined design flow results in improved capacitance density with a reasonable expectation of success.
In regards to claim 13 (Reith modified by Wang and Chadwick) does not show the method of claim 1, wherein the setting of the target region on the first layout includes: setting the target region on a partial sub-region of a first block among the plurality of blocks included in the semiconductor device.
Kito teaches setting the target region on a partial sub-region of a first block among the plurality of blocks included in the semiconductor device; Kito [0069], [0071], and [0072] teach that the cell-based IC includes functional blocks constructed by custom layout cells and basic standard layout cells constituting a plurality of blocks, and FIG. 11 of Kito shows an enlarged partial region 103a of the basic cells from which the unused region 150 is extracted and designated as the target region for decoupling capacitor insertion. This directly teaches setting a target region on a partial sub-region of a first block among the plurality of blocks included in the semiconductor device.
The motivation to combine Reith, Wang, Chadwick, and Kito at the effective filing date of the invention is that Kito provides the framework for identifying unused sub-regions within blocks as target regions for decoupling capacitor modification, which Reith, Wang, and Chadwick do not teach at the block sub-region level. A person of ordinary skill in the art would have recognized that applying Kito's sub-region identification methodology within the combined design flow enables more precise target region selection with a reasonable expectation of success.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) and in view of US20060190892A1 (Haridass) as applied to claim 10 above, and further in view of US7600208B1 (Sharma).
In regards to claim 11 (Reith modified by Wang, Chadwick, and Haridass) does not show the method of claim 10: wherein the first region includes at least one of a clock wiring among the plurality of clock wirings and a non-clock signal wiring among the plurality of non-clock signal wirings, and the wiring density of the first region is determined in accordance with the at least one of the clock wiring and the non-clock signal wiring.
Sharma teaches wherein the first region includes at least one of a clock wiring among the plurality of clock wirings and a non-clock signal wiring among the plurality of non-clock signal wirings, and the wiring density of the first region is determined in accordance with the at least one of the clock wiring and the non-clock signal wiring; Sharma [Column 4 Lines 30-55] and [Column 6 Lines 40-65] teach that clock tree components are high drive cells that switch every clock cycle, explicitly distinguishing clock network components from non-clock signal cells. Sharma's timing window analysis per region treats clock-driven cell switching separately from non-clock logic cell switching to determine decoupling capacitance needs per region, directly teaching that wiring density of a first region is determined in accordance with both clock wirings and non-clock signal wirings as distinct categories.
The motivation to combine Reith, Wang, Chadwick, Haridass, and Sharma at the effective filing date of the invention is that Sharma explicitly distinguishes clock wirings from non-clock signal wirings when performing per-region decoupling capacitor analysis, which Haridass does not explicitly address. A person of ordinary skill in the art would have recognized that combining Haridass's wiring density analysis with Sharma's clock/non-clock distinction produces a more accurate target region selection method with a reasonable expectation of success.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) as applied to claim 13 above, and in view of US20060190892A1 (Haridass) and further in view of US20130248957A1 (Kito).
In regards to claim 14 (Reith modified by Wang and Chadwick) does not show the method of claim 13, wherein the setting of the target region on the partial sub-region of the first block includes at least one of: upon determining that the plurality of standard cells is not disposed in a first sub-region, setting the first sub-region included in the first block as the target region; upon determining that a wiring density of a first sub-region included in the first block is less than a reference wiring density, setting the first sub-region as the target region; and upon determining that a width of wirings disposed in a first sub-region included in the first block is less than a reference width, setting the first sub-region as the target region;
Haridass teaches upon determining that a wiring density of a first sub-region included in the first block is less than a reference wiring density, setting the first sub-region as the target region; Haridass [0041] and [0048] teach that wiring geometry properties including line width and wiring density are analyzed per region of an integrated circuit to identify candidates for decoupling capacitor placement or modification. Applied to the sub-region context of Kito's block sub-region framework, this teaches setting the first sub-region as a target based on wiring density criteria.
Haridass teaches upon determining that a width of wirings disposed in a first sub-region included in the first block is less than a reference width, setting the first sub-region as the target region; Haridass [0041] teaches that wiring geometry information including line width is analyzed per region as a parameter that impacts wiring and propagation properties. Applied to the sub-region context of Kito's block sub-region framework, this teaches setting the first sub-region as a target based on wiring width criteria.
Haridass differs from the claimed invention in that it does not explicitly disclose upon determining that the plurality of standard cells is not disposed in a first sub-region, setting the first sub-region included in the first block as the target region.
Kito teaches upon determining that the plurality of standard cells is not disposed in a first sub-region, setting the first sub-region included in the first block as the target region; Kito [0072] and [0078] teach that the unused region 150 not occupied by a basic cell is extracted at Step S100 and designated as the target region for decoupling capacitor insertion. This directly teaches setting a first sub-region included in the first block as the target region upon determining that the plurality of standard cells are not disposed therein.
The motivation to combine Reith, Wang, Chadwick, and Haridass at the effective filing date of the invention is that Haridass provides per-region wiring density and wiring width analysis to identify target sub-regions within blocks for decoupling capacitor modification, which Reith, Wang, and Chadwick do not teach. A person of ordinary skill in the art would have recognized that applying Haridass's wiring property criteria within Kito's block sub-region framework produces a comprehensive target sub-region selection methodology with a reasonable expectation of success.
The motivation to combine Reith, Wang, Chadwick, Haridass, and Kito at the effective filing date of the invention is that Kito provides the explicit framework for identifying unused sub-regions within blocks as target regions based on the absence of standard cells, which Haridass does not teach. A person of ordinary skill in the art would have recognized that combining Haridass's wiring property criteria with Kito's sub-region framework produces a complete and flexible target sub-region selection methodology with a reasonable expectation of success.
Claims 15 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) as applied to claim 1 above, and in view of US7600208B1 (Sharma) and further in view of US20180365363A1 (Heilprin).
In regards to claim 15 (Reith) shows the method of claim 1, wherein the obtaining of the first layout includes:
developing a power plan for the plurality of power wirings and the plurality of ground wirings; Reith [Column 3 Lines 55 - 65] teaches the closest power-supply nets get extracted by using another layout checking tool and all power-supplies and their combinations are sorted in a connection table for developing power plans.
Reith differs from the claimed invention in that it does not explicitly disclose developing a floor plan for the plurality of blocks, the plurality of standard cells, the plurality of decoupling capacitor cells and the plurality of filler cells; performing a placement of elements included in the plurality of blocks and the plurality of standard cells; performing a routing of non-clock signals provided to the elements via the plurality of non-clock signal wirings; performing a clock tree synthesis (CTS) of clock signals provided to the elements via the plurality of clock wirings.
Wang teaches developing a floor plan for the plurality of blocks, the plurality of standard cells, the plurality of decoupling capacitor cells and the plurality of filler cells; Wang [0038] teaches the candidate floor plan generating part 14 generates multiple candidate floor plans based on a net list, library information, floor plan information and technology information. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans.
Wang teaches performing a placement of elements included in the plurality of blocks and the plurality of standard cells; Wang [0044] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells based on the net list, library information, and floor plan information. Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths.
Wang teaches performing a routing of non-clock signals provided to the elements via the plurality of non-clock signal wirings; Wang [0074] teaches the processor executes an automatic P&R tool in which routing is performed to connect circuit elements, demonstrating routing of non-clock signals provided to the elements via the plurality of non-clock signal wirings.
Wang differs from the claimed invention in that it does not explicitly disclose performing a clock tree synthesis (CTS) of clock signals provided to the elements via the plurality of clock wirings.
Sharma teaches performing a clock tree synthesis (CTS) of clock signals provided to the elements via the plurality of clock wirings; Sharma [Column 6 Lines 40-65] teaches that the automatic decap cell placement process can be performed during clock tree synthesis, directly naming CTS as a specific phase of the ASIC design flow in which decoupling capacitor cells are also processed. Sharma [Column 4 Lines 30-55] further teaches that clock tree components are high drive cells and switch every clock cycle, confirming CTS as a distinct named step in the design flow that includes decoupling capacitor cell processing.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the input data, blocks, standard cells, and automated layout generation that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, Chadwick, and Sharma at the effective filing date of the invention is that Sharma explicitly names clock tree synthesis as a distinct named step in the ASIC design flow in which decoupling capacitor cells are processed, which Wang does not teach. A person of ordinary skill in the art would have recognized that CTS is a standard step in any synchronous IC P&R flow and that Sharma's explicit teaching confirms its inclusion with a reasonable expectation of success.
In regards to claim 16 (Reith modified by Wang, Chadwick, and Sharma) does not show the method of claim 15, further comprising: verifying results of the placement and routing, wherein the setting of the target region on the first layout and the obtaining of the second layout are performed during the verifying results of the placement and routing;
Heilprin teaches verifying results of the placement and routing, wherein the setting of the target region on the first layout and the obtaining of the second layout are performed during the verifying results of the placement and routing; Heilprin [0087], [0126], [0127], and [0128] teach that a final optimization of the placement of decoupling capacitors takes place after, or is interleaved with, the optimization and closure of timing, and that an implementation phase completion includes quality control operations that verify timing and DCR closure before design release to production. Heilprin [0104], [0113], and [0135] teach that during this timing-driven phase filler locations are prioritized and selected as target regions and the decoupling capacitor swap is performed, directly teaching that both the setting of the target region and the obtaining of the second layout are performed during the verifying results of the placement and routing.
The motivation to combine Reith, Wang, Chadwick, and Heilprin at the effective filing date of the invention is that Heilprin teaches performing the decoupling capacitor modification during the timing-closure and verification phase of the design flow, which the other references do not explicitly address. A person of ordinary skill in the art would have recognized that performing the target region setting and second layout modification during verification as taught by Heilprin integrates naturally into the combined design flow with a reasonable expectation of success.
In regards to claim 17 (Reith modified by Wang and Chadwick) does not show the method of claim 16, wherein the verifying results of the placement and routing includes: performing a timing engineering change order (ECO) process; determining whether a timing condition has been satisfied;
Heilprin teaches performing a timing engineering change order (ECO) process; Heilprin [0085], [0087], and [0113] teach that incremental routing changes commonly known as ECO are implemented during timing closure, and that fillers hosting Metal-1 nets are replaced with decoupling capacitors in a timing-driven manner as part of this engineering change order process, directly teaching performing a timing engineering change order (ECO) process.
Heilprin teaches determining whether a timing condition has been satisfied; Heilprin [0104], [0122], and [0128] teach that the timing slack of nets is checked against a predefined slack margin and that swaps are only performed when the timing condition is satisfied, and that any remaining timing violations are corrected until chip timing requirements have been met, directly teaching determining whether a timing condition has been satisfied.
The motivation to combine Reith, Wang, Chadwick, and Heilprin at the effective filing date of the invention is that Heilprin teaches performing the decoupling capacitor modification during the timing-closure and verification phase of the design flow, which the other references do not explicitly address. A person of ordinary skill in the art would have recognized that performing the target region setting and second layout modification during verification as taught by Heilprin integrates naturally into the combined design flow with a reasonable expectation of success.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) in view of US20080120582A1 (Wang) and in view of US20090278222A1 (Chadwick) and in view of US20180365363A1 (Heilprin) as applied to claim 17 above, and further in view of US20130248957A1 (Kito).
In regards to claim 18 (Reith modified by Wang, Chadwick, and Heilprin) does not show the method of claim 17, wherein upon determining the timing condition has been satisfied, the method further comprises: performing a physical design rule check and correction;
Kito teaches wherein upon determining the timing condition has been satisfied, the method further comprises: performing a physical design rule check and correction; Kito [0080], [0083], and [0085] teach that as part of the decoupling capacitor cell insertion process, the process checks whether a wiring short is modified at Step S102, constituting a physical design rule check. If a wiring short is found, the short circuit is corrected at Step S105, constituting a physical design rule correction. This directly teaches performing a physical design rule check and correction following determination that the timing condition has been satisfied.
The motivation to combine Reith, Wang, Chadwick, Heilprin, and Kito at the effective filing date of the invention is that Kito teaches performing a physical design rule check and correction as part of the decoupling capacitor cell insertion process, which the other references do not teach. A person of ordinary skill in the art would have recognized that a DRC check following decoupling capacitor cell modification is a standard and necessary step to ensure layout validity with a reasonable expectation of success.
Allowable Subject Matter
Claim 20 is allowed.
The following is an examiner's statement of reasons for allowance: the prior art of record, whether taken alone or in combination, does not teach or suggest a method of designing a layout of a semiconductor device that, while verifying results of the placement and routing, obtains a second layout by replacing a first decoupling capacitor cell in a target region with a second decoupling capacitor cell having a structure different from that of the first decoupling capacitor cell, wherein the replacing includes removing at least one of a first power wiring and a first ground wiring from the first decoupling capacitor cell and electrically connecting the second decoupling capacitor cell to a second power wiring and a second ground wiring external to the target region, in combination with the remaining limitations recited in claim 20.
Response to Arguments
Applicant's arguments filed July 7, 2026 have been fully considered but are not persuasive for the reasons set forth below. Applicant's amendment necessitated the new grounds of rejection set forth above, which no longer rely on Oh.
With respect to independent claims 1 and 19, Applicant argues that Oh describes a destructive functional transformation that changes a decoupling capacitor into a distinct logic device (a NAND gate) and therefore fails to teach changing a first decoupling capacitor cell to a second decoupling capacitor cell. This argument is directed to Oh and is moot because the present rejection no longer relies on Oh for this limitation. The rejection now relies on Chadwick, which at [0035], [0037], and [0039] expressly teaches replacing a first decoupling capacitor cell with a substitute decoupling capacitor cell, selected from predefined decoupling capacitor cells in an ASIC cell library, that remains a decoupling capacitor cell and has the same decoupling capacitance but a different size, aspect ratio, and/or serpentined edges. Chadwick thus teaches changing a first decoupling capacitor cell to a structurally different second decoupling capacitor cell while maintaining decoupling capacitor continuity, precisely the feature Applicant identifies as distinguishing.
With respect to independent claim 2, Applicant argues that the cited art fails to teach replacing a first decoupling capacitor cell having a first structure with a second decoupling capacitor cell having a different second structure. Chadwick [0037] teaches replacing a lower aspect ratio decoupling capacitor with a higher aspect ratio decoupling capacitor and replacing one large decoupling capacitor with banks of smaller decoupling capacitors, each replacement yielding a second decoupling capacitor cell whose structure differs from the first while retaining the same decoupling capacitance. This directly teaches the disputed limitation.
With respect to claim 14, Applicant argues that Kito is directed to extracting an unused region devoid of any first decoupling capacitor cell and therefore teaches away. This argument is not persuasive. Claim 14 recites the setting of the target sub-region in the alternative ("at least one of"), and Kito is relied upon only for the alternative of setting a sub-region in which the plurality of standard cells is not disposed, which corresponds directly to Kito's extraction of an unused region not occupied by a basic cell. The presence of the first decoupling capacitor cell in the target region is provided by the base combination of Reith and Chadwick, not by Kito. Accordingly, there is no teaching away, and the combination reads on the claim.
With respect to dependent claims 3-13 and 15-18, Applicant relies on the arguments advanced for claims 1, 2, and 19. For the reasons set forth above, those arguments are not persuasive, and the rejections are maintained as set forth in this Office action.
With respect to independent claim 20, Applicant's argument is persuasive. Claim 20 was previously rejected in reliance on Oh for replacing a first decoupling capacitor cell with a second decoupling capacitor cell having a different structure, and Applicant correctly notes that Oh instead changes a decoupling capacitor into a functionally distinct logic device rather than a second decoupling capacitor cell. Accordingly, the rejection of claim 20 is withdrawn, and claim 20 is allowed as set forth in the Allowable Subject Matter section above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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