Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5 – 9, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and further in view of US20170069660A1 (OH).
In regards to claim 1 (Reith) shows a method of designing a layout of a semiconductor device, the method comprising:
a plurality of decoupling capacitor cells, a plurality of filler cells; Reith [Column 3 Lines 65 - Column 4 Lines 5] teaches deep trench lithographic fill patterns can be used to form decoupling capacitors for lower voltage power supplies and gate filler or GC and diffusion filler AA could be combined to form plate or FET-capacitors. Reith [Column 4 Lines 10-20] teaches different kinds of decoupling capacitors for different power supplies can be automatically generated in irregular empty spaces demonstrating plurality of decoupling capacitor cells and plurality of filler cells.
a plurality of power wirings, a plurality of ground wirings; Reith [Column 4 Lines 25-40] teaches the bottom plate is contacted by the first group of metal studs which are later linked by metal wiring and the top plate is contacted by a second group of metal studs and will be later linked by metal wire demonstrating multiple wiring connections for power and ground. Reith [Column 3 Lines 55-65] teaches the closest power-supply nets get extracted and all power-supplies and their combinations are sorted in a connection table.
setting a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells; Reith [Column 3 Lines 50 - 65] teaches when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool and then the closest power-supply nets get extracted by using another layout checking tool. Reith [Column 4 Lines 10 - 20] teaches the empty spaces are assigned the appropriate decoupling capacitances and in the spine area 55 of the DRAM chip there are many irregular empty spaces 81, 82, 83, 84, 85, 86 where different kinds of decoupling capacitors for different power supplies can be automatically generated.
Reith differs from the claimed invention in that it does not explicitly disclose receiving input data defining the semiconductor device; wherein the first layout includes a plurality of blocks, a plurality of standard cells; a plurality of clock wirings, and a plurality of non-clock signal wirings; obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data; obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region;
Wang teaches receiving input data defining the semiconductor device; Wang [0036] teaches net list is data describing connection information of semiconductor circuits formed on a semiconductor substrate and library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region. Wang [0043] teaches the interface part 11 obtains a net list, library information, floor plan information and technology information as input data defining the semiconductor device.
Wang teaches wherein the first layout includes a plurality of blocks, a plurality of standard cells; Wang [0037] teaches the term block refers to a region containing multiple standard cells and macrocells logically related to one another where multiple blocks are placed in an placement region. Wang [0036] teaches library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region.
Wang teaches a plurality of clock wirings, and a plurality of non-clock signal wirings; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where routing is performed to connect circuit elements. It would be obvious to a person of ordinary skill in the art that any functional semiconductor device inherently requires both clock distribution networks to provide timing synchronization signals and non-clock signal networks to transmit data and control signals between circuit elements, making plurality of clock wirings and plurality of non-clock signal wirings an obvious and necessary aspect of semiconductor layout design that standard P&R tools would accommodate.
Wang teaches obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans in response to input data including net list, library information, and floor plan information.
Reith differs from the claimed invention in that it does not explicitly disclose obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region;
OH teaches obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region; OH [0053], [0060], [0063], [0064], and [0085] teach that a spare gate cell is first formed in the type of a decoupling capacitor and exists in the layout as a preexisting first decoupling capacitor cell. When an ECO event occurs after testing, the preexisting decoupling capacitor cell in the target region is changed by forming an interconnection metal line pattern at that cell, converting it into a functionally different ECO cell structure and producing a modified second layout. This directly teaches obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the input data, blocks, standard cells, and automated layout generation that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces, with a reasonable expectation of success.
In regards to claim 2 (Reith) does not show: replacing the first decoupling capacitor cell having a first structure with a second decoupling capacitor cell having a second structure different from the first structure;
OH teaches replacing the first decoupling capacitor cell having a first structure with a second decoupling capacitor cell having a second structure different from the first structure; OH [0060], [0063]–[0064], [0071]–[0072], and [0085] teach that a spare gate cell formed in the type of a decoupling capacitor (first structure — source/drain connected MOS transistors) is changed into an ECO cell having a different structure (second structure — an inverter or NAND gate circuit) by forming a new interconnection metal line pattern. FIGS. 4/6 show the first decoupling capacitor structure and FIGS. 5/7 show the resulting second structure that is explicitly different from the first, directly teaching replacing a first decoupling capacitor cell having a first structure with a second decoupling capacitor cell having a second structure different from the first.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the input data, blocks, standard cells, and automated layout generation that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place rather than only placing new cells in empty spaces. OH further provides the explicit teaching of replacing a first decoupling capacitor cell structure with a second structurally different cell, which Reith and Wang do not teach, with a reasonable expectation of success.
In regards to claim 5 (Reith) does not show, wherein the obtaining of the second layout includes: generating a first modified decoupling capacitor cell by adding at least one additional wiring to the first decoupling capacitor cell while otherwise maintaining a structure of the first decoupling capacitor cell;
OH teaches generating a first modified decoupling capacitor cell by adding at least one additional wiring to the first decoupling capacitor cell while otherwise maintaining a structure of the first decoupling capacitor cell; OH [0064], [0082], and [0083] teach that an interconnection metal line pattern is formed at the spare gate cell formed in the type of a decoupling capacitor, adding metal wiring while the underlying transistor structure including gates, source/drain regions, and polysilicon remains intact. Parts A and C are electrically connected through a metal interconnection while the base transistor structure remains unchanged, directly teaching adding at least one additional wiring to the first decoupling capacitor cell while otherwise maintaining its structure.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place. OH further provides the explicit teaching of adding wiring to an existing decoupling capacitor cell while maintaining its underlying transistor structure, enabling targeted layout modification without full cell replacement, with a reasonable expectation of success.
In regards to claim 6 (Reith modified by Wang) does not show, wherein the generating of the first modified decoupling capacitor cell includes: arranging at least one of an additional power wiring and an additional ground wiring in relation to the first decoupling capacitor cell in the target region; electrically connecting the first decoupling capacitor cell to the at least one of the additional power wiring and the additional ground wiring;
OH teaches arranging at least one of an additional power wiring and an additional ground wiring in relation to the first decoupling capacitor cell in the target region; OH [0082] and [0083] teach that parts A and C of the spare gate cell are electrically connected through a metal interconnection formed at an upper metal layer in the target region, and pintext adding is performed to define power and ground connections for the rerouted cell, demonstrating arrangement of additional power and ground wiring in relation to the first decoupling capacitor cell in the target region.
OH teaches electrically connecting the first decoupling capacitor cell to the at least one of the additional power wiring and the additional ground wiring; OH [0064] and [0079] teach that during change into an ECO cell, metal line 30 is connected to the source of the PMOS transistors and metal line 40 is connected to the drain of the NMOS transistors, demonstrating electrical connection of the modified decoupling capacitor cell to additional power and ground wiring.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be changed in place. OH further provides the explicit teaching of arranging additional power and ground wiring connections at an existing decoupling capacitor cell in the target region, enabling power network optimization during the ECO process, with a reasonable expectation of success.
In regards to claim 7 (Reith) shows the method of claim 1, wherein the setting of the target region on the first layout includes:
setting the target region on a partial region of the semiconductor device; Reith [Column 3 Lines 50 - 65] teaches all remaining empty space on the chip gets identified by a layout tool and the empty spaces are assigned the appropriate decoupling capacitances where the target regions are set on partial regions of the semiconductor device that contain unused or empty areas. Reith [Column 4 Lines 10 - 25] teaches the spine area 55 of the DRAM chip has many irregular empty spaces where different kinds of decoupling capacitors can be automatically generated demonstrating setting target regions on partial regions.
In regards to claim 8 (Reith) shows the method of claim 7, wherein the setting of the target region on the partial region of the semiconductor device includes:
setting a first region included in the semiconductor device as the target region, wherein the plurality of blocks and the plurality of standard cells are not disposed in the first region; Reith [Column 3 Lines 50-65] teaches that all remaining empty space on the chip gets identified by a layout tool and then the empty spaces are assigned the appropriate decoupling capacitances, which shows setting empty regions without functional elements as target regions. Reith [Column 4 Lines 10-25] teaches that in the spine area of the DRAM chip there are many irregular empty spaces where different kinds of decoupling capacitors can be automatically generated, which shows specific regions where blocks and standard cells are not disposed becoming target regions for capacitor placement.
In regards to claim 9 (Reith) shows the method of claim 8:
wherein the first region is proximate to at least one of a corner of the semiconductor device, an edge portion of the semiconductor device, and a center portion of the semiconductor device; Reith [Column 2 Lines 55 - 65] teaches it is common to form dummy patterns around the edge of a semiconductor chip array to avoid problems associated with non-uniform patterns which form along the edges of an array. Reith [Column 4 Lines 10 - 25] teaches in the spine area 55 of the DRAM chip there are many irregular empty spaces indicating regions near center portions and edges where decoupling capacitors can be formed.
In regards to claim 19 (Reith) shows a design system for a semiconductor device, the design system comprising:
a plurality of decoupling capacitor cells, a plurality of filler cells; Reith [Column 3 Lines 65 - Column 4 Lines 5] teaches deep trench lithographic fill patterns can be used to form decoupling capacitors for lower voltage power supplies and gate filler or GC and diffusion filler AA could be combined to form plate or FET-capacitors. Reith [Column 4 Lines 10-20] teaches different kinds of decoupling capacitors for different power supplies can be automatically generated in irregular empty spaces demonstrating plurality of decoupling capacitor cells and plurality of filler cells.
a plurality of power wirings, a plurality of ground wirings; Reith [Column 4 Lines 25-40] teaches the bottom plate is contacted by the first group of metal studs which are later linked by metal wiring and the top plate is contacted by a second group of metal studs and will be later linked by metal wire demonstrating multiple wiring connections for power and ground. Reith [Column 3 Lines 55-65] teaches the closest power-supply nets get extracted and all power-supplies and their combinations are sorted in a connection table.
set a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells; Reith [Column 3 Lines 50 - 65] teaches when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool and then the closest power-supply nets get extracted by using another layout checking tool. Reith [Column 4 Lines 10 - 20] teaches the empty spaces are assigned the appropriate decoupling capacitances and in the spine area 55 of the DRAM chip there are many irregular empty spaces 81, 82, 83, 84, 85, 86 where different kinds of decoupling capacitors for different power supplies can be automatically generated.
Reith differs from the claimed invention in that it does not explicitly disclose a storage device configured to store information including procedures; a processor configured to access the storage device and execute the procedures; obtain a first layout of the semiconductor device by performing a placement and routing in response to the input data; wherein the procedures includes a design module configured to: receive input data defining the semiconductor device; the first layout including a plurality of blocks, a plurality of standard cells; a plurality of clock wirings, and a plurality of non-clock signal wirings; obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region;
Wang teaches a storage device configured to store information including procedures; Wang [0033] teaches the semiconductor layout design apparatus includes a processor 1, a display device 2, a net list memory device 3, a library information memory device 4, a floor plan information memory device 5, a technology information memory device 6, and a floor plan evaluation result memory device 7 where the processor 1 and memory devices are interconnected through a network line 8. Wang [0036] teaches library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region.
Wang teaches a processor configured to access the storage device and execute the procedures; Wang [0033] teaches the semiconductor layout design apparatus includes a processor 1, a display device 2, a net list memory device 3, a library information memory device 4, a floor plan information memory device 5, a technology information memory device 6, and a floor plan evaluation result memory device 7 where the processor 1 and memory devices are interconnected through a network line 8. Wang [0034] teaches the processor 1 includes an interface part 11, an inter-block connection information extracting part 12, a cell initial placement part 13, a candidate floor plan generating part 14, a floor plan evaluation value calculating part 15, a floor plan selecting part 16, an placement optimizing part 17, and a verifying part 18.
Wang teaches obtain a first layout of the semiconductor device by performing a placement and routing in response to the input data; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans in response to input data including net list, library information, and floor plan information.
Wang teaches wherein the procedures includes a design module configured to: receive input data defining the semiconductor device; Wang [0034] teaches the processor 1 includes an interface part 11, an inter-block connection information extracting part 12, a cell initial placement part 13, a candidate floor plan generating part 14, a floor plan evaluation value calculating part 15, a floor plan selecting part 16, an placement optimizing part 17, and a verifying part 18. Wang [0035] teaches the interface part 11 performs processing for retrieving a net list stored in the net list memory device 3, library information stored in the library information memory device 4, floor plan information stored in the floor plan information memory device 5, and technology information stored in the technology information memory device 6.
Wang teaches the first layout including a plurality of blocks, a plurality of standard cells; Wang [0037] teaches the term block refers to a region containing multiple standard cells and macrocells logically related to one another where multiple blocks are placed in an placement region. Wang [0036] teaches library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region.
Wang teaches a plurality of clock wirings, and a plurality of non-clock signal wirings; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where routing is performed to connect circuit elements, where standard placement and routing tools inherently route both clock distribution networks for timing synchronization and non-clock signal networks for data transmission to circuit modules, thereby rendering obvious plurality of clock wirings and plurality of non-clock signal wirings.
Reith differs from the claimed invention in that it does not explicitly disclose obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region;
OH teaches obtain a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region; OH [0053], [0063], [0064], and [0085] teach that the cell-based IC layout system, when an ECO event occurs after testing, changes the preexisting decoupling capacitor cell by forming an interconnection metal line pattern, thereby producing a modified second layout. The design module of the combined system is configured to obtain the second layout by changing the first decoupling capacitor cell in the target region.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design system by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's processor and storage device architecture provides the system-level implementation that Reith's decoupling capacitor placement methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design system by configuring the design module to obtain the second layout by changing the first decoupling capacitor cell in the target region, with a reasonable expectation of success.
Claims 3, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) as applied to claim 1 respectively above, and further in view of US20060190892A1 (Haridass).
In regards to claim 3 (Reith) shows the method of claim 2:
wherein the target region further includes a first filler cell; Reith [Column 3 Lines 65 - Column 4 Lines 5] teaches deep trench lithographic fill patterns can be used to form decoupling capacitors for lower voltage power supplies and gate filler or GC and diffusion filler AA could be combined to form plate or FET-capacitors where filler cells are present in target regions that contain decoupling capacitors.
electrically connecting the second decoupling capacitor cell with at least one of a second power wiring and a second ground wiring disposed external to the target region; Reith [Column 3 Lines 55 - 65] teaches the closest power-supply nets get extracted by using another layout checking tool and all power-supplies and their combinations are sorted in a connection table which determines the appropriate type of capacitances once the power-supply nets closest to the empty spaces are extracted from the layout where electrical connections are established between decoupling capacitors and external power supply networks.
Reith differs from the claimed invention in that it does not explicitly disclose the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes; removing at least one of a first power wiring and a first ground wiring from at least one of the first decoupling capacitor cell and the first filler cell; arranging the second decoupling capacitor cell in the target region;
OH teaches the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes; arranging the second decoupling capacitor cell in the target region; OH [0064] and [0082] teach that when a spare gate cell existing as a decoupling capacitor is selected as an ECO cell, an interconnection metal line pattern is formed at that cell and specific wiring connections are rerouted, demonstrating that the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes arranging the new cell structure and establishing its connections in the target region.
OH differs from the claimed invention in that it does not explicitly disclose removing at least one of a first power wiring and a first ground wiring from at least one of the first decoupling capacitor cell and the first filler cell;
Haridass teaches removing at least one of a first power wiring and a first ground wiring from at least one of the first decoupling capacitor cell and the first filler cell; Haridass [0047] teaches that adding or removing decoupling capacitors may also require minor changes to the power wiring as well, directly teaching that replacing a decoupling capacitor cell requires removing associated power or ground wiring from the first decoupling capacitor cell or filler cell.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be replaced with a structurally different second cell in the target region, with a reasonable expectation of success.
The motivation to combine Reith, Wang, OH, and Haridass at the effective filing date of the invention is that Haridass teaches that removing a decoupling capacitor requires corresponding changes to power wiring, which OH does not explicitly address. A person of ordinary skill in the art would have recognized that when replacing a decoupling capacitor cell, associated power and ground wiring must be removed as taught by Haridass, with a reasonable expectation of success.
In regards to claim 10 (Reith modified by Wang and OH) does not show, wherein the setting of the target region on the partial region of the semiconductor device includes: upon determining that a wiring density of a first region included in the semiconductor device is less than a reference wiring density, setting the first region as the target region;
Haridass teaches upon determining that a wiring density of a first region included in the semiconductor device is less than a reference wiring density, setting the first region as the target region; Haridass [0025], [0027], [0041], [0044], and [0048] teach a mechanism for determining required decoupling capacitance for portions of an integrated circuit and identifying the location for decoupling capacitor insertion. Haridass [0041] teaches that the power grid description analyzed per region contains wiring geometry information including line width, height, and spacing that impacts wiring and propagation properties. Haridass [0044] teaches collecting wiring capacitance per region and Haridass [0048] teaches subdividing the chip into cells for per-region analysis. By analyzing wiring properties per region relative to predetermined thresholds to identify regions requiring decoupling capacitor modification, Haridass teaches determining that a wiring density of a first region is less than a reference wiring density and setting that region as the target region.
The motivation to combine Reith, Wang, OH, and Haridass at the effective filing date of the invention is that Haridass provides per-region wiring density analysis to identify target regions for decoupling capacitor modification, which Reith, Wang, and OH do not teach. A person of ordinary skill in the art would have recognized that applying Haridass's wiring density framework within the combined Reith/Wang/OH design flow produces more targeted decoupling capacitor optimization with a reasonable expectation of success.
In regards to claim 12 (Reith modified by Wang and OH) does not show the method of claim 7, wherein the setting of the target region on the partial region of the semiconductor device includes: upon determining that a width of wirings disposed in a first region included in the semiconductor device is less than a reference width, setting the first region as the target region.
Haridass teaches upon determining that a width of wirings disposed in a first region included in the semiconductor device is less than a reference width, setting the first region as the target region; Haridass [0041] teaches that the power grid description analyzed per region contains wiring geometry information including line width, which is identified as a parameter that impacts wiring and propagation properties. The per-region analysis of wiring line width as a criterion for identifying target regions for decoupling capacitor modification directly teaches determining that a width of wirings in a first region is less than a reference width and setting that region as the target region.
The motivation to combine Reith, Wang, OH, and Haridass at the effective filing date of the invention is that Haridass provides per-region wiring geometry analysis including line width to identify target regions for decoupling capacitor modification, which Reith, Wang, and OH do not teach. A person of ordinary skill in the art would have recognized that applying Haridass's wiring width analysis within the combined Reith/Wang/OH design flow produces more targeted decoupling capacitor optimization with a reasonable expectation of success.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) as applied to claim 1 respectively above, and further in view of US20130248957A1 (Kito).
In regards to claim 4 (Reith modified by Wang) does not show, wherein the second decoupling capacitor cell includes: a first power wiring and a first ground wiring in a first wiring layer among a plurality of vertically stacked wiring layers, wherein the first power wiring and first ground wiring extend in a first direction; a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer, wherein the second power wiring and the second ground wiring extend in a second direction intersecting the first direction; a first via electrically connecting the first power wiring and the second power wiring; and a second via electrically connecting the first ground wiring and the second ground wiring;
OH teaches a first via electrically connecting the first power wiring and the second power wiring; and a second via electrically connecting the first ground wiring and the second ground wiring; OH [0111] and [0113] teach via contacts that electrically connect between metal layers in the decoupling capacitor cell structure across multiple metal layers, and OH [0113] specifically teaches that a via contact is a contact to electrically connect between metal layers, directly teaching a second via electrically connecting the first ground wiring and the second ground wiring between adjacent wiring layers.
OH differs from the claimed invention in that it does not explicitly disclose a first power wiring and a first ground wiring in a first wiring layer among a plurality of vertically stacked wiring layers, wherein the first power wiring and first ground wiring extend in a first direction; a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer, wherein the second power wiring and the second ground wiring extend in a second direction intersecting the first direction;
Kito teaches a first power wiring and a first ground wiring in a first wiring layer among a plurality of vertically stacked wiring layers, wherein the first power wiring and first ground wiring extend in a first direction; Kito [0057] and [0075] teach that the second decoupling capacitor includes decoupling capacitor members 31a and 31b constituted by a first layer of metal extending in a plane direction of the semiconductor substrate, and power rails 40a and 40b constituted by a second layer of metal on the semiconductor substrate facing portions of the decoupling capacitor members. Kito [0075] confirms that the decoupling capacitor members are constituted by first layer metal and the power rails are constituted by second layer metal, directly teaching first and second vertically adjacent wiring layers with power and ground wirings extending in respective directions.
Kito teaches a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer, wherein the second power wiring and the second ground wiring extend in a second direction intersecting the first direction; Kito [0057] and [0075] teach that power rails 40a and 40b are constituted by a second layer of metal on the semiconductor substrate that faces portions of the decoupling capacitor members in the first layer, directly teaching a second power wiring and a second ground wiring in a second wiring layer adjacent to the first wiring layer extending in a second direction intersecting the first direction.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be replaced with a structurally different second cell, with a reasonable expectation of success.
The motivation to combine Reith, Wang, OH, and Kito at the effective filing date of the invention is that Kito provides an explicit two-layer metal decoupling capacitor structure with vertically stacked wiring layers, which OH does not teach. A person of ordinary skill in the art would have recognized that applying Kito's multi-layer wiring structure to the second decoupling capacitor cell produced by OH's ECO process results in improved capacitance density with a reasonable expectation of success.
In regards to claim 13 (Reith modified by Wang and OH) does not show the method of claim 1, wherein the setting of the target region on the first layout includes: setting the target region on a partial sub-region of a first block among the plurality of blocks included in the semiconductor device.
Kito teaches setting the target region on a partial sub-region of a first block among the plurality of blocks included in the semiconductor device; Kito [0069], [0071], and [0072] teach that the cell-based IC includes functional blocks constructed by custom layout cells and basic standard layout cells constituting a plurality of blocks, and FIG. 11 of Kito shows an enlarged partial region 103a of the basic cells from which the unused region 150 is extracted and designated as the target region for decoupling capacitor insertion. This directly teaches setting a target region on a partial sub-region of a first block among the plurality of blocks included in the semiconductor device.
The motivation to combine Reith, Wang, OH, and Kito at the effective filing date of the invention is that Kito provides the framework for identifying unused sub-regions within blocks as target regions for decoupling capacitor modification, which Reith, Wang, and OH do not teach at the block sub-region level. A person of ordinary skill in the art would have recognized that applying Kito's sub-region identification methodology within the combined design flow enables more precise target region selection with a reasonable expectation of success.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) and in view of US20060190892A1 (Haridass) as applied to claim 1 above, and further in view of US7600208B1 (Sharma).
In regards to claim 11 (Reith modified by Wang and OH) does not show the method of claim 10: wherein the first region includes at least one of a clock wiring among the plurality of clock wirings and a non-clock signal wiring among the plurality of non-clock signal wirings, and the wiring density of the first region is determined in accordance with the at least one of the clock wiring and a non-clock signal wiring.
Sharma teaches wherein the first region includes at least one of a clock wiring among the plurality of clock wirings and a non-clock signal wiring among the plurality of non-clock signal wirings, and the wiring density of the first region is determined in accordance with the at least one of the clock wiring and a non-clock signal wiring; Sharma [Column 4 Lines 30–55] and [Column 6 Lines 40–65] teach that clock tree components are high drive cells that switch every clock cycle, explicitly distinguishing clock network components from non-clock signal cells. Sharma's timing window analysis per region treats clock-driven cell switching separately from non-clock logic cell switching to determine decoupling capacitance needs per region, directly teaching that wiring density of a first region is determined in accordance with both clock wirings and non-clock signal wirings as distinct categories.
The motivation to combine Reith, Wang, OH, Haridass, and Sharma at the effective filing date of the invention is that Sharma explicitly distinguishes clock wirings from non-clock signal wirings when performing per-region decoupling capacitor analysis, which Haridass does not explicitly address. A person of ordinary skill in the art would have recognized that combining Haridass's wiring density analysis with Sharma's clock/non-clock distinction produces a more accurate target region selection method with a reasonable expectation of success.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) as applied to claim 1 respectively above, and in view of US20060190892A1 (Haridass) and further in view of US20130248957A1 (Kito).
In regards to claim 14 (Reith modified by Wang and OH) does not show the method of claim 13, wherein the setting of the target region on the partial sub-region of the first block includes at least one of: upon determining that the plurality of standard cells is not disposed in first sub-region, setting a first sub-region included in the first block as the target region; upon determining that a wiring density of a first sub-region included in the first block is less than a reference wiring density, setting the first sub-region as the target region; and upon determining that a width of wirings disposed in a first sub-region included in the first block is less than a reference width, setting the first sub-region as the target region;
Haridass teaches upon determining that a wiring density of a first sub-region included in the first block is less than a reference wiring density, setting the first sub-region as the target region; Haridass [0041] and [0048] teach that wiring geometry properties including line width and wiring density are analyzed per region of an integrated circuit to identify candidates for decoupling capacitor placement or modification. Applied to the sub-region context of Kito's block sub-region framework, this teaches setting the first sub-region as a target based on wiring density criteria.
Haridass teaches upon determining that a width of wirings disposed in a first sub-region included in the first block is less than a reference width, setting the first sub-region as the target region; Haridass [0041] teaches that wiring geometry information including line width is analyzed per region as a parameter that impacts wiring and propagation properties. Applied to the sub-region context of Kito's block sub-region framework, this teaches setting the first sub-region as a target based on wiring width criteria.
Haridass differs from the claimed invention in that it does not explicitly disclose upon determining that the plurality of standard cells is not disposed in first sub-region, setting a first sub-region included in the first block as the target region;
Kito teaches upon determining that the plurality of standard cells is not disposed in first sub-region, setting a first sub-region included in the first block as the target region; Kito [0072] and [0078] teach that the unused region 150 not occupied by a basic cell is extracted at Step S100 and designated as the target region for decoupling capacitor insertion. This directly teaches setting a first sub-region included in the first block as the target region upon determining that the plurality of standard cells are not disposed therein.
The motivation to combine Reith, Wang, OH, and Haridass at the effective filing date of the invention is that Haridass provides per-region wiring density and wiring width analysis to identify target sub-regions within blocks for decoupling capacitor modification, which Reith, Wang, and OH do not teach. A person of ordinary skill in the art would have recognized that applying Haridass's wiring property criteria within Kito's block sub-region framework produces a comprehensive target sub-region selection methodology with a reasonable expectation of success.
The motivation to combine Reith, Wang, OH, Haridass, and Kito at the effective filing date of the invention is that Kito provides the explicit framework for identifying unused sub-regions within blocks as target regions based on the absence of standard cells, which Haridass does not teach. A person of ordinary skill in the art would have recognized that combining Haridass's wiring property criteria with Kito's sub-region framework produces a complete and flexible target sub-region selection methodology with a reasonable expectation of success.
Claims 15 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) as applied to claim 1 respectively above, and further in view of US7600208B1 (Sharma).
In regards to claim 15 (Reith) shows the method of claim 1, wherein the obtaining of the first layout includes:
developing a power plan for the plurality of power wirings and the plurality of ground wirings; Reith [Column 3 Lines 55 - 65] teaches the closest power-supply nets get extracted by using another layout checking tool and all power-supplies and their combinations are sorted in a connection table for developing power plans.
Reith differs from the claimed invention in that it does not explicitly disclose developing a floor plan for the plurality of blocks, the plurality of standard cells, the plurality of decoupling capacitor cells and the plurality of filler cells; performing a placement of elements included in the plurality of blocks and the plurality of standard cells; performing a routing of non-clock signals provided to the elements via the plurality of non-clock signal wirings; performing a clock tree synthesis (CTS) of clock signals provided to the elements via the plurality of clock wirings;
Wang teaches developing a floor plan for the plurality of blocks, the plurality of standard cells, the plurality of decoupling capacitor cells and the plurality of filler cells; Wang [0038] teaches the candidate floor plan generating part 14 generates multiple candidate floor plans based on a net list, library information, floor plan information and technology information. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans.
Wang teaches performing a placement of elements included in the plurality of blocks and the plurality of standard cells; Wang [0044] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells based on the net list, library information, and floor plan information. Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths.
Wang teaches performing a routing of non-clock signals provided to the elements via the plurality of non-clock signal wirings; Wang [0074] teaches the processor executes an automatic P&R tool in which routing is performed to connect circuit elements, demonstrating routing of non-clock signals provided to the elements via the plurality of non-clock signal wirings.
Wang differs from the claimed invention in that it does not explicitly disclose performing a clock tree synthesis (CTS) of clock signals provided to the elements via the plurality of clock wirings;
Sharma teaches performing a clock tree synthesis (CTS) of clock signals provided to the elements via the plurality of clock wirings; Sharma [Column 6 Lines 40–65] teaches that the automatic decap cell placement process can be performed during clock tree synthesis, directly naming CTS as a specific phase of the ASIC design flow in which decoupling capacitor cells are also processed. Sharma [Column 4 Lines 30–55] further teaches that clock tree components are high drive cells and switch every clock cycle, confirming CTS as a distinct named step in the design flow that includes decoupling capacitor cell processing.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the floor plan, placement, and routing steps that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and Sharma at the effective filing date of the invention is that Sharma explicitly names clock tree synthesis as a distinct named step in the ASIC design flow in which decoupling capacitor cells are processed, which Wang does not teach. A person of ordinary skill in the art would have recognized that CTS is a standard step in any synchronous IC P&R flow and that Sharma's explicit teaching confirms its inclusion with a reasonable expectation of success.
In regards to claim 16 (Reith) does not show: verifying results of the placement and routing, wherein the setting of the target region on the first layout and the obtaining of the second layout are performed during the verifying results of the placement and routing;
OH teaches verifying results of the placement and routing, wherein the setting of the target region on the first layout and the obtaining of the second layout are performed during the verifying results of the placement and routing; OH [0061], [0063], and [0064] teach that after the fabricated IC is tested, it is determined whether an ECO event has occurred, constituting verification of placement and routing results. OH [0063] and [0064] teach that when the ECO event occurs during that verification phase, the preexisting decoupling capacitor cell in the target region is changed in place by forming an interconnection metal line pattern, converting it into a second cell structure different from the first without restarting the design flow, directly teaching that both the setting of the target region and the obtaining of the second layout are performed during the verifying results of the placement and routing.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is that OH teaches modifying a preexisting decoupling capacitor cell during the ECO and verification phase of the design flow, which Wang and Sharma do not teach. A person of ordinary skill in the art would have recognized that performing the target region setting and second layout modification during verification as taught by OH integrates naturally into the combined design flow with a reasonable expectation of success.
In regards to claim 17 (Reith) does not show the method of claim 16, wherein the verifying results of the placement and routing includes: performing a timing engineering change order (ECO) process; determining whether a timing condition has been satisfied;
OH teaches performing a timing engineering change order (ECO) process; OH [0055], [0058], [0061], and [0085] teach that the spare gate cell is formed for ECO purposes and after testing it is determined whether an ECO event or ECO issue has occurred. When a test result is determined to be a failure, the function or timing of fabricated functional cells may be changed or revised, constituting a timing ECO process. OH is entirely directed to ECO processes performed in the context of decoupling capacitor cells, directly teaching performing a timing engineering change order process.
OH teaches determining whether a timing condition has been satisfied; OH [0061] and [0085] teach that after the fabricated IC is tested it is determined whether an ECO event or ECO issue has occurred, and when the test result passes without an ECO event, the design is confirmed, constituting a determination of whether a timing condition has been satisfied. This directly teaches determining whether a timing condition has been satisfied following the timing ECO process.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is that OH teaches performing a timing ECO process and determining whether a timing condition has been satisfied in the context of decoupling capacitor cell modification, which Wang and Sharma do not teach. A person of ordinary skill in the art would have recognized that OH's timing ECO process and pass/fail determination integrate naturally into the combined verification flow with a reasonable expectation of success.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) as applied to claim 1 respectively above, and further in view of US20130248957A1 (Kito).
In regards to claim 18 (Reith) does not show: wherein upon determining the timing condition has been satisfied, the method further comprises: performing a physical design rule check and correction;
Kito teaches wherein upon determining the timing condition has been satisfied, the method further comprises: performing a physical design rule check and correction; Kito [0080], [0083], and [0085] teach that as part of the decoupling capacitor cell insertion process, the process checks whether wiring short is modified at Step S102, constituting a physical design rule check. If a wiring short is found, the short circuit is corrected at Step S105, constituting a physical design rule correction. This directly teaches performing a physical design rule check and correction following determination that the timing condition has been satisfied.
The motivation to combine Reith, Wang, OH, and Kito at the effective filing date of the invention is that Kito teaches performing a physical design rule check and correction as part of the decoupling capacitor cell insertion process, which Reith, Wang, and OH do not teach. A person of ordinary skill in the art would have recognized that a DRC check following decoupling capacitor cell modification is a standard and necessary step to ensure layout validity with a reasonable expectation of success.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US6353248B1 (Reith) and in view of US20080120582A1 (Wang) and in view of US20170069660A1 (OH) as applied to claim 1 respectively above, and in view of US20060190892A1 (Haridass) and further in view of US7600208B1 (Sharma).
In regards to claim 20 (Reith) shows a method of designing a layout of a semiconductor device, the method comprising:
developing a power plan for a plurality of power wirings and a plurality of ground wirings included in the semiconductor device; Reith [Column 3 Lines 55 - 65] teaches the closest power-supply nets get extracted by using another layout checking tool and all power-supplies and their combinations are sorted in a connection table for developing power plans.
setting a target region on the first layout, wherein the target region includes a first decoupling capacitor cell among the plurality of decoupling capacitor cells; Reith [Column 3 Lines 50 - 65] teaches when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool and then the closest power-supply nets get extracted by using another layout checking tool. Reith [Column 4 Lines 10 - 20] teaches the empty spaces are assigned the appropriate decoupling capacitances and in the spine area 55 of the DRAM chip there are many irregular empty spaces 81, 82, 83, 84, 85, 86 where different kinds of decoupling capacitors for different power supplies can be automatically generated.
the plurality of standard cells is not disposed in the target region; Reith [Column 3 Lines 50–65] and [Column 4 Lines 10–20] teach that all remaining empty space on the chip is identified by a layout tool and assigned appropriate decoupling capacitances, and that the irregular empty spaces 81–86 in the spine area of the DRAM chip are regions where different kinds of decoupling capacitors can be automatically generated. Because these target regions are defined as the remaining empty spaces on the chip after layout is complete, by definition the plurality of standard cells and functional circuit elements are not disposed in these regions, directly demonstrating that the target region does not contain the plurality of standard cells.
wherein the target region is a sub-region of the semiconductor device proximate to at least one of a corner of the semiconductor device and an edge portion of the semiconductor device; Reith [Column 2 Lines 55 - 65] teaches it is common to form dummy patterns around the edge of a semiconductor chip array to avoid problems associated with non-uniform patterns which form along the edges of an array where the present invention takes advantage of these unused portions of the chip by creating passive devices such as decoupling capacitors. Reith [Column 4 Lines 10 - 25] teaches in the spine area 55 of the DRAM chip there are many irregular empty spaces indicating regions near center portions and edges where decoupling capacitors can be formed.
arranging the second decoupling capacitor cell in the target region; Reith [Column 3 Lines 50 - 65] teaches when the chip layout is about to be finished all remaining empty space on the chip gets identified by a layout tool and then the empty spaces are assigned the appropriate decoupling capacitances where different kinds of decoupling capacitors for different power supplies can be automatically generated and arranged in target regions.
electrically connecting the second decoupling capacitor cell to a second power wiring and a second ground wiring external to the target region; Reith [Column 3 Lines 55 - 65] teaches the closest power-supply nets get extracted by using another layout checking tool and all power-supplies and their combinations are sorted in a connection table which determines the appropriate type of capacitances once the power-supply nets closest to the empty spaces are extracted from the layout where electrical connections are established between decoupling capacitors and external power supply networks.
Reith differs from the claimed invention in that it does not explicitly disclose receiving input data defining the semiconductor device; obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data, wherein the obtaining of the first layout of the semiconductor device includes: developing a floor plan for a plurality of blocks, a plurality of standard cells, a plurality of decoupling capacitor cells and a plurality of filler cells included in the semiconductor device; performing a placement of elements included in the plurality of blocks and the plurality of standard cells; performing a clock tree synthesis (CTS) for clock signals provided to the elements via a plurality of clock wirings included in the semiconductor device; performing a routing of non-clock signals provided to the elements via a plurality of non-clock signal wirings included in the semiconductor device; verifying results of the placement and routing; while verifying results of the placement and routing, obtaining a second layout of the semiconductor device by replacing the first decoupling capacitor cell in the target region with a second decoupling capacitor cell having a structure different from that of the first decoupling capacitor cell; the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes: removing at least one of a first power wiring and a first ground wiring from the first decoupling capacitor cell;
Wang teaches receiving input data defining the semiconductor device; Wang [0036] teaches net list is data describing connection information of semiconductor circuits formed on a semiconductor substrate and library information is circuit information of circuit components such as standard cells, macrocells and gates that can be placed in an placement region. Wang [0043] teaches the interface part 11 obtains a net list, library information, floor plan information and technology information as input data defining the semiconductor device.
Wang teaches obtaining a first layout of the semiconductor device by performing a placement and routing in response to the input data, wherein the obtaining of the first layout of the semiconductor device includes: Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where the purpose of the global placement is to determine the relative positions of blocks that result in short wiring lengths. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans in response to input data including net list, library information, and floor plan information.
Wang teaches developing a floor plan for a plurality of blocks, a plurality of standard cells, a plurality of decoupling capacitor cells and a plurality of filler cells included in the semiconductor device; Wang [0038] teaches the candidate floor plan generating part 14 generates multiple candidate floor plans based on a net list, library information, floor plan information and technology information. Wang [0075] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells on each of the created candidate floor plans, demonstrating the concept of developing floor plans that define various circuit elements.
Wang teaches performing a placement of elements included in the plurality of blocks and the plurality of standard cells; Wang [0044] teaches the cell initial placement part 13 performs an initial placement of standard cells and macrocells based on the net list, library information, and floor plan information. Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region.
Wang teaches performing a routing of non-clock signals provided to the elements via a plurality of non-clock signal wirings included in the semiconductor device; Wang [0074] teaches the processor 1 executes an automatic P & R tool to roughly place standard cells and macrocells in the placement region where routing is performed to connect circuit elements, demonstrating the concept of routing signals including non-clock signals to elements via wiring.
Wang teaches verifying results of the placement and routing; Wang [0078] teaches the verifying part 18 verifies the wiring and timing performance and if no problem is found as a result of the verification the floor plan is determined as final. Wang [0080] teaches if a problem with wiring and timing performance is found as a result of the verification, the process returns to step S24 and creation of candidate floor plans is performed again.
Wang differs from the claimed invention in that it does not explicitly disclose while verifying results of the placement and routing, obtaining a second layout of the semiconductor device by replacing the first decoupling capacitor cell in the target region with a second decoupling capacitor cell having a structure different from that of the first decoupling capacitor cell;
OH teaches while verifying results of the placement and routing, obtaining a second layout of the semiconductor device by replacing the first decoupling capacitor cell in the target region with a second decoupling capacitor cell having a structure different from that of the first decoupling capacitor cell; OH [0053], [0060], [0061], [0063], [0064], and [0085] teach that a spare gate cell is first formed in the type of a decoupling capacitor and exists in the layout as a preexisting decoupling capacitor cell having a first structure. OH [0061] teaches that after the fabricated IC is tested, it is determined whether an ECO event has occurred, constituting verification of placement and routing results. OH [0063] and [0064] teach that when the ECO event occurs during that verification phase, the preexisting decoupling capacitor cell is changed in place by forming an interconnection metal line pattern, converting it into a second cell structure different from the first without restarting the design flow. This directly teaches obtaining a second layout by replacing the first decoupling capacitor cell with a second decoupling capacitor cell having a different structure while verifying results of the placement and routing.
OH differs from the claimed invention in that it does not explicitly disclose the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes: removing at least one of a first power wiring and a first ground wiring from the first decoupling capacitor cell;
Haridass teaches the replacing of the first decoupling capacitor cell with the second decoupling capacitor cell includes: removing at least one of a first power wiring and a first ground wiring from the first decoupling capacitor cell; Haridass [0047] teaches that adding or removing decoupling capacitors may also require minor changes to the power wiring as well, directly teaching that replacing the first decoupling capacitor cell with a structurally different second decoupling capacitor cell requires removing at least one of a first power wiring and a first ground wiring from the first decoupling capacitor cell.
Haridass differs from the claimed invention in that it does not explicitly disclose performing a clock tree synthesis (CTS) for clock signals provided to the elements via a plurality of clock wirings included in the semiconductor device;
Sharma teaches performing a clock tree synthesis (CTS) for clock signals provided to the elements via a plurality of clock wirings included in the semiconductor device; Sharma [Column 6 Lines 40–65] teaches that the automatic decap cell placement process can be performed during clock tree synthesis, directly naming CTS as a specific phase of the ASIC design flow in which decoupling capacitor cells are also processed. Sharma [Column 4 Lines 30–55] further teaches that clock tree components are high drive cells and switch every clock cycle, confirming CTS as a distinct named step in the design flow that includes decoupling capacitor cell processing.
The motivation to combine Reith and Wang at the effective filing date of the invention is to create a complete semiconductor layout design flow by combining Reith's decoupling capacitor placement methodology with Wang's automated placement and routing system. A person of ordinary skill in the art would have recognized that Wang's P&R framework provides the input data, blocks, standard cells, and automated layout generation that Reith's decoupling capacitor methodology requires, with a reasonable expectation of success.
The motivation to combine Reith, Wang, and OH at the effective filing date of the invention is to enable modification of preexisting decoupling capacitor cells during the design process. A person of ordinary skill in the art would have recognized that OH's ECO-based cell modification technique directly improves upon the combined Reith/Wang design flow by allowing a preexisting decoupling capacitor cell to be replaced with a structurally different second cell during the verification phase, with a reasonable expectation of success.
The motivation to combine Reith, Wang, OH, and Haridass at the effective filing date of the invention is that Haridass teaches that removing a decoupling capacitor requires minor changes to associated power wiring, which OH does not explicitly address. A person of ordinary skill in the art would have recognized that incorporating Haridass's power wiring removal teaching produces a complete cell replacement process with a reasonable expectation of success.
The motivation to combine Reith, Wang, OH, Haridass, and Sharma at the effective filing date of the invention is that Sharma explicitly names clock tree synthesis as a distinct step in the design flow in which decoupling capacitor cells are processed, which the other references do not teach. A person of ordinary skill in the art would have recognized that CTS is a standard step in any synchronous IC design flow and that Sharma's explicit teaching confirms its inclusion with a reasonable expectation of success.
Response to Argument
Applicant's arguments filed March 25, 2026 have been considered but are not persuasive for the following reasons.
With respect to independent claim 1, Applicant argues that Reith does not disclose "obtaining a second layout of the semiconductor device by changing the first decoupling capacitor cell in the target region," contending that Reith teaches filling empty space with new decoupling capacitors rather than changing a preexisting decoupling capacitor cell. This argument is acknowledged as to Reith alone and the rejection has been updated accordingly. The rejection now relies on OH for this limitation. OH [0053] explicitly teaches that a spare gate cell is first formed in the type of a decoupling capacitor and exists in the layout as a preexisting decoupling capacitor cell. OH [0061], [0063], and [0064] further teach that when an ECO event occurs after testing, the preexisting decoupling capacitor cell is changed in place by forming an interconnection metal line pattern, producing a modified second layout. This directly and explicitly teaches obtaining a second layout by changing a preexisting first decoupling capacitor cell in the target region. Applicant's argument is therefore not persuasive against the updated rejection.
With respect to independent claim 2, Applicant argues that Wang is silent on decoupling capacitors and cannot teach replacing a first decoupling capacitor cell having a first structure with a second decoupling capacitor cell having a second structure different from the first. This argument is acknowledged as to Wang and the rejection has been updated accordingly. The rejection now relies on OH for this limitation. OH [0060], [0063]–[0064], [0071]–[0072], and [0085] explicitly teach that a spare gate cell formed in the type of a decoupling capacitor having a first structure — source and drain connected MOS transistors configured as a capacitor — is changed into an ECO cell having a second structure — an inverter or NAND gate circuit — that is explicitly and structurally different from the first. FIGS. 4/6 of OH show the first decoupling capacitor structure and FIGS. 5/7 show the resulting second structure. Applicant's argument that Wang is silent on decoupling capacitors is therefore not persuasive against the updated rejection.
With respect to independent claim 19, Applicant's argument mirrors that of claim 1 and fails for the same reasons. OH explicitly teaches the design module of the combined system obtaining a second layout by changing a preexisting first decoupling capacitor cell in the target region, as discussed above with respect to claim 1.
With respect to independent claim 20, Applicant's argument mirrors that of claims 1 and 2 and fails for the same reasons. OH explicitly teaches that the preexisting decoupling capacitor cell is changed in place during the verification phase, directly teaching the "while verifying results of the placement and routing" temporal limitation that Wang was previously relied upon for. Applicant's argument that Wang is silent on decoupling capacitors is not persuasive against the updated rejection which no longer relies on Wang for this limitation.
With respect to dependent claims 3–18, these claims remain unpatentable for the same reasons as their respective independent claims from which they depend, as the updated rejections address each limitation with direct and explicit teachings from the cited references.
Conclusion
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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