DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 08/25/2022 and 02/19/2025 for application number 17/895,250. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/declaration, 2 IDS, and Claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on November 16,2021. It is noted, however, that applicant has not filed a certified copy of the JP 2021-186554 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/25/2022 and 02/19/2025 are being considered by the examiner. However, the IDS submitted on 02/19/2025 with respect to WO2020/202312 has the incorrect publication date of 11/18/2021. Examiner has considered what they believed the applicant intended to submit as a reference for the IDS, but not what was given in the IDS. See PTO-892 and relevant documents for the correct date of 10/08/2020.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following limitations of “a cloud” in claim 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 3, 5-6, 8-11, and 13-15 objected under 37 CFR 1.71(a) to because of the following informalities:
In claim 1, ll.6, “the i-th variable pair” should read as “a i-th variable pair”.
In claim 1, ll.6, “the first variable group” should read as “a first variable group”.
In claim 1, ll.6, “the second variable group” should read as “a second variable group”.
In claim 3, p.39, ll.7-8, “the vector h” should read as “a vector h”.
In claim 3, p.39, ll.8, “the bias of the variable” should read as “a bias of the variable”.
In claim 3, p.39, ll.9, “the temperature signal ST” should read as “a temperature signal ST”.
In claim 3, p.39, ll.9-10, “the temperature parameter T” should read as “a temperature parameter T”.
In claim 5, ll.2, “the hot bath method” should read as “a hot bath method”.
In claim 5, ll.2-3, “the metropolis method” should read as “a metropolis method”.
In claim 6, ll.1-2, “the ground state” should read as “a ground state”
In claim 6, ll.4, “the complete bipartite graph” should read as “a complete bipartite graph”
In claim 6, ll.8-9, “the first variable group” should read as “a first variable group”.
In claim 6, ll.9, “the second variable group” should read as “a second variable group”.
In claim 6, ll.9. “coupling λ" should read as “a coupling λ".
In claim 6, ll.10-11, “the i-th variable pair” should read as “a i-th variable pair”.
In claim 6, ll.13-14, “the bias coefficient h” should read as “a bias coefficient h”.
In claim 6, ll.14, “the bias acting” should read as “a bias acting”.
In claim 8, ll.5, “the product-sum operation” should read as “a product-sum operation”.
In claim 9, ll.4, “the update destination” should read as “a update destination”.
In claim 10, ll.8, “the output value” should read as “an output value”.
In claim 10, ll.11, “an output value” should read as “the output value”.
In claim 11, ll.1-2, “the ground state” should read as “a ground state”
In claim 11, ll.3, “the user” should read as “a user”
In claim 11, ll.6, “the complete bipartite graph” should read as “a complete bipartite graph”
In claim 11, ll.11-12, “the first variable group” should read as “a first variable group”.
In claim 11, ll.12, “the second variable group” should read as “a second variable group”.
In claim 11, ll.12, “coupling λ" should read as “a coupling λ".
In claim 11, p.43, ll.1-2, “the i-th variable pair” should read as “a i-th variable pair”.
In claim 11, p.43, ll.4-5, “the bias coefficient h” should read as “a bias coefficient h”.
In claim 11, p.43, ll.5, “the bias acting” should read as “a bias acting”.
In claim 13, ll.4, “the update destination” should read as “a update destination”.
In claim 14, ll.8, “the output value” should read as “an output value”.
In claim 14, ll.11, “an output value” should read as “the output value”.
In claim 15, p.45, ll.1, “the problem” should read as “a problem”
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“arithmetic unit” in at least claims 6 and 11 is interpreted with respect to at least par.51 and 91 for the various hardware/software embodiments.
“product-sum arithmetic unit” in at least claim 8 is interpreted with respect to at least par. 61-62, and 87-88.
“comparison arithmetic unit” in at least claims 9 and 13 is interpreted with respect to at least par. 63, and 88.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 11 recites the limitation "the variable" in the corresponding limitation of “…a bias coefficient memory that stores the bias coefficient h indicating the bias acting on the variable…”. There is insufficient antecedent basis for this limitation in the claim. The claim recites “variables”, “variable group”, “first [and second] variable group”, and “i-th variable pair” prior to the limitation in question. This is unclear to which “variable” that “the variable” in question references, and if “the variable” is specific to a singular variable or a non-singular variable. For purposes of examination, “the variable” will be considered “the variables” in reference to “variables”.
Claim 15 recites the limitation "the data". There is insufficient antecedent basis for this limitation in the claim. There are no instances of “data” and it is unclear to which data is in question in the parent claims, such as “information by [a] user”, “variables”, “ground state”, “interaction matrix”, and/or “coupling”, or if “data” should be a new limitation as “an data” instead of “the data”.
Claim 8 limitation "a product-sum arithmetic unit" invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. In the specification, there is no disclosure of adequate structure to perform the claimed function. In particular, the specification states that the product-sum arithmetic unit performs the claimed function of product-sum. However, there is no disclosure of any particular structure, either explicitly or inherently, to perform the product-sum. The use of the term “product-sum arithmetic unit” are not adequate structure for performing the comparison because it does not describe a particular structure for performing the function. As would be recognized by those of ordinary skill in the art, the term “product-sum arithmetic unit” refers to any kind of structure to do product-sum and can be performed in any number of ways in hardware, software or a combination of the two. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which product-sum arithmetic unit structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claims 9, 10, 13 and 14 limitation of "a comparison arithmetic unit" invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. In the specification, there is no disclosure of adequate structure to perform the claimed function. In particular, the specification states that the comparison arithmetic unit performs the claimed function of the mathematical function. However, there is no disclosure of any particular structure, either explicitly or inherently, to perform the mathematical function. The use of the term “comparison arithmetic unit” are not adequate structure for performing the mathematical function because it does not describe a particular structure for performing the function. As would be recognized by those of ordinary skill in the art, the term “comparison arithmetic unit” refers to any kind of structure to do mathematical functions and can be performed in any number of ways in hardware, software or a combination of the two. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which comparison arithmetic unit structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-10 and 13-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure to perform the claimed functions of product-sum and mathematical functions given the claimed units. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 6-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims does not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “arithmetic unit” encompasses software per se. See par. 91 of the specification. A claim whose BRI covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter. See MPEP 2106.03(II). Accordingly, Claims 6-15 fails to recite statutory subject matter under 35 U.S.C. 101. For purposes of examination, Claims 6-15 arithmetic unit will be considered to exclude all software per se.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-5 recite a method and, therefore, is a process. Claims 6-10 recites a device and, therefore, is a machine. Claims 11-15 recites a system and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 1 recites
An optimization method using an information processing device that executes a ground state search, comprising:
converting a binary quadratic model with constraints into a complete bipartite graph that has an interaction relationship and a coupling that makes the same values in the ground state between the i-th variable pair of the first variable group and the second variable group, in each variable group, dividing the variables into groups that can be updated under satisfying the constraints, and performing state updates for each group in parallel.
The above underlined limitations are related to converting one mathematical model into another mathematical model and executing the ground state search which amount to mathematical calculations and relationships that falls under “mathematical concepts” of abstract ideas (see at least specification paragraphs 2-3, 8, 10, 31-36, and 39-48). The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claims 2-5 recite further steps and details to executing the ground state search which amount to mathematical calculations and relationships that falls under “mathematical concepts” of abstract ideas.
Claim 2, is directed to memories and supply lines to store and apply the abstract idea. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “information processing device“, “a first variable memory that stores the value of the 0/1 variable of the first variable group, a second variable memory that stores the value of the 0/1 variable of the second variable group”, and “a signal SW supply line”. However, the additional elements of “information processing device”, “a first variable memory”, “a second variable memory”, and “a signal SW supply line” are recited at a high-level of generality (i.e., as a generic computer component for executing the math; as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. storing variables of the first/second variable groups, and reading from the memories) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “information processing device”, “a first variable memory”, “a second variable memory”, and “a signal SW supply line” are recited at a high-level of generality (i.e., as a generic computer component for executing the math; as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of storing/retrieving data are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 3 is directed to searching for the ground state by performing simulated annealing. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “an interaction coefficient memory that stores an interaction matrix J”, “a bias coefficient memory that stores the vector h”, “a signal ST supply line that supplies the temperature signal ST”, and “a signal SR supply line that supplies a random number signal SR”. However, the additional elements of “an interaction coefficient memory”, “a bias coefficient memory”, “a signal ST supply line”, and “a signal SR supply line” are recited at a high-level of generality (i.e., as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. storing interaction matrix J, storing vector h, and reading from the memories) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “an interaction coefficient memory”, “a bias coefficient memory”, “a signal ST supply line”, and “a signal SR supply line” are recited at a high-level of generality (i.e., as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of storing/retrieving data are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 4 is directed to the relationship and/or calculation of the matrix and the coupling strength. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claim recites an abstract idea.
Claim 5 is directed to executing the hot bath or metropolis method for updating. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claim 6 recites
An information processing device that searches the ground state, comprising:
an arithmetic unit that updates variables in a variable group of the complete bipartite graph with constraints, and
the arithmetic unit includes
an interaction coefficient memory that stores interaction matrix J, which summarizes the interaction coefficients showing the interactions acting between the first variable group and the second variable group, and coupling
λ
that makes the same values in the ground state between the i-th variable pair of the first variable group and the second variable group,
a bias coefficient memory that stores the bias coefficient h indicating the bias acting on the variable,
a first variable memory that stores the variables of the first variable group,
a second variable memory that stores the variables of the second variable group, and
a signal SW supply line that supplies a selection signal SW for selecting the first variable group or the second variable group,
the arithmetic unit, when the selection signal SW selects the d-th variable group (d = 1, 2), calculates the next state for each group of variables summarized by the constraints, the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of the coupling
λ
, and the value of the bias coefficient h are used as inputs.
The above underlined limitations are related to executing the ground state search which amount to mathematical calculations and relationships that falls under “mathematical concepts” of abstract ideas (see at least specification paragraphs 16-28, 32-48, and 52-64). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “an arithmetic unit“, “an interaction coefficient memory that stores an interaction matrix J”, “a bias coefficient memory that stores the vector h”, “a first variable memory that stores the variables of the first variable group, a second variable memory that stores the variables of the second variable group”, “a signal SW supply line that supplies a selection signal SW”, and “read from the memory storing the corresponding variable group”. However, the additional elements of “an arithmetic unit”, “an interaction coefficient memory”, “a bias coefficient memory”, “a first/second variable memory”, and “a signal SW supply line” are recited at a high-level of generality (i.e., as a generic computer component for performing the math; as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. interaction matrix J, vector h, variables of the first/second variable groups, and reading from the memories) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “an arithmetic unit”, “an interaction coefficient memory”, “a bias coefficient memory”, “a first/second variable memory”, and “a signal SW supply line” are recited at a high-level of generality (i.e., as a generic computer component for performing the math; as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. interaction matrix J, vector h, variables of the first/second variable groups, and reading from the memories) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claims 7-10 recite further steps and details to executing the ground state search which amount to mathematical calculations and relationships that falls under “mathematical concepts” of abstract ideas
Claim 7 is merely directed to multiple units to execute the updates. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a unit” and “the first variable memory and the second variable memory store a group of variables summarized by constraints.”. However, the additional elements of “a unit” and “the first/second memory” are recited at a high-level of generality (i.e., as a generic computer component to execute the math; and as a generic memory for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. store a group of variables summarized by constraints) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a unit” and “the first/second memory” are recited at a high-level of generality (i.e., as a generic computer component to execute the math; and as a generic memory for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. store a group of variables summarized by constraints) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 8 is merely directed to a product-sum arithmetic unit that executes a product-sum operation. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a product-sum arithmetic unit”. However, the additional elements of “a product-sum arithmetic unit” are recited at a high-level of generality (i.e., as a generic computer component to execute the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a product-sum arithmetic unit” are recited at a high-level of generality (i.e., as a generic computer component to execute the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 9 is merely directed to a comparison arithmetic unit that executes a probabilistic update. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a comparison arithmetic unit”. However, the additional elements of “a comparison arithmetic unit” are recited at a high-level of generality (i.e., as a generic computer component to execute the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a comparison arithmetic unit” are recited at a high-level of generality (i.e., as a generic computer component to execute the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 10 is merely directed to including supply lines for the inputs required by the math for simulated annealing. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a signal ST supply line for supplying a temperature signal ST”, and “a signal SR supply line for supplying a random number signal”. However, the additional elements of “a signal ST supply line” and “a signal SR supply line” are recited at a high-level of generality (i.e., as a generic data lines to supply the data for the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a signal ST supply line” and “a signal SR supply line” are recited at a high-level of generality (i.e., as a generic data lines to supply the data for the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claim 6 recites
An information processing system that searches the ground state, comprising:
a user terminal used for inputting information by the user, and
an arithmetic unit that updates variables in a variable group of the complete bipartite graph with constraints, and is placed on a cloud different from the user terminal, the arithmetic unit includes an interaction coefficient memory that stores interaction matrix J, which summarizes the interaction coefficients showing the interactions acting between the first variable group and the second variable group, and coupling
λ
that makes the same values in the ground state between the i-th variable pair of the first variable group and the second variable group,
a bias coefficient memory that stores the bias coefficient h indicating the bias acting on the variable,
a first variable memory that stores the variables of the first variable group,
a second variable memory that stores the variables of the second variable group, and
a signal SW supply line that supplies a selection signal SW for selecting the first variable group or the second variable group,
the arithmetic unit, when the selection signal SW selects the d-th variable group (d = 1, 2), calculates the next state for each group of variables summarized by the constraints, the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of the coupling
λ
, and the value of the bias coefficient h are used as inputs.
The above underlined limitations are related to executing the ground state search which amount to mathematical calculations and relationships that falls under “mathematical concepts” of abstract ideas (see at least specification paragraphs 16-28, 32-48, and 52-64) and mental steps. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a user terminal“, “an arithmetic unit“, “a cloud”, “an interaction coefficient memory that stores an interaction matrix J”, “a bias coefficient memory that stores the vector h”, “a first variable memory that stores the variables of the first variable group, a second variable memory that stores the variables of the second variable group”, “a signal SW supply line that supplies a selection signal SW”, and “read from the memory storing the corresponding variable group”. However, the additional elements of “a user terminal”, “an arithmetic unit”, “a cloud”, “an interaction coefficient memory”, “a bias coefficient memory”, “a first/second variable memory”, and “a signal SW supply line” are recited at a high-level of generality (i.e., as a generic computer component for receiving the data; as a generic computer component for performing the math; as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. inputting information, storing interaction matrix J, storing vector h, storing variables of the first/second variable groups, and reading from the memories) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a user terminal”, “an arithmetic unit”, “a cloud”, “an interaction coefficient memory”, “a bias coefficient memory”, “a first/second variable memory”, and “a signal SW supply line” are recited at a high-level of generality (i.e., as a generic computer component for receiving the data; as a generic computer component for performing the math; as a generic memories for storing data; and as a generic data line for supplying the data required by the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” and “Receiving or transmitting data over a network” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claims 11-15 recite further steps and details to executing the ground state search which amount to mathematical calculations and relationships that falls under “mathematical concepts” and/or “mental steps” of abstract ideas.
Claim 12 is merely directed to multiple units to execute the updates. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a unit” and “the first variable memory and the second variable memory store a group of variables summarized by constraints.”. However, the additional elements of “a unit” and “the first/second memory” are recited at a high-level of generality (i.e., as a generic computer component to execute the math; and as a generic memory for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. store a group of variables summarized by constraints) are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a unit” and “the first/second memory” are recited at a high-level of generality (i.e., as a generic computer component to execute the math; and as a generic memory for storing data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. At most, the additional elements of storing/retrieving data (i.e. store a group of variables summarized by constraints) are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 13 is merely directed to a comparison arithmetic unit that executes a probabilistic update. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a comparison arithmetic unit”. However, the additional elements of “a comparison arithmetic unit” are recited at a high-level of generality (i.e., as a generic computer component to execute the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a comparison arithmetic unit” are recited at a high-level of generality (i.e., as a generic computer component to execute the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 14 is merely directed to including supply lines for the inputs required by the math for simulated annealing. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “a signal ST supply line for supplying a temperature signal ST”, and “a signal SR supply line for supplying a random number signal”. However, the additional elements of “a signal ST supply line” and “a signal SR supply line” are recited at a high-level of generality (i.e., as a generic data lines to supply the data for the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a signal ST supply line” and “a signal SR supply line” are recited at a high-level of generality (i.e., as a generic data lines to supply the data for the math) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 15 is directed to the user for the ground state search. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, The claim recites the following additional elements: “the user can set the data related to the problem to be solved via the user terminal”. However, the additional elements of the user can set the data related to the problem to be solved via the user terminal is merely adding insignificant extra-solution activities. Additionally, the additional elements of the user can set the data related to the problem to be solved via the user terminal is merely generally linking the use of a judicial exception to a particular technological environment or field of use of limiting to a particular data source. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the user can set the data related to the problem to be solved via the user terminal is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” and “Receiving or transmitting data over a network” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Stallings (NPL: “Computer Organization and Architecture”) at least Chapter 8 abstract, and 8.1 that discloses I/O interfaces/modules, control signals and user input. Additionally, the additional elements of the user can set the data related to the problem to be solved via the user terminal is merely generally linking the use of a judicial exception to a particular technological environment or field of use of limiting to a particular data source. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okuyama et al. (WO 2020/202312 A1) using the corresponding US publication 2022/0129780 A1 (From IDS filed 02/19/2025) as the English translation, hereinafter Okuyama.
Regarding claim 1, Okuyama discloses:
An optimization method using an information processing device that executes a ground state search, comprising:
converting a binary quadratic model with constraints into a complete bipartite graph that has an interaction relationship ["a ground state is obtained by a method of representing (simulating) an interaction relation of an Ising model as a complete bipartite graph", par.31; Fig.6 and par.65, model conversion unit 611] and
a coupling that makes the same values in the ground state between the i-th variable pair of the first variable group and the second variable group, in each variable group, dividing the variables into groups that can be updated under satisfying the constraints ["the interaction wi … the value of the i-th spin of the first spin group and the value of the i-th spin of the second spin group are the same value…
λ
is a minimum eigenvalue of the matrix J. Also herein,
λ
may be a maximum eigenvalue of -J" par.33-36, see equation 4], and
performing state updates for each group in parallel ["the values of the spins of each group can be updated at the same time" par.38 ].
Regarding claim 2, Okuyama disclose the invention substantially as claimed. See the discussion of claim 1 above.
Okuyama discloses:
wherein the information processing device includes a first variable memory that stores the value of the 0/1 variable of the first variable group, a second variable memory that stores the value of the 0/1 variable of the second variable group [“a spin state that takes a binary value of +1/-1 (which may be "0/1", "up/down", or the like)” par.21; Fig.5, Spin memory 1 (513a) and Spin memory 2 (513b)], and
a signal SW supply line that supplies a selection signal SW that selects one of the variable groups when updating the value ["The signal EN is a signal that periodically repeats the values of H (high) and L (low). When… EN is H… outputs the value of first spin memory… when… EN is L… outputs the value of the second spin memory " par.56], and
updates the state of the variable of the memory selected by the selection signal SW according to an update method that satisfies the constraint imposed on the variable [“The signal SP output from the comparator … When the signal EN is H (High), the information of the signal SP is written in the first spin memory 513a, and when the signal EN is L (Low), the information of the signal SP is written in the second spin memory 513b.” par.63].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 8-9, 11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Okuyama, and in view of Patterson et al. (NPL: “Computer Organization and Design MIPS Edition: The Hardware/Software Interface (5th ed.)”), hereinafter Patterson.
Regarding claim 6, Okuyama discloses:
An information processing device that searches the ground state, comprising:
an arithmetic unit that updates variables in a variable group of the complete bipartite graph with constraints [Fig. 5, 500; Fig.4, Arithmetic Device 20; “the spin array of each column in the ground state of the model represented by the complete bipartite graph” par.38], and
the arithmetic unit includes an interaction coefficient memory that stores interaction matrix J, which summarizes the interaction coefficients showing the interactions acting between the first variable group and the second variable group ["the arithmetic circuit 500 includes an interaction coefficient memory 511" par.52; "Information indicating the matrix J… is stored in the interaction coefficient memory 511" par.53; Jij, par.22-24; the interactions Jij act between the i-th spin of the left column spin group (... first spin group) and the j-th spin of the right column spin group (... second spin group)" par.32],
A coupling
λ
that makes the same values in the ground state between the i-th variable pair of the first variable group and the second variable group ["the interaction wi … the value of the i-th spin of the first spin group and the value of the i-th spin of the second spin group are the same value…" par.33-36, see equation 4],
a bias coefficient memory that stores the bias coefficient h indicating the bias acting on the variable ["Information indicating the vector h is stored in the external magnetic field coefficient memory 512." par.53; "the vector h representing the external magnetic field coefficient in the external magnetic field coefficient memory 512 for the interaction relationship of the Ising model based on the Ising format problem data 602." par.67],
a first variable memory that stores the variables of the first variable group, a second variable memory that stores the variables of the second variable group ["The first spin memory 513a stores information of an N-dimensional vector indicating the spin states of the first spin group of the complete bipartite graph described above. The second spin memory 513b stores information of an N-dimensional vector indicating the spin states of the second spin group of the complete bipartite graph" par.54], and
a signal SW supply line that supplies a selection signal SW for selecting the first variable group or the second variable group ["The signal EN is a signal that periodically repeats the values of H (high) and L (low). When… EN is H… outputs the value of first spin memory… when… EN is L… outputs the value of the second spin memory " par.56],,
the arithmetic unit, when the selection signal SW selects the d-th variable group (d = 1, 2), calculates the next state for each group of variables summarized by the constraints [“The signal SP output from the comparator … When the signal EN is H (High), the information of the signal SP is written in the first spin memory 513a, and when the signal EN is L (Low), the information of the signal SP is written in the second spin memory 513b.” par.63],
the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of SW related to the coupling
λ
, and the value of the bias coefficient h are used as inputs [Fig.5].
Okuyama does not explicitly disclose the arithmetic unit includes an interaction coefficient memory that stores interaction matrix J and Coupling
λ
; the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of the coupling A, and the value of the bias coefficient h are used as inputs.
Okuyama discloses power iteration using the Product-sum arithmetic device that requires both the interaction matrix J and the Eigenvalue [“The maximum eigenvalue of the matrix J is required for the calculation of Formula 4, and the maximum eigenvalue attached with origin shift can be efficiently calculated by a commonly known algorithm called a power iteration method. This is to repeatedly execute a matrix-vector product, and the product-sum arithmetic device 515 can be utilized” par.59],
In the analogous art of computer architecture, Patterson teaches using the memory closest for reusing recently accessed data [“Memory hierarchies take advantage of temporal locality by keeping more recently accessed data items closer to the processor” p.377].
It would have been obvious to one of ordinary skill in the art, having the teachings of Okuyama and Patterson before him before the effective filing date of the claimed invention to modify the interaction coefficient memory disclosed by Okuyama, to reuse the memory for the recently accessed data required for the device as taught by Patterson, in order to utilize Temporal locality and Spatial locality for improved processing time [Patterson: Sec.5.1]. The combination of Okuyama and Patterson discloses an interaction coefficient memory that stores interaction matrix J and Coupling
λ
; the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of the coupling A, and the value of the bias coefficient h are used as inputs.
Regarding claim 8, Okuyama and Patterson disclose the invention substantially as claimed. See the discussion of claim 6 above.
Okuyama discloses wherein the arithmetic unit includes a product-sum arithmetic unit that executes the calculation of the next state based on the product-sum operation ["The N-dimensional vector output from the product-sum arithmetic device 515 and the N-dimensional vector output from the vector multiplier 516 are input to the comparator 518" par.62; "The signal SP output from the comparator 518 is the next state of spin based on the MCMC described above" par.63].
Regarding claim 9, Okuyama and Patterson disclose the invention substantially as claimed. See the discussion of claim 6 above.
Okuyama discloses wherein the arithmetic unit includes a comparison arithmetic unit that operates the next state of the update destination by executing a probabilistic update ["The signal SP output from the comparator … When the signal EN is H (High), the information of the signal SP is written in the first spin memory 513a, and when the signal EN is L (Low), the information of the signal SP is written in the second spin memory 513b" par.63].
Regarding claim 11, Okuyama discloses:
An information processing system that searches the ground state, comprising:
A user terminal used for inputting information by the user ["The input device 14 is a user interface that receives an input of information from a user" par.49], and
an arithmetic unit that updates variables in a variable group of the complete bipartite graph with constraints [Fig. 5, 500; Fig.4, Arithmetic Device 20; “the spin array of each column in the ground state of the model represented by the complete bipartite graph” par.38], and
is placed on a cloud different from the user terminal ["the information processing device 10 may be realized using virtual information processing resources, such as a cloud server, which are partially or entirely provided by a cloud system" par.47]
the arithmetic unit includes an interaction coefficient memory that stores interaction matrix J, which summarizes the interaction coefficients showing the interactions acting between the first variable group and the second variable group ["the arithmetic circuit 500 includes an interaction coefficient memory 511" par.52; "Information indicating the matrix J… is stored in the interaction coefficient memory 511" par.53; Jij, par.22-24; the interactions Jij act between the i-th spin of the left column spin group (... first spin group) and the j-th spin of the right column spin group (... second spin group)" par.32],
A coupling
λ
that makes the same values in the ground state between the i-th variable pair of the first variable group and the second variable group ["the interaction wi … the value of the i-th spin of the first spin group and the value of the i-th spin of the second spin group are the same value…" par.33-36, see equation 4],
a bias coefficient memory that stores the bias coefficient h indicating the bias acting on the variable ["Information indicating the vector h is stored in the external magnetic field coefficient memory 512." par.53; "the vector h representing the external magnetic field coefficient in the external magnetic field coefficient memory 512 for the interaction relationship of the Ising model based on the Ising format problem data 602." par.67],
a first variable memory that stores the variables of the first variable group, a second variable memory that stores the variables of the second variable group ["The first spin memory 513a stores information of an N-dimensional vector indicating the spin states of the first spin group of the complete bipartite graph described above. The second spin memory 513b stores information of an N-dimensional vector indicating the spin states of the second spin group of the complete bipartite graph" par.54], and
a signal SW supply line that supplies a selection signal SW for selecting the first variable group or the second variable group ["The signal EN is a signal that periodically repeats the values of H (high) and L (low). When… EN is H… outputs the value of first spin memory… when… EN is L… outputs the value of the second spin memory " par.56],,
the arithmetic unit, when the selection signal SW selects the d-th variable group (d = 1, 2), calculates the next state for each group of variables summarized by the constraints [“The signal SP output from the comparator … When the signal EN is H (High), the information of the signal SP is written in the first spin memory 513a, and when the signal EN is L (Low), the information of the signal SP is written in the second spin memory 513b.” par.63],
the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of SW related to the coupling
λ
, and the value of the bias coefficient h are used as inputs [Fig.5].
Okuyama does not explicitly disclose the arithmetic unit includes an interaction coefficient memory that stores interaction matrix J and Coupling
λ
; the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of the coupling A, and the value of the bias coefficient h are used as inputs.
Okuyama discloses power iteration using the Product-sum arithmetic device that requires both the interaction matrix J and the Eigenvalue [“The maximum eigenvalue of the matrix J is required for the calculation of Formula 4, and the maximum eigenvalue attached with origin shift can be efficiently calculated by a commonly known algorithm called a power iteration method. This is to repeatedly execute a matrix-vector product, and the product-sum arithmetic device 515 can be utilized” par.59],
In the analogous art of computer architecture, Patterson teaches using the memory closest for reusing recently accessed data [“Memory hierarchies take advantage of temporal locality by keeping more recently accessed data items closer to the processor” p.377].
It would have been obvious to one of ordinary skill in the art, having the teachings of Okuyama and Patterson before him before the effective filing date of the claimed invention to modify the interaction coefficient memory disclosed by Okuyama, to reuse the memory for the recently accessed data required for the device as taught by Patterson, in order to utilize Temporal locality and Spatial locality for improved processing time [Patterson: Sec.5.1]. The combination of Okuyama and Patterson discloses an interaction coefficient memory that stores interaction matrix J and Coupling
λ
; the value of the variable read from the memory storing the corresponding variable group, the value of the interaction coefficient in the interaction matrix J corresponding to the variable, the value of the coupling A, and the value of the bias coefficient h are used as inputs.
Regarding Claim 13, it is directed to claim 9. The claim is rejected for the reasons given above.
Regarding claim 15, Okuyama and Patterson disclose the invention substantially as claimed. See the discussion of claim 11 above.
Okuyama discloses wherein the user can set the data related to the problem to be solved via the user terminal ["The problem data 601 is set by the user, for example, via the user interface" par.65].
Claims 3-5, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Okuyama, and in view of Patterson, and further in view of Hayashi et al. (NPL: “An Ising Computer based on simulated quantum annealing by path integral Monte Carlo method”), hereinafter Hayashi.
Regarding claim 3, Okuyama disclose the invention substantially as claimed. See the discussion of claim 2 above.
Okuyama discloses:
wherein the information processing device searches for the ground state by performing an operation based on simulated annealing [“a method for obtaining an optimum solution or an approximate solution of a minimization problem by utilizing this, there is simulated annealing” par.29-31],
the information processing device includes an interaction coefficient memory that stores an interaction matrix J that defines the interaction relationship of the binary quadratic model ["the arithmetic circuit 500 includes an interaction coefficient memory 511" par.52; "Information indicating the matrix J… is stored in the interaction coefficient memory 511" par.53; Jij, par.22-24; the interactions Jij act between the i-th spin of the left column spin group (... first spin group) and the j-th spin of the right column spin group (... second spin group)" par.32],
a coupling strength
λ
that is a value related to the coupling [“The maximum eigenvalue of the matrix J is required for the calculation of Formula 4, and the maximum eigenvalue attached with origin shift can be efficiently calculated by a commonly known algorithm called a power iteration method. This is to repeatedly execute a matrix-vector product, and the product-sum arithmetic device 515 can be utilized” par.59, this discloses the calculation of the eigenvalue using product-sum arithmetic device 515],
a bias coefficient memory that stores the vector h related to the bias of the variable ["Information indicating the vector h is stored in the external magnetic field coefficient memory 512." par.53; "the vector h representing the external magnetic field coefficient in the external magnetic field coefficient memory 512 for the interaction relationship of the Ising model based on the Ising format problem data 602." par.67],
a signal SR supply line that supplies a random number with related to the temperature parameter T and a uniform random number from 0 to 1 [“The signal SR represents an N-dimensional vector in which each element is a random number independent of each other. In this example, each element is the product of the temperature T and the random number -ln(u)/2. However, u is a uniform random number (0<u<=1)” par.60],
calculates the next state based on the interaction matrix J, the coupling strength
λ
, the vector h, the temperature, and the random number [Figure 5, SP signal – next state, interaction coefficient memory – matrix J, Signal SW – formula 4 includes coupling strength
λ
,
Signal SR – temperature T and random number u].
However, Okuyama does not explicitly disclose:
an interaction coefficient memory that stores an interaction matrix J that defines the interaction relationship of the binary quadratic model, and a coupling strength A that is a value related to the coupling,
a signal ST supply line that supplies the temperature signal ST related to the temperature parameter T, and a signal SR supply line that supplies a random number signal SR that gives a uniform random number from 0 to 1.
calculates the next state based on the interaction matrix J, the coupling strength
λ
, the vector h, the temperature signal ST, and the random number signal SR
Okuyama discloses power iteration using the Product-sum device that requires both the interaction matrix J and the Eigenvalue [“The maximum eigenvalue of the matrix J is required for the calculation of Formula 4, and the maximum eigenvalue attached with origin shift can be efficiently calculated by a commonly known algorithm called a power iteration method. This is to repeatedly execute a matrix-vector product, and the product-sum arithmetic device 515 can be utilized” par.59],
In the analogous art of computer architecture, Patterson teaches using the memory closest for reusing recently accessed data [“Memory hierarchies take advantage of temporal locality by keeping more recently accessed data items closer to the processor” p.377].
It would have been obvious to one of ordinary skill in the art, having the teachings of Okuyama and Patterson before him before the effective filing date of the claimed invention to modify the interaction coefficient memory disclosed by Okuyama, to reuse the memory for the recently accessed data required for the device as taught by Patterson, in order to utilize Temporal locality and Spatial locality for improved processing time [Patterson: Sec.5.1]. The combination of Okuyama and Patterson discloses an interaction coefficient memory that stores an interaction matrix J that defines the interaction relationship of the binary quadratic model, and a coupling strength A that is a value related to the coupling.
However, Okuyama and Patterson does not explicitly disclose:
a signal ST supply line that supplies the temperature signal ST related to the temperature parameter T, and a signal SR supply line that supplies a random number signal SR that gives a uniform random number from 0 to 1.
calculates the next state based on the interaction matrix J, the coupling strength
λ
, the vector h, the temperature signal ST, and the random number signal SR
In the analogous art of ground state searching of Ising models using simulated annealing, Hayashi teaches
a signal ST supply line that supplies the temperature signal ST, and a signal SR supply line that supplies a random number signal SR [Figure 2, shows a spin unit with temperature and random signal supply lines; “We multiply temperature and random variables in each operator” Sec.V].
It would have been obvious to one of ordinary skill in the art, having the teachings of Okuyama, Patterson, and Hayashi before him before the effective filing date of the claimed invention to modify the information processing device disclosed by Okuyama, to implement the multiplication of the temperature and random variables inside the information processing device using supply lines as taught by Hayashi, in order to reduce the amount of circuitry required and improve scaling and parallel processing [Hayashi: Sec.V]. The combination of Okuyama, Patterson, and Hayashi discloses calculates the next state based on the interaction matrix J, the coupling strength
λ
, the vector h, the temperature signal ST, and the random number signal SR.
Regarding claim 4, Okuyama, Patterson, and Hayashi disclose the invention substantially as claimed. See the discussion of claim 3 above.
Okuyama discloses:
wherein the interaction matrix J is a real symmetric matrix ["the adjacent matrix, which is generally a symmetrical matrix…" par.53], and
the coupling strength A can be determined by numerical calculation based on the interaction matrix J and the constraints [“The maximum eigenvalue of the matrix J is required for the calculation of Formula 4, and the maximum eigenvalue attached with origin shift can be efficiently calculated by a commonly known algorithm called a power iteration method. This is to repeatedly execute a matrix-vector product, and the product-sum arithmetic device 515 can be utilized” par.59].
Regarding claim 5, Okuyama, Patterson, and Hayashi disclose the invention substantially as claimed. See the discussion of claim 3 above.
Okuyama discloses wherein the state is updated based on the hot bath method or the metropolis method ["there are transition probabilities according to the metropolis method and transition probabilities according to a heat bath method." par.26].
Regarding claim 10, Okuyama and Patterson disclose the invention substantially as claimed. See the discussion of claim 9 above.
wherein the arithmetic unit includes
a signal SR supply line for supplying a combined temperature signal ST related to a temperature parameter T, and a uniform random number of 0 to 1[“The signal SR represents an N-dimensional vector in which each element is a random number independent of each other. In this example, each element is the product of the temperature T and the random number -ln(u)/2. However, u is a uniform random number (0<u<=1)” par.60],
the comparison arithmetic unit [Figure 5,516+518] performs an operation based on simulated annealing by using the output value by the calculation, the signal SR as input values, and outputs the next state of the variable group as an output value [“The N-dimensional vector output from the product-sum arithmetic device 515 and the N-dimensional vector output from the vector multiplier 516 are input to the comparator 518” par.62; “Signal SP output from the comparator 518 is the next state of spin based on the MCMC” par.63].
Okuyama and Patterson does not explicitly disclose
a signal ST supply line for supplying a temperature signal ST relating to a temperature parameter T, and a signal SR supply line for supplying a random number signal SR that gives a uniform random number of 0 to 1, the comparison arithmetic unit using the temperature signal ST, and the random number signal SR as input values,
In the analogous art of ground state searching of Ising models using simulated annealing, Hayashi teaches
a signal ST supply line that supplies the temperature signal ST, and a signal SR supply line that supplies a random number signal SR [Figure 2, shows a spin unit with temperature and random signal supply lines; “We multiply temperature and random variables in each operator” Sec.V].
It would have been obvious to one of ordinary skill in the art, having the teachings of Okuyama, Patterson, and Hayashi before him before the effective filing date of the claimed invention to modify the information processing device disclosed by Okuyama, to implement the multiplication of the temperature and random variables inside the information processing device using supply lines as taught by Hayashi, in order to reduce the amount of circuitry required and improve scaling and parallel processing [Hayashi: Sec.V]. The combination of Okuyama, Patterson, and Hayashi discloses the comparison arithmetic unit using the temperature signal ST, and the random number signal SR as input values,
Regarding Claim 14, it is directed to claim 10. The claim is rejected for the reasons given above.
Claims 7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Okuyama, and in view of Patterson, and further in view of Yoshimura (US 2016/0063725 A1).
Regarding claim 7, Okuyama and Patterson disclose the invention substantially as claimed. See the discussion of claim 6 above.
Okuyama discloses:
patent literature JP-A-2016-51313 (PTL), which corresponds to Yoshimura [par.2-4].
Plurality of circuits implementing updating values of a plurality of non-adjacent spins in parallel [“When the MCMC or the SA is applied to the Ising model, the value of the spin is probabilistically determined based on Formula 2. Herein, it is possible to apply state transition based on Formula 2 to a plurality of non-adjacent spins at the same time. For this reason, for example, as described in PTL 1, by preparing a plurality of circuits implementing probabilistic processes based on Formula 2 and updating values of a plurality of non-adjacent spins in parallel” par.30]
A circuit comprising the first variable memory or the second variable memory is arranged in each of the plurality of circuit, and the first variable memory and the second variable memory store a group of variables summarized by constraints ["The first spin memory 513a stores information of an N-dimensional vector indicating the spin states of the first spin group of the complete bipartite graph described above. The second spin memory 513b stores information of an N-dimensional vector indicating the spin states of the second spin group of the complete bipartite graph" par.54; "the values of the spins of each group can be updated at the same time" par.38].
However, Okuyama and Patterson does not explicitly disclose:
wherein the arithmetic unit includes a unit that executes variable update processing, and a plurality of the units are provided, one for each constraint, and the first variable memory or the second variable memory is arranged in each of the plurality of units.
In the analogous art of ground state searching of Ising models architectures, Yoshimura teaches
wherein the arithmetic unit [Fig.6, Spin Array 110; Fig.13] includes a unit that executes variable update processing, and a plurality of the units are provided, one for each constraint [Fig.13, N000-N221 (spin unit 300); Fig.32A ], and spin memory [“multiple spin units each of which includes: a memory cell for storing a value of a specified spin (attention spin) of the Ising model…” par.61]
It would have been obvious to one of ordinary skill in the art, having the teachings of Okuyama, Patterson, and Yoshimura before him before the effective filing date of the claimed invention to modify the arithmetic unit spin updating circuitry disclosed by Okuyama and Patterson, to incorporate the spin array architecture as taught by Yoshimura, in order to update spins groups simultaneously, improving parallelism and efficiency [Yoshimura: par.142-147].
Regarding Claim 12, it is directed to claim 7. The claim is rejected for the reasons given above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wikipedia (NPL: “Power iteration”) discloses power iteration and relationship between matrix and eigenvalue.
Takemoto et al. (NPL: “A 2×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems”) discloses annealing processors with arrays of Spin circuitry. See fig.2.6.1 and 2.6.2.
Su et al. (NPL: “CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems”) discloses CMOS annealing processor. See figure 31.2.1.
Yamamoto et al. (NPL: “STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions”) discloses array of update units. See Figure 7.3.2 and 7.3.3.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182