DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application claims the benefit under 35 U.S.C. 119(a) of Korean Patent No. 10-2021-0156626, filed 11/15/2021. The benefit claim is acknowledged by the Examiner.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/05/2025 has been entered.
This action is responsive to the Applicant’s amendments filed on 12/05/2025. Claims 1, 3-6, 8-9, 11-17, and 20 remain pending in the application. Claims 1, 5, 8-9, 13-14, 17, and 19 have been amended. Claims 2, 10, 18, and 19 have been cancelled. Any examiner’s note, objection, and rejection not repeated is withdrawn due to Applicant’s amendment.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/26/2022 and 07/02/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Examiner’s Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Objections
Claim 13 is objected to because of the following informalities: “determined to correspond to the the one of the...” in line 7. The Examiner suggests removing one of the underlined “the”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 8-9, 11-13, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bagchi et al. (US 20160314055 A1) hereafter Bagchi in view of Kaul et al. (US 20160179728 A1) hereafter Kaul.
Regarding claim 1, Bagchi teaches:
An electronic device comprising:
cores of one or more processors (Paragraph 6, “an embedded device comprising: a processor”, a processor inherently includes cores);
one or more memories (Paragraph 6; “a code memory; and one or more module(s) stored in the code memory and configured for execution by the processor”) storing instructions configured to, when executed by the cores, configure the cores to:
prior to a second execution of an application that performs a simulation, perform a first execution of the application for operations of the application on the electronic device, the operations including performing different simulation phases (Paragraph 108, step 701; “first, an application is executed” performs a first execution of the application. It implies performance in a simulation environment as it may be performed “on an in-circuit emulator or a computer emulation”. This execution precedes a subsequent execution, “the method... on the test application can also perform well on a target application”, corresponding to a first execution prior to a second execution. During execution, the system performs multiple stages including reading values, retrieving data, and “compressed, e.g., in three different ways as depicted in step 703”, followed by classification, corresponding to different operational phases of the application during execution.);
during and in conjunction with the first execution, analyze data patterns of the data to determine dominant data patterns (Paragraph 108; “the value of all reads... are stored”, and thereafter “compressed... in three different ways”. The results are evaluated and “the smallest one is chosen”. Selecting among multiple compression outcomes based on the data corresponds to analyzing characteristics of the data to determine a most representative, corresponding to dominant, pattern. These operations are performed as part of the execution workflow, thereby occurring in conjunction with the first execution.);
select compression schemes according to the dominant data patterns (Paragraph 108; the data is “compressed... in three different ways” and “the smallest one is chosen”. The selected method is associated with the data as “the register is then marked with the corresponding type in a table”. Selection of a compression method based on evaluation of the data corresponds to selecting a compression scheme according to the dominant data pattern of the data.);
perform the second execution of the application, wherein during the second execution of the application, apply the previously selected compression scheme, wherein whichever of the compression schemes is applied is based on the compression schemes selected based on the dominant data patterns (Paragraphs 108-112; data is “compressed... in three different wats” and “the smallest one is chosen”, and the result is stored such that the “register is then marked with the corresponding type in a table”, which selects compression schemes based on analysis of data during a first execution. It further applies the selected compression schemes in subsequent processing, as compression is performed using type specific algorithms, where data is “compressed... into a compressed dataset” and “using an associated compression algorithm”. It further indicates reuse across executions, as “the method... on the test application can also perform well on a target application”, corresponding to performing a second execution in which the previously selected compression schemes are applied.).
Bagchi does not teach respectively corresponding communication phases of communicating data between the cores; or determining each time one of the communication phases is being performed.
However, Kaul teaches:
respectively corresponding communication phases of communicating data between the cores (Paragraph 53; communication between processing elements corresponding to cores is disclosed as “data communication between the source logic and the destination logic”, and signals are transmitted “from the core to each other port”. It further teaches multiple distinct stages of communication, including establishing a channel, transferring data, acknowledging receipt, and termination. These stages correspond to respective communication phases of communicating data between cores.);
determining each time one of the communication phases is being performed (Paragraph 53; “after an establishment of a circuit-switched channel, data communication... occurs”, “the source logic receives an acknowledgement indicating successful receipt”, and “when the last ack signal is received, the circuit-switched channel is closed”, teaches event-driven awareness of communication state which are explicitly recognized via signals, which requires the system to identify when each phase is occurring, thus corresponding to determining the current communication phase.).
Bagchi and Kaul are considered to be analogous to the claimed invention because they are in the same field of digital data processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bagchi to incorporate the teachings of Kaul and have utilized the idea of respective corresponding communication phases of communicating data between cores to determine which compression scheme to apply during each phase. A person of ordinary skill in the art would have recognized that coordinating data exchange between processing components using defined communication phases is a known method in the art whose implementation yields the predictable result of enabling efficient data transfer during execution. A person of ordinary skill in the art would have been motivated to do so because Bagchi expressly teaches improving communication efficiency based on data type, and Kaul involves repeated transfer of data segments between cores where bandwidth optimization is desirable.
Regarding claim 3, Bagchi in view of Kaul teach the device of claim 1. Kaul teaches:
wherein the cores comprise a source core and a destination core located in a same processor, in different processors, or in processors comprised in different electronic devices (Paragraph 53; “data communication between the source logic and the destination logic occurs”, where data is transmitted “from the core to each other port”, which discloses a source and destination core exchanging data. Such cores are implemented in a circuit-switched architecture which is consistent with allowing cores to be implemented within a same processor, in different processors, or in different devices, depending on the system configuration of the circuit-switched architecture.).
Regarding claim 6, Bagchi in view of Kaul teaches the device of claim 1. Bagchi teaches:
wherein the one or more processors comprise any one or any combination of: a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU) (Paragraph 115; “Processor 886, and other processing devices described herein, can each include one or more central processing units (CPU)”).
Regarding claim 8, Bagchi in view of Kaul teaches the device of claim 1. Bagchi teaches:
wherein information about the selected compression schemes is stored in association with the first execution and is used for the second execution to apply the selected compression schemes during the second execution (Paragraphs 107-112; generating and storing compression selection results from an initial execution is disclosed by “executing a predefined application program... recording values [and] compressing the recorded data”, in which “the register is then marked with the corresponding type in a table” and “a table of classifications of the registers... can be uploaded at compile time”. It further explicitly teaches reuse of stored selection for later execution, “the method of compression that performs the best on the test application can also perform well on a target application”, and is further “compressed... using an associated compression algorithm”.).
Regarding claim 9, Bagchi teaches:
A method comprising:
performing a second execution of an application that performs a simulation (Paragraph 108; “the method of compression that performs the best on the test application can also perform well on a target application”, where the test application is the first execution, and the target application is the second execution. The execution “may be performed on an in-circuit emulator or a computer emulation”, the emulator execution corresponding to a simulation.);
prior to beginning the second execution of the application on the cores, during and in conjunction with a first execution of the application, analyzing data patterns of the data exchanged between the cores to determine dominant data patterns (Paragraph 108; “executing a predefined application program... on a representative processor” and “recording values... during execution of the application” corresponds to performing a first execution for analysis activity. It further discloses “compressing the recorded data... int here different ways” and “of the three compressed versions, the smallest one is chosen”, which corresponds to evaluating data behavior across multiple schemes, selecting a best fit scheme, and identifying a dominant pattern via the best compression outcome.);
selecting compression schemes for the respective communication phases according to the dominant data patterns (Paragraph 108; the data is “compressed... in three different ways” and “the smallest one is chosen”. The selected method is associated with the data as “the register is then marked with the corresponding type in a table”. Selection of a compression method based on evaluation of the data corresponds to selecting a compression scheme according to the dominant data pattern of the data.);
when performing the second execution of the application, during the second execution of the application, apply the previously selected compression scheme, wherein whichever of the compression schemes is applied is based on the compression schemes selected based on the dominant data patterns (Paragraphs 108-112; data is “compressed... in three different wats” and “the smallest one is chosen”, and the result is stored such that the “register is then marked with the corresponding type in a table”, which selects compression schemes based on analysis of data during a first execution. It further applies the selected compression schemes in subsequent processing, as compression is performed using type specific algorithms, where data is “compressed... into a compressed dataset” and “using an associated compression algorithm”. It further indicates reuse across executions, as “the method... on the test application can also perform well on a target application”, corresponding to performing a second execution in which the previously selected compression schemes are applied.).
Bagchi does not teach communication phases of communicating data between the cores; performing a second execution of an application that performs a simulation in parallel on cores of an electronic device, including alternating between communication phases of data exchange of the application between the cores for respectively corresponding simulation phases of the simulation.
However, Kaul teaches:
communication phases of communicating data between the cores (Paragraph 53; communication between processing elements corresponding to cores is disclosed as “data communication between the source logic and the destination logic”, and signals are transmitted “from the core to each other port”. It further teaches multiple distinct stages of communication, including establishing a channel, transferring data, acknowledging receipt, and termination. These stages correspond to respective communication phases of communicating data between cores);
in parallel on cores of an electronic device (Paragraph 53; “data communication between the source logic and the destination logic”, and “two or more transfers... may occur simultaneously”, in which the source and destination logic correspond to cores and the simultaneous transfers correspond to parallel execution across cores.), including alternating between communication phases (Paragraph 53; establishment, transfer, acknowledgement, close, the repeating steps corresponding to alternating between communication phases) of data exchange of the application between the cores for respectively corresponding simulation phases of the simulation (Paragraph 53; “after an establishment of a circuit-switched channel”, “multiple segments can be communicated”, “receives an acknowledgement”, and “the circuit-switched channel is closed”. Communication occurs as part of execution flow and each phase is triggered by a state of the operation. Phases occur in a repeating sequence tied to processing, therefore the communication phases correspond to respective operational simulation phases of the application.).
Bagchi and Kaul are considered to be analogous to the claimed invention because they are in the same field of digital data processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bagchi to incorporate the teachings of Kaul and have utilized the idea of respective corresponding communication phases of communicating data between cores to determine which compression scheme to apply during each phase. A person of ordinary skill in the art would have recognized that coordinating data exchange between processing components using defined communication phases is a known method in the art whose implementation yields the predictable result of enabling efficient data transfer during execution. A person of ordinary skill in the art would have been motivated to do so because Bagchi expressly teaches improving communication efficiency based on data type, and Kaul involves repeated transfer of data segments between cores where bandwidth optimization is desirable.
Regarding claim 11, Bagchi in view of Kaul teaches the method of claim 9. Bagchi teaches:
wherein the cores perform the compression and decompression and are located either in a same processor or in different processors (Paragraph 113; multiple processors containing multiple cores is explicitly disclosed, “one or more processors “. Further, “a processor and computer-readable-medium carrying program instructions to cause the processor to carry out the run-time type-specific compression of non-deterministic data”, also “carrying out type-specific decompression”.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the processor of Bagchi in view of Kaul to use multiple cores within the same processor. Kaul provides the background for the use of a multi-core processor in Paragraph 2. “Networks-on-Chip (NoCs), for on-die communication between cores, are important in enabling scalable performance as the number of cores and intellectual property (IP) blocks increases in multi-core processors”. The use of multi-core processors are a known method yielding the predictable result of scalable improvements in performance through parallel processing.
Regarding claim 12, Bagchi in view of Kaul teaches the method of claim 9. Bagchi teaches:
wherein the electronic device comprises two computing devices, the computing devices comprising respective processors, the processors each comprising a respective one of the cores (Paragraph 113; “systems including multiple nodes, each having one or more processors, that intercommunicate”, multiple nodes correspond to multiple computing devices, each node containing its own processor, and each processor inherently includes at least one processor core.).
Regarding claim 13, Bagchi in view of Kaul teach the method of claim 9. Bagchi teaches:
wherein a second electronic device comprises a second core (systems including multiple nodes... that intercommunicate”, and “each having one or more processors”. Each node, corresponding to an electronic device, includes a processor and each processor inherently contains at least one core.);
using a compression scheme previously determined to correspond to the one of the communication phases (Paragraph 112; “compressing the recorded data for each of the plurality of NDRs”, and “selecting the register type associated with the smallest size”, and “associating each... with the selected register type in a table”, teaches pre-selection/association of compression methods to data types which are then used when that phase type is processed, supporting a compression scheme previously selected for a communication phase.).
Kaul teaches:
wherein the second execution of the application further comprises executing the application on the second core (Paragraph 53; “after an establishment of a circuit-switched channel, data communication... occurs over that circuit-switched channel” and “multiple segments can be communicated”, which teaches a subsequent execution/processing phase over an established channel, corresponding to a second execution context of the application’s communication behavior. Kaul ties operations to cores and inter-core execution endpoints, “forward (stream, tail) and reverse (ack) handshaking signals sent over dedicated channels from the core to each other port”, which teaches that operations originate at a core and communication occurs between multiple cores. Therefore, during a subsequent execution phase, the application is executed on the participating cores, of which the second core is a participant, thus corresponding to the second execution of the application comprising executing the application on the second core.);
one of the determined communication phases exchanges data between the second core and a core of the electronic device (Paragraph 53; “forward... and reverse (ack) handshaking signals sent over dedicated channels from the core to each other port”, discloses communications between cores over dedicated channels, thus supporting a communication phase exchanging data between a second core and another core of the device.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have one communication phase in Kaul that exchanges data between cores over a channel to be processed using a compression scheme previously selected and associated with that type of date/communication phase as disclosed by the pre-classification and compression selection mechanism of Bagchi.
Regarding claim 16, Bagchi in view of Kaul teaches the method of claim 9. Bagchi teaches:
A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 9 (Paragraph 118; “Various aspects herein may be embodied as computer program products including computer readable program code (“program code”) stored on a computer readable medium, e.g., a tangible non-transitory computer storage medium”).
Regarding claim 17, Bagchi teaches:
A method comprising:
performing a second execution of an application (Paragraph 108; “the method of compression hat performs the best on the test application can also perform well on a target application”, the target application corresponds to the second execution of the application);
the application performing a simulation (Paragraph 108; “execution may be performed on... a computer emulation of the target processor”, the emulation corresponding to a simulation);
the simulation phases generating data (Paragraph 108; “recording values from each of the plurality of NDRs... during execution of the application”, during first execution, i.e. the simulation, the system records values, corresponding to data.);
prior to second execution of the application, performing a first execution of the application (Paragraph 108, step 701; “first, an application is executed” performs a first execution of the application. It implies performance in a simulation environment as it may be performed “on an in-circuit emulator or a computer emulation”. This execution precedes a subsequent execution, “the method... on the test application can also perform well on a target application”, corresponding to a first execution prior to a second execution.);
during and in conjunction with the first execution, analyzing patterns of data movement between the cores to determine dominant patterns of data (Paragraph 108; “the value of all reads... are stored”, and thereafter “compressed... in three different ways”. The results are evaluated and “the smallest one is chosen”. Selecting among multiple compression outcomes based on the data corresponds to analyzing characteristics of the data to determine a most representative, corresponding to dominant, pattern. These operations are performed as part of the execution workflow, thereby occurring in conjunction with the first execution.);
selecting compression schemes for the respective communication phases according to the determined dominant data patterns (Paragraph 108; the data is “compressed... in three different ways” and “the smallest one is chosen”. The selected method is associated with the data as “the register is then marked with the corresponding type in a table”. Selection of a compression method based on evaluation of the data corresponds to selecting a compression scheme according to the dominant data pattern of the data.);
when performing the second execution of the application (Paragraph 108, step 701; “first, an application is executed” performs a first execution of the application. It implies performance in a simulation environment as it may be performed “on an in-circuit emulator or a computer emulation”. This execution precedes a subsequent execution, “the method... on the test application can also perform well on a target application”, the target application corresponding to the second execution.), applying a first of the compression schemes, selected during the first execution as corresponding to the first of the communication phases (Paragraphs 108-112; data is “compressed... in three different wats” and “the smallest one is chosen”, and the result is stored such that the “register is then marked with the corresponding type in a table”, which selects compression schemes based on analysis of data during a first execution. It further applies the selected compression schemes in subsequent processing, as compression is performed using type specific algorithms, where data is “compressed... into a compressed dataset” and “using an associated compression algorithm”.) to compress and decompress data exchanged between the cores by the first communication phase (Paragraph 113; multiple processors containing multiple cores is explicitly disclosed, “one or more processors “. Further, “a processor and computer-readable-medium carrying program instructions to cause the processor to carry out the run-time type-specific compression of non-deterministic data”, also “carrying out type-specific decompression”);
wherein whichever of the compression schemes is applied to any of the communication phases during the second execution is based on the compression schemes selected based on the dominant data patterns during the first execution (Paragraphs 108, 112; “executing a predefined application program”, in which values are recorded from the compression of the executed application, and “of the three compressed versions, the smallest one is chosen” and saved to a register for future execution. “the method of compression that performs the best on the test application can also perform well on a target application”, where the target application corresponds to the second execution. Paragraph 112 then discloses the use of an “associated compression algorithm” for each corresponding phase, the applied compression scheme being previously selected and associated via classification.);
compressing and decompressing data (Paragraphs 109-113; “compressing the uncompressed dataset” and “carrying out type-specific decompression” expressly teaches compression and decompression of data.).
Bagchi does not teach in parallel on two cores of a same processor; alternating between simulation phases that have respectively corresponding communication phases; the communication phases exchanging the data between the cores; determining each time that a first/second of the communication phases is to begin being performed; or data being exchanged between cores at the first/second communication phase.
However, Kaul teaches:
in parallel on two cores of a same processor (Paragraphs 2 and 53; “Networks-on-Chip (NoCs), for on-die communication between cores, are important in enabling scalable performance as the number of cores and intellectual property (IP) blocks increases in multi-core processors”, “data communication between the source and the destination logic occurs” and “two or more transfers... may occur simultaneously”, where simultaneous transfers correspond to operating in parallel.);
alternating between simulation phases (Paragraph 53; establishment, transfer, acknowledgement, close, the repeating steps corresponding to alternating between communication phases during the first simulation) that have respectively corresponding communication phases (Paragraph 53; “after an establishment of a circuit-switched channel”, “multiple segments can be communicated”, “receives an acknowledgement”, and “the circuit-switched channel is closed”. Communication occurs as part of execution flow and each phase is triggered by a state of the operation. Phases occur in a repeating sequence tied to processing, therefore the communication phases correspond to respective operational simulation phases of the application);
the communication phases exchanging the data between the cores (Paragraph 53; “forward... and reverse (ack) handshaking signals sent over dedicated channels from the core to each other port”, discloses communications between cores over dedicated channels, thus supporting a communication phase exchanging data between a second core and another core of the device);
respectively corresponding communication phases of communicating data between the cores (Paragraph 53; communication between processing elements corresponding to cores is disclosed as “data communication between the source logic and the destination logic”, and signals are transmitted “from the core to each other port”. It further teaches multiple distinct stages of communication, including establishing a channel, transferring data, acknowledging receipt, and termination. These stages correspond to respective communication phases of communicating data between cores.);
determining each time that a first of the communication phases is to begin being performed (Paragraph 53; “after an establishment of a circuit-switched channel, data communication... occurs”, “the source logic receives an acknowledgement indicating successful receipt”, and “when the last ack signal is received, the circuit-switched channel is closed”, teaches event-driven awareness of communication state which are explicitly recognized via signals, which requires the system to identify when each phase begins, thus corresponding to determining the beginning of the current communication phase.).
determining each time that a second of the communication phases is to begin being performed (Paragraph 53; “after an establishment of a circuit-switched channel, data communication... occurs”, “the source logic receives an acknowledgement indicating successful receipt”, and “when the last ack signal is received, the circuit-switched channel is closed”, teaches event-driven awareness of communication state which are explicitly recognized via signals, which requires the system to identify when each phase, whether the first, second, or plurality thereof, begins, thus corresponding to determining the beginning of the current communication phase.);
data exchanged between the cores by the first/second communication phase (Paragraph 53; “data communication between the source logic and the destination logic occurs” and communication is “from the core to each other port”, which teaches core to core data exchange over a communication phase.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the processor of Bagchi in view of Kaul to use multiple cores within the same processor. Kaul provides the background for the use of a multi-core processor in Paragraph 2. “Networks-on-Chip (NoCs), for on-die communication between cores, are important in enabling scalable performance as the number of cores and intellectual property (IP) blocks increases in multi-core processors”. The use of multi-core processors are a known method yielding the predictable result of scalable improvements in performance through parallel processing. Further, it would have been obvious to someone of ordinary skill in the art to have utilized the idea of respective corresponding communication phases of communicating data between cores to determine which compression scheme to apply during each alternating phase. A person of ordinary skill in the art would have recognized that coordinating data exchange between processing components that alternate between phases using defined communication phases is a known method in the art whose implementation yields the predictable result of enabling efficient data transfer during execution. A person of ordinary skill in the art would have been motivated to do so because Bagchi expressly teaches improving communication efficiency based on data type, and Kaul involves repeated transfer of data segments between cores where bandwidth optimization is desirable.
Regarding claim 19, Bagchi in view of Kaul teaches the method of claim 17. Bagchi teaches:
a first identified dominant pattern of data (Paragraph 112; “classifying the plurality of NDRs into three types”, and “compressing data from each type into a corresponding sub-dataset using an associated compression algorithm”, teaches identifying multiple distinct data patterns based on data characteristics and treating them differently, each corresponding to the first and second identified dominant data patterns.);
a second identified dominant pattern of data (Paragraph 112; “classifying the plurality of NDRs into three types”, and “compressing data from each type into a corresponding sub-dataset using an associated compression algorithm”, teaches identifying multiple distinct data patterns based on data characteristics and treating them differently, each corresponding to the first and second identified dominant data patterns).
Kaul teaches:
corresponding to the first of the communication phases (Paragraph 53; “after an establishment of a circuit-switched channel, data communication... occurs”, “multiple segments can be communicated”, “the source logic receives an acknowledgement”, where multiple distinct communication phases occur, corresponding to the first and second communication phases.);
corresponding to the second of the communication phases (Paragraph 53; “after an establishment of a circuit-switched channel, data communication... occurs”, “multiple segments can be communicated”, “the source logic receives an acknowledgement”, where multiple distinct communication phases occur, corresponding to the first and second communication phases).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to have combined the teachings of Bagchi with Kaul to have tied the dominant patterns of data to each communication phase. A person of ordinary skill in the art would have recognized that data exchanged during different communication phases have different patterns, and an association of different patterns to different communication phases would yield the predictable result of correct processing of data during execution.
Claims 4 and 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bagchi in view of Kaul, further in view of Ren et al. (US 20210158127 A1) hereafter Ren.
Regarding claim 4, Bagchi in view of Kaul teach the electronic device of claim 1. Bagchi in view of Kaul does not teach wherein the application comprises a molecular dynamics (MD) simulation, training of and/or inference by an artificial intelligence module, supercomputer-based processing, and/or a multi-node task.
However, Ren teaches:
wherein the application comprises a molecular dynamics (MD) simulation, training of and/or inference by an artificial intelligence module, supercomputer-based processing, and/or a multi-node task (Paragraph 77; “the parallel processing unit 1100 may be configured to accelerate numerous deep learning systems (e.g., graph neural network training and inference) and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation…”).
Bagchi, Kaul, and Ren are considered to be analogous to the claimed invention because they are in the same field of parallel processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bagchi in view of Kaul to incorporate the teachings of Ren and have the application comprise a MD simulation, training/inference by an artificial intelligence module, supercomputer-based processing, or multi-node task. These types of workloads typically involve large volumes of data and compute operations distributable across multiple processing units. A person of ordinary skill in the art would have recognized that these use cases would benefit from parallel communication across multiple cores of an electronic device, thus enabling efficient execution of these types of applications.
Regarding claim 14, Bagchi in view of Kaul teach the method of claim 9. Bagchi in view of Kaul does not teach wherein the simulation comprises a molecular dynamics (MD) simulation.
However, Ren teaches:
wherein the simulation comprises a molecular dynamics (MD) simulation (Paragraph 77; “the parallel processing unit 1100 may be configured to accelerate numerous deep learning systems (e.g., graph neural network training and inference) and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation…”).
Bagchi, Kaul, and Ren are considered to be analogous to the claimed invention because they are in the same field of parallel processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bagchi in view of Kaul to incorporate the teachings of Ren and have the simulation comprise a MD simulation. These types of workloads typically involve large volumes of data and compute operations distributable across multiple processing units. A person of ordinary skill in the art would have recognized that these use cases would benefit from parallel communication across multiple cores of an electronic device, thus enabling efficient execution of these types of applications.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bagchi in view of Kaul, further in view of Plotkin et al. (US 20180330045 A1) hereafter Plotkin, further in view of Annau et al. (US 20200218982 A1) hereafter Annau, further in view of Afzal et al. (US 11537853 B1) hereafter Afzal.
Regarding claim 5, Bagchi in view of Kaul teaches the device of claim 1. Bagchi teaches:
a first of the compression schemes is associated with communicating information, and wherein a second of the compression schemes is associated with communicating data (Paragraphs 108-112; “compressed... in three different ways [and] the smallest one is chosen”, in which “the register is then marked with the corresponding type in a table” and during execution, “compressed... using an associated compression algorithm” corresponds to predetermined information associating a compression scheme with a particular category of communicating information.).
Kaul teaches:
communication phases of communicating data between the cores (Paragraph 53; communication between processing elements corresponding to cores is disclosed as “data communication between the source logic and the destination logic”, and signals are transmitted “from the core to each other port”. It further teaches multiple distinct stages of communication, including establishing a channel, transferring data, acknowledging receipt, and termination. These stages correspond to respective communication phases of communicating data between cores.).
Bagchi in view of Kaul does not teach that the simulation comprises an MD simulation, contains simulated atom data, performs a block floating point-based compression scheme, or a zero-value-aware-based compression scheme.
However, Plotkin teaches:
A MD simulation containing simulated atom data including force data (Paragraph 23; “particular embodiments provide methods for predicting unfolding-specific protein epitopes which comprise molecular-dynamics-based simulations” and “parameters/variables corresponding to any sub-portion of the substantial portion of the protein or peptide aggregate based on geometrical/spatial criteria associated with the atoms, the location(s) of the atoms in the primary sequence, the secondary structure of particular atoms or the like”, explicitly discloses a MD simulation and data associated with simulated atoms. Paragraph 52 further discloses “the potential function V may be conveniently converted to forces which may in turn be used by the molecular dynamics engine” corresponding to force data used by the MD simulation).
Bagchi, Kaul, and Plotkin are considered to be analogous to the claimed invention because they are in the same field of parallel computing to perform simulation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bagchi in view of Kaul to incorporate the teachings of Plotkin and have the application comprise a MD simulation that contains simulated atom coordinate data. This type of workload typically involves large volumes of data and compute operations that can be distributed across multiple processing units. A person of ordinary skill in the art would have recognized that atom coordinate data is fundamental to MD simulations and would benefit from parallel communication across multiple cores of an electronic device, thus enabling efficient execution of those applications.
Bagchi in view of Kaul further in view of Plotkin does not teach a block floating point-based compression scheme or a zero-value-aware-based compression scheme.
However, Annau teaches:
a first compression scheme comprising a block floating point-based compression scheme (Paragraph 77; “converting values to a lower-precision format can save memory. But even if the overall count of bits used to represent numbers in the lower-precision format is not reduced (e.g., because more bits are used for mantissa values, even if an exponent is shared), conversion to a block floating-point format can improve computational efficiency for certain common operations”, explicitly disclosing the block-floating point scheme).
Bagchi, Kaul, Plotkin, and Annau are considered to be analogous to the claimed invention because they are in the same field of techniques for parallel processing. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Bagchi in view of Kaul further in view of Plotkin with Annau to have utilized a block floating point-based compression scheme. The prior art explicitly discloses motivation for a person of ordinary skill in the art that conversion to a block floating point format “can improve computational efficiency for certain common operations”.
Bagchi in view of Kaul further in view of Plotkin further in view of Annau does not teach a zero-value-aware-based compression scheme.
However, Afzal teaches:
a second compression scheme comprising a zero-value-aware-based compression scheme (Col. 2, lines 57-61; “the compression scheme configuration may include one or more types of compression, e.g., zero value compression, shared value compression, or a combination of zero value and shared value compression”).
Bagchi, Kaul, Plotkin, Annau, and Afzal are considered to be analogous to the claimed invention because they are in the same field of parallel processing. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Cheung in view of Zhang further in view of Plotkin further in view of Annau with Afzal and utilize a zero-value-aware-based compression scheme. Doing so would achieve the obvious and expected result of lower memory usage and enablement of larger models to run on resource-constrained devices due to tensors being more efficiently encoded.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Bagchi in view of Kaul, further in view of Xu et al. (US 20210295168 A1) hereafter Xu.
Regarding claim 15, Bagchi in view of Kaul teach the method of clam 9. Bagchi in view of Kaul does not teach wherein the application trains or implements a machine learning model.
However, Xu teaches:
wherein the application trains or implements a machine learning model (Paragraph 70, Fig. 11, step 1104; “At step 1104, training data is received at the first worker node. The training data may include training input data and corresponding reference output data. The training data may be used to train the neural network model.”, neural network model corresponds to machine learning model).
Bagchi, Kaul and Xu are considered to be analogous to the claimed invention because they are in the same field of parallel processing. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bagchi in view of Kaul to incorporate the teachings of Xu and train or implement a machine learning model. A person of ordinary skill in the art would have found the use of parallel processing to be a known method in machine learning implementation methodology yielding the predictable result of optimized processing.
Response to Arguments
Applicant's arguments filed 12/05/2025 have been fully considered. Applicant’s arguments are summarized below:
Claims 1-6 and 8-20 rejections under 35 U.S.C. 112(a) and 112(b) are moot in view of amendments to the claims.
Dependent claims are submitted as allowable.
Examiner’s response:
The Examiner agrees that the amendments to the claims resolve the previously outstanding rejections under 35 U.S.C. 112(a) and 112(b). Accordingly, the rejections of claims 1-6 and 8-20 under 35 U.S.C. 112(a) and 112(b) are withdrawn.
Independent claims 1, 9, and 17 remain rejected upon further consideration in light of the amendments. Therefore, contrary to Applicant's arguments, because the dependent claims depend from an unpatentable claim and does not add limitations that overcome the rejection, it likewise remains rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jiang et al. (US 20230022619 A1) discusses utilizing a knowledge base of compression information and utilizing information from the transfer data stream to assign respective compression times of the candidates to each segment.
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/KENNETH P TRAN/ Examiner, Art Unit 2196
/APRIL Y BLAIR/ Supervisory Patent Examiner, Art Unit 2196
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