DETAILED ACTION
This office action is in response to applicant’s remarks filed on March 12, 2026 in application 17/897,037.
Claims 1-20 are presented for examination. Claims 1, 11-12 are amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 12, 2026 have been fully considered but they are not persuasive.
Applicant stated that claim 1 has been amended to recite a “host being … configured to produce a marker indicating where corrupted data lies in the memory location.” and no combination of the cited art teaches “copying data held in memory location near and around, but not including, the failed memory location” and “placing copied data in a reserved area within the jolly,” as recited.
Examiner disagreed. Cheriton teach of relying on a secondary memory backup to implement fine-grain remapping in response to memory errors (col. 12 lines 11-67). Cheriton teach of using ECC or memory backup on secondary memory to recover the data (col. 12 lines 29-67). The recovered data is the data of the failed memory location and therefore is not copied/considered in the error recovery. It is the data being recovered and therefore is not copied. The uncorrupted data is moved and the corrupted data is repaired by scrubbing and remapping. The fine grained online for remapping for physical lines, and when a memory error occurs within a portion of PLID5, it is determined that at least some the remaining data or metadata of PLID5 may safely store a forwarding address. PLID5’s tag field is safe. The data content is copied to PLID 7 (fig. 5, col. 8 lines 55-67).
For these reasons, the rejections are maintained. Refer below for further details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheriton (US 9,502,139) in further view of Stevens (US 6,145,088) in further view of Achtenberg et al. (US 2018/0374548).
In regard to claim 1, Cheriton teaches a system comprising:
the host being configured to operate a patrol scrubbing routine, the patrol scrubbing routine being configured to scan and determine whether failures are present in the memory (memory scrubbing, col. 12, lines 11-28), the host being further configured to produce a marker indicating where the corruption data lies in a memory location (detect memory error and updating memory error records, col. 12 lines 11-28);
a jolly (physical line with PLID “PLID3” used to remapped, fig. 7, col. 13, lines 10-22, the jolly is described in applicant’s specification as a spare component (bank, section or row), para. 7); and
the memory controller being configured to receive information associated with a failed memory location within the memory, the information indicating an error at the failed memory location (detect if there is an error in the cell of an associated memory device, fig. 3B, col. 7 lines 5-25), the memory controller (memory controller may perform fine grained online remapping of physical memory along with other properties, col. 6 lines 3-20) being further configured to perform, upon receiving the information, operations including:
copying data held in memory locations near and around, but not including the failed memory location (remapping logic is invoked and remaps memory address XX to a separate physical memory line, col. 7 lines 5-25);
placing copied data in a reserved area within the jolly (to a separate physical memory line, col. 7 lines 5-35);
replacing a set of physical addresses associated with the failed memory location and a region near and around the failed memory location with a set of physical addresses associated with the reserved area, such that the copied data can be accessed using the set of physical addresses associated with the reserved area (remapping to handle memory errors using a structure memory, fig. 3a-fig. 3b, col. 6 lines 63-65, col. 7 lines 1-40); and
outputting to the central controller, the set of physical addresses associated with the reserved area (remapped to use the second physical memory line (PLID3) for data content, col. 13 lines 10-22).
Cheriton does not explicitly teach but Stevens teaches of conduct a data recovery off-line (restoration of data loss from offline backup, col. 1 lines 48-56, and perform data recovery remotely, col. 2 lines 22-40).
It would have been obvious to modify the system of Cheriton by adding Stevens remote data recovery. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing an off-site data recovery service to restore data loss from an offline backup (col. 1 lines 38-67).
Cheriton and Stevens does not explicitly teach but Achtenberg et al. teach a central controller communicatively coupled to a host (a controller with a front-end module that interface with a host and a back-end module that interfaces with one or more non-volatile memory, para. 3, para. 42) and a memory using a back-end block; a memory controller included within the back-end block and communicatively coupled to the memory the host (flash memory controller can format the flash memory to map out bad flash memory cells, and allocate spare memory cells to be substituted for future failed cells, fig. 3, para. 39).
It would have been obvious to modify the system of Cheriton and Stevens by adding Achtenberg et al. non-volatile storage with adaptive redundancy. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in utilizing the back-end module for error correction (para. 46).
In regard to claim 2, Cheriton teaches the system of claim 1, further including the host being configured to repair the memory at the failed memory location using an error correcting code (ECC logic in a physical line detects if there is an error in the cell to which the address is mapped and if memory error is detected, the remapping logic is invoked, fig. 3B, col. 7-35).
Cheriton does not explicitly teach but Stevens teaches repair the memory during the data recovery in an off-line mode (restoration of data loss from offline backup, col. 1 lines 48-56, and perform data recovery remotely, col. 2 lines 22-40).
Refer to claim 1 for motivational statement.
Cheriton and Stevens does not explicitly teach but Achtenberg et al. teach the central controller, and wherein the central controller is configured to received input logical addresses from the host (a controller with a front-end module that interface with a host and a back-end module that interfaces with one or more non-volatile memory, para. 3, para. 42).
Refer to claim 1 for motivational statement.
In regard to claim 3, Cheriton teaches the system of claim 2, wherein the system is further configured to operate unimpeded by using the set of physical addresses to retrieve data from the reserved area, the data corresponding to uncorrupted data at the region near and around the failed memory location (remaps memory address XX to a separate physical memory line containing the same data content, fig. 3B, col. 7 lines 5-35).
In regard to claim 4, Cheriton teaches the system of claim 1, wherein the memory controller is configured to receive the information from a patrol scrubber (memory scrubber, col. 5 lines 5-25).
In regard to claim 5, Cheriton teaches the system of claim 1, wherein the memory location spans a range of addresses (address XX to a separate physical memory line, col. 7 lines 5-35).
In regard to claim 6, Cheriton teaches the system of claim 5, wherein the range of addresses includes a plurality of non-consecutive physical memory locations (detect an error in the cell, col. 7 lines 5-35, fine grained online remapping, fig. 3B).
In regard to claim 7, Cheriton teaches the system of claim 1, wherein the memory controller is further configured to classify the error based on the received information (if the error is correctable or transient, the remapping logic copies the contents of the original memory line to the separate memory line .. if the content cannot be extracted, the system may be able to recover from an uncorrectable memory error by copying the memory content from corresponding backup memory location, col. 7 lines 5-45).
In regard to claim 8, Cheriton teaches the system of claim 7, wherein the memory controller is configured to classify the error as recoverable or as unrecoverable (if the error is correctable or transient, the remapping logic copies the contents of the original memory line to the separate memory line .. if the content cannot be extracted, the system may be able to recover from an uncorrectable memory error by copying the memory content from corresponding backup memory location, col. 7 lines 5-45).
In regard to claim 9, Cheriton teaches the system of claim 8, wherein when the error is classified as unrecoverable, the memory controller is further configured to notify a host that the memory location has an unrecoverable error (if the error is correctable or transient, the remapping logic copies the contents of the original memory line to the separate memory line .. if the content cannot be extracted, the system may be able to recover from an uncorrectable memory error by copying the memory content from corresponding backup memory location, col. 7 lines 5-45).
In regard to claim 10, Cheriton teaches the system of claim 9, wherein the system is further configured to remove one or more addresses corresponding to the unrecoverable error from a pool of valid addresses available to the host (remapping to handle memory errors, col. 7 lines 5-35).
In regard to claim 11, Cheriton teaches a method comprising:
receiving, by a memory controller communicatively coupled to the memory, information identifying an error at a failed memory location in the memory (detect if there is an error in the cell of an associated memory device, fig. 3B, col. 7 lines 5-25);
marking the failed memory location as having corrupted data (detect memory error and updating memory error records, col. 12 lines 11-28);
copying data held in the memory locations near and around, but not including, the failed memory location (remapping logic is invoked and remaps memory address XX to a separate physical memory line, col. 7 lines 5-25);
placing copied data in a reserved area within a jolly (physical line with PLID “PLID3” used to remapped, fig. 7, col. 13, lines 10-22, the jolly is described in applicant’s specification as a spare component (bank, section or row), para. 7);
replacing a set of physical addresses associated with the failed memory location and a region near and around the failed memory location with a set of physical addresses associated with the reserved area, such that the copied data can be accessed using the set of physical addresses associated with the reserved area (remapping to handle memory errors using a structure memory, fig. 3a-fig. 3b, col. 6 lines 63-65, col. 7 lines 1-40);
outputting, by the central controller, the set of physical addresses associated with the reserved area (remapped to use the second physical memory line (PLID3) for data content, col. 13 lines 10-22); and
Cheriton does not explicitly teach but Stevens teaches mitigating memory errors offline by repairing or permanently retiring the failed memory location (restoration of data loss from offline backup, col. 1 lines 48-56, and perform data recovery remotely, col. 2 lines 22-40).
It would have been obvious to modify the system of Cheriton by adding Stevens remote data recovery. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing continuously handles message while in recovery operations (col. 16 lines 46-67).
Cheriton and Stevens does not explicitly teach but Achtenberg et al. teach communicatively coupling a central controller to a host and a memory (a controller with a front-end module that interface with a host and a back-end module that interfaces with one or more non-volatile memory, para. 3, para. 42).
It would have been obvious to modify the system of Cheriton and Stevens by adding Achtenberg et al. non-volatile storage with adaptive redundancy. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in utilizing the back-end module for error correction (para. 46).
In regard to claim 12, Cheriton does not explicitly teach but Stevens teaches the method of claim 10, further comprising repairing, by the host, the error at the failed memory location using an error correcting code in an off-line mode (restoration of data loss from offline backup, col. 1 lines 48-56, and perform data recovery remotely, col. 2 lines 22-40).
Refer to claim 1 for motivational statement.
In regard to claim 13, Cheriton teaches the method of claim 12, further including operating unimpeded by using the set of addresses to retrieve data from the reserved area, the data corresponding to uncorrupted data associated with the set of physical addresses corresponding to the region near and around the failed memory location (remaps memory address XX to a separate physical memory line containing the same data content, fig. 3B, col. 7 lines 5-35).
In regard to claim 14, Cheriton teaches the method of claim 10, further including receiving, by the memory controller, the information from a patrol scrubber (memory scrubber, col. 5 lines 5-25).
In regard to claim 15, Cheriton teaches the method of claim 10, wherein the memory location spans a range of addresses corresponding to a plurality of non-consecutive physical memory locations (address XX to a separate physical memory line, col. 7 lines 5-35).
In regard to claim 16, Cheriton teaches the method of claim 15, wherein the range of addresses includes one or more specified addresses where the error is located (detect an error in the cell, col. 7 lines 5-35).
In regard to claim 17, Cheriton teaches the method of claim 10, further including classifying, by the memory controller, the error based on the received information (if the error is correctable or transient, the remapping logic copies the contents of the original memory line to the separate memory line .. if the content cannot be extracted, the system may be able to recover from an uncorrectable memory error by copying the memory content from corresponding backup memory location, col. 7 lines 5-45).
In regard to claim 18, Cheriton teaches the method of claim 17, wherein the classifying includes marking the error as recoverable or as unrecoverable (if the error is correctable or transient, the remapping logic copies the contents of the original memory line to the separate memory line .. if the content cannot be extracted, the system may be able to recover from an uncorrectable memory error by copying the memory content from corresponding backup memory location, col. 7 lines 5-45).
In regard to claim 19, Cheriton teaches the method of claim 18 further comprising, notifying the host that the memory location has an unrecoverable error when the error is classified unrecoverable (if the error is correctable or transient, the remapping logic copies the contents of the original memory line to the separate memory line .. if the content cannot be extracted, the system may be able to recover from an uncorrectable memory error by copying the memory content from corresponding backup memory location, col. 7 lines 5-45).
In regard to claim 20, Cheriton teaches the method of claim 19, further including removing one or more addresses corresponding to the unrecoverable error from a pool of valid addresses available to the host (remapping to handle memory errors, col. 7 lines 5-35).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Lastras et al. (US 2015/0019905) (IBM) stale data scrub
Lastras et al. (US 2014/0310570) (IBM) stale data scrub
Gollub et al. (US 2014/0195852) (IBM) detect error at memory location
Gollub et al. (US 2014/0195867) (IBM) memory testing and detecting errors
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Wang et al. (US 11,835,612) recover the corrupted K-space data
Lin et al. (US 11,798,614) recover the corrupted codewords
Manjunath et al. (US 11,640,332) repair corrupted data based on the uncorrupted data
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Biswas et al. (US 2009/0271676) error detection/recovery mechanism
Mestery et al. (US 2022/0116311) front end and back end controller for load balancing
Eemani et al. (US 11,487,439) correct fatal error
Gunasekaran et al. (US 10,911,540) front-end and back-end storage array
Radovanovic (US 8,725,906) SAN controller with error recovery
Stiffler et al. (US 6,622,263) System directed checkpointing
Micka et al. (US 5,592,618) memory controller and recovery offline
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Ryu et al. (US 2022/0197739) error check and scrub, store page offline
Liu et al. (US 2022/0019564) scrubbing and offline analysis
Velayuthaperumal et al. (US 2020/0159621) scrub and identified failed block can go offline
Gilda et al. (US 2017/0091023) error information collected during scrub
Chen et al. (US 2014/0068365) read scrub and offline channel tracking
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Brown et al. (US 11,182,094) recovery copy command
Mullins et al. (US 2003/0005353) repair algorithm executed offline
Briggs et al. (US 6,545,830) offline recalibrated
Rothberg (US 6,661,591) offline retry procedure
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Kim et al. (US 2022/0374309) detects uncorrectable errors
Azad et al. (US 11,429,481) scrubbing technique
Li (US 2020/0004624) scrubbing can correct one error
Benedict et al. (US 2016/0092306) detailed scrub for uncorrectable error, two error corrector
Son et al. (US 2014/0146624) correct errors including uncorrectable errors
Dell et al. (US 2008/0162991) uncorrectable error signal
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOAN TRUONG whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 Loan.truong@uspto.gov
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