Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 31, 2026 has been entered.
Response to Arguments
Applicant’s arguments, filed March 31, 2026, with respect to claims 1, 13, and 21 have been considered but are moot because of the new ground of rejection.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: the location of "a temperature output terminal" reference is not shown on Fig. 5. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
Regarding claim 1, using Fig. 5, examiner interprets "a first current source" and "a second current source" could be either 402 or 404; "a first current" and "a second current" could be either I1 or I2; "a first switch" could be either 406 or 408; "a temperature output terminal" is the node at 420 between 412 and 414; "a capacitor" is 412; and "a second switch" is 414.
Regarding claim 13, using Fig. 5, examiner interprets "a first current source" and "a second current source" could be either 402 or 404; "a first current" and "a second current" could be either I1 or I2; "a first switch" and "a second switch" could be either 406 or 408; "a third switch" is 414; "a temperature output terminal" is the node at 420 between 412 and 414; and "a capacitor" is 412.
Regarding claim 21, using Fig. 5, examiner interprets "a first current source" and "a second current source" could be either 402 or 404; "a first current" and "a second current" could be either I1 or I2; "a first switch" and "a second switch" could be either 406 or 408; "a capacitor" is 412; "a temperature output terminal" is the node at 420 between 412 and 414; and "a third switch" is 414.
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Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13-16 and 21-22 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by McLeod (US 7281846 B2); hereinafter McLeod.
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Applicant’s drawing with interpreted location (per claim interpretation above) of a temperature output terminal.
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McLeod’s location of a temperature output terminal.
Regarding Claim 13, McLeod discloses a method for sensing a temperature of a component, the method comprising: providing a first current [Fig. 1, NI] to a diode input terminal [102] by closing a first switch [P1/110 at the output of 104] that is coupled between a first current source [104] and the diode input terminal; providing a second current [I] to the diode input terminal by opening the first switch and closing a second switch [P2/112 at the output of 106] that is coupled between a second current source [106] and the diode input terminal; opening and closing a third switch [P1/110, wherein terminal of P1/110 is in between Co/122 and P2/112] synchronously with the opening and closing of the first switch, the third switch coupled between a temperature output terminal [terminal of P1/110 is in between Co/122 and P2/112] and a ground terminal [gnd], wherein closing the third switch shorts the temperature output terminal to the ground terminal; coupling a capacitor [124/Ct] between the diode input terminal and the temperature output terminal; and providing a voltage signal [Voffset] at the temperature output terminal that is indicative of a temperature of the component [column 2, lines 58-59; temperature offset capacitor (Co) prior to the temperature output terminal].
Regarding Claim 14, McLeod discloses the method of claim 13, wherein the voltage signal at the temperature output terminal is a difference in voltage across the component with the first current provided to it, and with the second current provided to it [column 2, lines 25-59].
Regarding Claim 15, McLeod discloses the method of claim 13, wherein the component is a diode [102].
Regarding Claim 16, McLeod discloses the method of claim 13, wherein the component is a transistor [column 5, lines 42-55].
Regarding Claim 21, McLeod discloses a circuit for temperature sensing [Fig. 1], the circuit comprising: a first current source [104] having a first current output [output of 104] coupled to a component input terminal [upper node of 102] of a component [102], the first current source capable of providing a first current [NI] at the first current output; a second current source [106] having a second current output [output of 106] coupled to the component input terminal, the second current source capable of providing a second current [I] at the second current output; a first switch [P1/110 at output of 104] coupled between the first current output and the component input terminal; a second switch [P2/112 at output of 106] coupled between the second current output and the component input terminal; a capacitor [Ct/124] coupled between the component input terminal and a temperature output terminal [[terminal of P1/110 is in between Co/122 and P2/112]; a third switch [P1/110, wherein terminal of P1/110 is in between Co/122 and P2/112] coupled between the temperature output terminal and a ground terminal [gnd] and configurable to short the temperature output terminal to the ground terminal, wherein: the circuit capable of a first state wherein the first switch and third switch close synchronously, the second switch opens, and the first current is produced at the first current output [Column 2, lines 25-59]; the circuit capable of a second state wherein the first switch and the third switch open synchronously, the second switch closes, and the second current is produced at the second current output [Column 2, lines 25-59]; and the capacitor is capable of providing a voltage signal [Voffset] to the temperature output terminal, in which the voltage signal indicates a temperature at the component [Column 2, lines 25-59; temperature offset capacitor (Co) prior to the temperature output terminal].
Regarding Claim 22, McLeod discloses the circuit of claim 21, wherein the voltage signal at the temperature output terminal is a difference in voltage across the component with the first current provided to the component input terminal, and with the second current provided to it [Column 2, lines 25-59].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Holloway et al. (US 6962436 B1), in view of McLeod; hereinafter Holloway, in view of McLeod.
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Applicant’s drawing with interpreted location (per claim interpretation above) of a temperature output terminal.
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Holloway’s location of a temperature output terminal.
Regarding Claim 1, Holloway discloses a circuit [Fig. 1] comprising: a first current source [105C] having a first current output [output of 105C] coupled to a diode input terminal [107], the first current source configured to provide a first current [Ic] at the first current output; a second current source [105B] having a second current output [output of 105B], the second current source configured to provide a second current [Ib] at the second current output; a first switch [S4] coupled between the second current output and the diode input terminal; a capacitor [Cdac1] coupled between the diode input terminal and a temperature output terminal [109], [Cdac1 coupled between 107 and 109 thru Cdac2]; and a second switch [S6] coupled between the temperature output terminal and a ground terminal [ground below S6], and configurable to short the temperature output terminal to the ground terminal, wherein the capacitor is capable of providing a voltage signal [Vdac1] to the temperature output terminal, in which the voltage signal indicates a temperature at the diode input terminal [column 6, lines 27-39]. Holloway does not explicitly disclose wherein the second current is larger than the first current.
However, McLeod discloses wherein the second current (Fig. 1, 104, NI) is larger than the first current (Fig. 1, 106, I). (Column 2, lines 27-30). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of McLeod in the invention of Holloway, with the expected benefit of providing a more accurate temperature measurement. This method of improving Holloway using McLeod was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of McLeod. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Holloway and McLeod to obtain the invention: incorporating the current sources with the two different size currents.
Regarding Claim 2, Holloway, in view of McLeod, discloses the circuit of claim 1, wherein the capacitor is a first capacitor [Holloway, Cdac1], and the circuit further comprises: an amplifier [Holloway, 112] having a first amplifier input [Holloway, inverting (-)] and an amplifier output [Holloway, output of 112]; a third switch [Holloway, S5] coupled between the temperature output terminal and the first amplifier input; and a second capacitor [Holloway, Cdac2] coupled between the first amplifier input and the ground terminal.
Claims 3, 5-7, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Holloway, in view of McLeod, further in view of Hunter (US 12155300 B2); hereinafter Holloway, in view of McLeod, further in view of Hunter.
Regarding Claim 3, Holloway, in view of McLeod, does not explicitly disclose the circuit of claim 2, further comprising: a fourth switch coupled between a second amplifier input and a first reference voltage terminal, the first reference voltage terminal providing a first reference voltage; and a fifth switch coupled between the second amplifier input and a second reference voltage terminal, the second reference voltage terminal providing a second reference voltage.
However, Hunter discloses a circuit [Fig. 2] further comprising: a fourth switch [250] coupled between a second amplifier input [non-inverting (+) of 218] and a first reference voltage terminal, the first reference voltage terminal providing a first reference voltage [Vref(+)]; and a fifth switch [252] coupled between the second amplifier input and a second reference voltage terminal, the second reference voltage terminal providing a second reference voltage [Vref(-)]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Hunter in the invention of Holloway, in view of McLeod, with the expected benefit of accommodating different temperature characteristics. This method of improving Holloway, in view of McLeod, using Hunter was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Hunter. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Holloway, in view of McLeod, and Hunter to obtain the invention: incorporating the teachings of Hunter's additional switches and reference voltages at Holloway's non-inverting amplifier input.
Regarding Claim 5, Holloway, in view of McLeod, further in view of Hunter, discloses the circuit of claim 3, further comprising: a sixth switch [McLeod, Fig. 1, P2/112 at the output of 106] coupled between the first current source [McLeod, 106] and the diode input terminal [McLeod, node above 102], wherein the sixth switch and the first switch [McLeod, P1/110 at the output of 104] close alternately [Mcleod, Column 2, lines 33-53] to provide either the first current or the second current to the diode input terminal.
Regarding Claim 6, Holloway, in view of McLeod, further in view of Hunter, does not explicitly disclose the circuit of claim 5, wherein the sixth switch is closed for a first period of a cycle, and the first switch is closed for a second period of the cycle, and the first period is longer than the second period. It would have been obvious to one having ordinary skill in the art at the time the invention was made to interpret that when one switch is closed for a first period of a cycle, and another switch is closed for a second period of a cycle, that the first period can be longer than the second period, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding Claim 7, Holloway, in view of McLeod, further in view of Hunter, does not explicitly disclose the circuit of claim 6, wherein the first period is at least twice as long as the second period of the cycle. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the first period be at least twice as long as the second period of the cycle, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding Claim 11, Holloway, in view of McLeod, further in view of Hunter, discloses the circuit of claim 3, wherein the first reference voltage and the second reference voltage represent first and second temperature limits, respectively [Hunter, column 6, lines 9-21].
Regarding Claim 12, Holloway, in view of McLeod, further in view of Hunter, discloses the circuit of claim 11, wherein the first reference voltage is higher than the second reference voltage [Hunter, column 4, lines 56-63].
Claims 17-20 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over McLeod, in view of Chen (US 20130308359 A1); hereinafter McLeod, in view of Chen.
Regarding Claim 17, McLeod does not explicitly disclose the method of claim 13, further comprising: comparing the voltage signal at the temperature output terminal to a first reference voltage; and asserting a fault indication signal responsive to the voltage signal at the temperature output terminal having a higher voltage than the first reference voltage.
However, Chen discloses the method [Fig. 2] wherein comparing the voltage signal at the temperature output terminal [output of 31] to a first reference voltage [Vref2 at 33]; and asserting a fault indication signal [output of 26] responsive to the voltage signal at the temperature output terminal having a higher voltage than the first reference voltage. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Chen in the invention of McLeod, with the expected benefit of accommodating different temperature characteristics. This method of improving McLeod using Chen was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Chen. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of McLeod and Chen to obtain the invention: modifying McLeod's amplifier input to incorporate the teachings of Chen's comparator and reference voltage.
Regarding Claim 18, McLeod, in view of Chen, discloses the method of claim 17, wherein after asserted, the fault indication signal remains asserted until the voltage signal at the temperature output terminal is lower in voltage than a second reference voltage [Chen, Vref1], the second reference voltage being lower in voltage than the first reference voltage [Chen, paragraph 0035].
Regarding Claim 19, McLeod, in view of Chen, discloses the method of claim 18, wherein the voltage signal at the temperature output terminal is compared to either the first reference voltage or the second reference voltage, depending on a value of the fault indication signal [Chen, Abstract].
Regarding Claim 20, McLeod, in view of Chen, discloses the method of claim 17, further comprising: turning off the component responsive to the fault indication signal being asserted [McLeod, column 2, lines 60-67; column 3, lines 1-4].
Regarding Claim 23, McLeod does not explicitly disclose the circuit of claim 22, comparing the voltage signal at the temperature output terminal to a first reference voltage; and asserting a fault indication signal responsive to the voltage signal at the temperature output terminal having a higher voltage than the first reference voltage.
However, Chen discloses the circuit [Fig. 2] wherein comparing the voltage signal at the temperature output terminal [output of 31] to a first reference voltage [Vref2 at 33]; and asserting a fault indication signal [output of 26] responsive to the voltage signal at the temperature output terminal having a higher voltage than the first reference voltage. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Chen in the invention of McLeod, with the expected benefit of accommodating different temperature characteristics. This method of improving McLeod using Chen was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Chen. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of McLeod and Chen to obtain the invention: modifying McLeod's amplifier input to incorporate the teachings of Chen's comparator and reference voltage.
Regarding Claim 24, McLeod, in view of Chen, discloses the circuit of claim 23, wherein after asserted, the fault indication signal remains asserted until the voltage signal at the temperature output terminal is lower in voltage than a second reference voltage [Chen, Vref1], the second reference voltage being lower in voltage than the first reference voltage [Chen, paragraph 0035].
Regarding Claim 25, McLeod, in view of Chen, discloses the circuit of claim 24, wherein the voltage signal at the temperature output terminal is compared to either the first reference voltage or the second reference voltage, depending on a value of the fault indication signal [Chen, Abstract].
Allowable Subject Matter
Claims 4 and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: claim 4, is objected to because the prior art of the record does not disclose nor render obvious wherein.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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