Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/27/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 7 recites the limitation “wherein the first electrode covers an entirety of the plurality of protrusions” in the claim, which lacks the full support of the original disclosure. The elected species of Fig. 2 shows that the first electrode 130 does not cover at least the bottom horizontal surfaces of the plurality of protrusions 211a’. Thus, this limitation lacks the full support of the original disclosure.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5-8 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the central portion" in the 19th line of the claim. It is unclear whether this limitation refers to “a central portion of the first semiconductor layer” in the 11th line of the claim or “a central portion of the second semiconductor layer” in the 12th and 13th lines of the claim.
Claims 5-8 and 10 are rejected because they depend on the rejected claim 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 3 and 5-6, 8 and 10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Saito et al. (US 2014/0361321 A1).
Regarding claim 3, Saito et al. teaches in Fig. 3, a light-emitting diode (LED) device (1; [0074]) comprising: a light emitting layer (20; [0075]) having a core shell structure (23 is the core, 22 and 21 are the shell; see Fig. 3) comprising: a first semiconductor layer (22; [0082]) having a first surface (the external surface of the upper half of 22) through which light is emitted (light extraction area; [0084]); an active layer (23; [0082]) formed adjacent to the first semiconductor layer (22), the active layer (23) surrounding a second surface (the bottom surface of 22), a third surface (the left half of the bottom surface of 22) and a fourth surface (the right half of the bottom surface of 22) of the first semiconductor layer (22), the fourth surface (the right half of the bottom surface of 22) being opposite to the first surface (the external surface of the upper half of 22), and the second and third surfaces (the bottom surface of 22 and the left half of the bottom surface of 22) being side surface (the bottom side surface) of the first semiconductor layer (22); and a second semiconductor layer (21; [0082]) formed adjacent to the active layer (23); a passivation layer (40/51; [0097, 0102]) provided on the light emitting layer (20) including an end portion (the left end) of the active layer (23) at the first surface (the external surface of the upper half of 22) of the first semiconductor layer (22), the passivation layer (40/51) including a first opening (the opening of 40) at a central portion of the first semiconductor layer (the center section including portions of the top surface and the bottom surface of 22; see Fig. 3 below) on the first surface (the external surface of the upper half of 22) of the first semiconductor layer (22) and a second opening (the bottom opening of 51) at a central portion of the second semiconductor layer (the center section including portions of the top surface and the bottom surface of 21) on a first surface (the bottom surface) of the second semiconductor layer (21); a first electrode (710; [0076]) provided in the first opening (the opening of 40) to contact the first semiconductor layer (22); a second electrode (720; [0076]) provided in the second opening (the bottom opening of 51) to contact the second semiconductor layer (21); and a plurality of protrusions (the protrusions of 22 above the bottommost points of the grooves of the top surface of 22; [0085]) formed at the central portion (the center section including portions of the top surface and the bottom surface of 22; see Fig. 3 below) on the first surface (the external surface of the upper half of 22) of the first semiconductor layer (22), wherein the end portion of the active layer (the left end of 23), the first surface of the first semiconductor layer (the external surface of the upper half of 22 including the upper half of the left side surface of 22) and a first surface of the passivation layer (the left inner side surface of 40/51) are coplanar on a light emitting side of the LED device (the upper side of 1; see Fig. 3).
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[AltContent: rect][AltContent: rect][AltContent: textbox (Central portion of a first semiconductor layer)][AltContent: textbox (Central portion of a second semiconductor layer)][AltContent: arrow][AltContent: arrow]
Fig. 3 of Saito et al. shows the center regions of the first and second semiconductor layers
Regarding claim 5, Saito et al. teaches in Fig. 3, the LED device of claim 3, wherein the first electrode (710) is provided on an upper surface of the plurality of protrusions (the protrusions of 22 above the bottommost points of the grooves of the top surface of 22; see Fig. 3).
Regarding claim 6, Saito et al. teaches in Fig. 3, the LED device of claim 3, wherein the first electrode (710) is provided directly on an upper surface of the plurality of protrusions (the protrusions of 22 above the bottommost points of the grooves of the top surface of 22; see Fig. 3).
Regarding claim 8, Saito et al. teaches in Fig. 3, the LED device of claim 3, wherein the first electrode (710) comprises a first portion (the bottom half portion) provided on an upper surface of the plurality of protrusions (the protrusions of 22 above the bottommost points of the grooves of the top surface of 22) and a second portion (the upper half portion) provided on an upper surface of the passivation layer (40/51; see Fig. 3).
Regarding claim 10, Saito et al. teaches in Fig. 3, the LED device of claim 3, wherein the passivation layer (40/51) is a monolithic (interpreted as huge, massive based on the definition of “monolithic” in https://www.merriam-webster.com/dictionary/monolithic: “of, relating to, or resembling a monolith : huge, massive”) layer provided between the first opening (the opening of 40) and the second opening (the bottom opening of 51).
Response to Arguments
Applicant's arguments with respect to claim 3 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeong (US 2014/0070256 A1) teaches a light emitting device having a passivation layer covering the side surfaces of the semiconductor layers with a top opening and a bottom opening.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 3/4/2026