DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed December 2, 2025 have been entered and considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kitahara (US 20040159893 A1), in view of Shibata et al. (US 7084465 B2).
Regarding claim 1, Kitahara teaches:
A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate [1, paragraph [0020], Fig. 2(a)] having a first polarity type [P-type];
forming a patterned mask layer [81 “silicon nitride film”, paragraph [0038], Fig. 2(b)] over the semiconductor substrate [1];
forming a deep well [150, paragraph [0063], Fig. 5] within the semiconductor substrate [1] using the patterned mask layer [81], wherein the deep well [150] has (1) a second polarity type [N-type] different from the first polarity type [P-type] and (2) an adjusted well depression having a depression width measured along a lateral direction;
removing the patterned mask layer [81, paragraph [0044], Fig. 3(b)];
forming complementary wells [140, 110, Fig. 5] in the semiconductor substrate [1] and above and connected to the deep well [150, Fig. 5],
wherein the complementary wells [140, 110, Fig. 5] are adjacent to, directly contacting, and peripheral to current flowing terminals [UNT, LNT, Fig. 5] of the semiconductor device; and
wherein the complementary wells [140/110, paragraph [0063], Fig. 5] connected to the deep well [150, paragraph [0063], Fig. 5] surround and define an isolated well [130/120, paragraph [0063], Fig. 5] in the semiconductor substrate [1, paragraph [0063], Fig. 5] dedicated to provide a current flow along a length of one corresponding current channel,
forming a gate portion over the semiconductor substrate [1] and between the complementary wells [140, 110], the gate portion configured to control the current flow between the current flowing terminals, wherein the gate portion corresponds to a gate interface width.
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Drawings and pictures can anticipate claims if they clearly show the structure
which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the
picture must show all the claimed structural features and how they are put together.
Jockmus v. Leviton, 28F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial.
For instance, drawings in a design patent can anticipate or make obvious the claimed
invention as can drawings in utility patents. When the reference is a utility patent, it does
not matter that the feature shown is unintended or unexplained in the specification. The
drawings must be evaluated for what they reasonably disclose and suggest to one of
ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979).
(MPEP 2125)
Kitahara does not teach:
an adjusted well depression having a depression width measured along a lateral direction across opposing edges of a concave surface of the adjusted well depression.
wherein the concave surface is continuously concave between the complementary wells;
wherein the gate portion corresponds to a gate interface width that overlaps the depression width and is less than the depression width.
Shibata et al. teaches:
an adjusted well depression [12, Col. 14, Line 30 to Col. 18, Line 27, Fig. 4] having a depression width measured along a lateral direction across opposing edges of a concave surface of the adjusted well depression [12, Fig. 4].
wherein the concave surface [12, Col. 13, Lines 37-67 to Col. 14, Lines 1-18, Fig. 3] is continuously concave between the complementary wells [14, 15, Fig. 3];
wherein the gate portion [26, Col. 3, Lines 1-9, Fig. 4] corresponds to a gate interface width that overlaps the depression width [12, Fig. 4] and is less than the depression width [12, Fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Shibata et al. into the teachings of Kitahara to include an adjusted well depression having a depression width measured along a lateral direction across opposing edges of a concave surface of the adjusted well depression. Wherein the concave surface is continuously concave between the complementary wells; wherein the gate portion corresponds to a gate interface width that overlaps the depression width and is less than the depression width, for the purpose of reducing parasitic capacitance and noise, increasing density, and enhancing performance, efficiency and functionality. See also, MPEP 2144.04(IV)(A) Changes in Size/Proportion, MPEP 2144.04(IV)(B) Changes in Shape, and MPEP 2144.04 (VI)(C) Rearrangement of Parts.
Regarding claim 2, Kitahara and Shibata et al. teach the method of claim 1.
Kitahara further teaches:
the patterned mask layer [81, paragraph [0038], Fig. 2(b)] is formed with an opening [34, 35, Fig. 2(b)] therein that exposes a top portion of the semiconductor device, wherein the opening [34, 35] has an opening width that (1) corresponds to the depression width and (2) is greater than the gate interface width; and
the deep well [150] is formed having (1) peripheral portions having a first depth [130d] and below masked portions of the patterned mask layer [81] and (2) a second depth [150d] below the opening [34, 35], wherein the second depth is greater than the first depth and corresponds to the adjusted well depression of the deep well [150], wherein the first and second depths are measured along a vertical direction from a top surface of the semiconductor substrate [1] to the corresponding portions of the deep well [150].
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Regarding claim 3, Kitahara and Shibata et al. teach the method of claim 2.
Kitahara further teaches:
the gate portion is formed having a peripheral edge; and
the adjusted well depression of the deep well [150, Fig. 5] extends for an adjusted separation distance along the lateral direction from the peripheral edge of the gate portion, wherein the adjusted separation distance is equal to or greater than the second depth.
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Regarding claim 4, Kitahara and Shibata et al. teach the method of claim 3.
Kitahara further teaches:
wherein the adjusted well depression maintains the second depth across the adjusted separation distance below and adjacent to the peripheral edge for reducing or eliminating zones between the gate portion and the deep well [150, Fig. 5] that are at risk of punch-through failures.
Regarding claim 5, Kitahara and Shibata et al. teach the method of claim 2.
Kitahara further teaches:
wherein forming the deep well [150, paragraph [0068]] includes implanting dopants corresponding to the second polarity type [N-type] through the patterned mask layer [81] instead of implanting the dopants directly onto the semiconductor substrate [1] before forming the patterned mask layer [81].
Regarding claim 6, Kitahara and Shibata et al. teach the method of claim 2.
Kitahara further teaches:
forming an oxide layer [83, paragraph [0043], Fig. 3(a)] over the semiconductor substrate [1] and in the opening [34, 35, Fig. 2(b)] of the patterned mask layer [81, Fig. 2(b)], the oxide layer [83] having a width that matches the depression width [see MPEP 2144.04 (IV)(A)] and greater than the gate interface width, wherein the oxide layer [83] corresponds to a gate oxide [38 “gate insulating film”, paragraph [0031], Fig. 5] for the gate portion.
[MPEP 2144.04 (IV)(A) Changes in Size/Proportion]
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Regarding claim 7, Kitahara and Shibata et al. teach the method of claim 2.
Kitahara further teaches:
wherein forming the deep well [150, paragraph [0045], Fig. 5] includes implanting dopants corresponding to the second polarity type [N-type] through the patterned mask layer [81, paragraph [0081], Fig. 2(a)-5] before forming the oxide layer [83, Fig. 3(a)] [see MPEP 2144.04 (IV)(C)].
[MPEP 2144.04 (IV)(C) Changes in Sequence of Adding Ingredients]
Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959) (Prior art reference disclosing a process of making a laminated sheet wherein a base sheet is first coated with a metallic film and thereafter impregnated with a thermosetting material was held to render prima facie obvious claims directed to a process of making a laminated sheet by reversing the order of the prior art process steps.). See also In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930) (Selection of any order of mixing ingredients is prima facie obvious.).
Regarding claim 8, Kitahara and Shibata et al. teach the method of claim 1.
Kitahara further teaches:
wherein forming the complementary wells [140, 110] includes forming an isolated well [130, 120] by separating a portion of the semiconductor substrate [1] from a remaining portion thereof using a combination of the complementary wells [140, 110] and the deep well [150].
Regarding claim 9, Kitahara and Shibata et al. teach the method of claim 8.
Kitahara further teaches:
wherein the corresponding semiconductor device is a Field-Effect Transistor (FET) with a triple well (TW) structure that includes the deep well [150, paragraph [0063], Fig. 5] and the isolated well [130, 120, Fig. 5] of different polarity types [P-type/N-type].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kitahara (US 20040159893 A1), in view of Shibata et al. (US 7084465 B2) as applied to claim 1 above, and further in view of Kung et al. (US 10686047 B2).
Regarding claim 10, Kitahara and Shibata et al. teach the method of claim 1.
Kitahara and Shibata et al. do not teach:
wherein forming the complementary wells includes forming implant portions that connect the complementary wells to peripheral portions of the deep well, wherein a combination of the complementary wells and the implant portions have a depth that is less than a maximum depth associated with the adjusted well depression of the deep well.
Kung et al. teaches:
wherein forming the complementary wells [41 “fourth well regions”, Col. 8, Line 39, Fig. 5] includes forming implant portions [38 “third well regions”, Col. 5, Line 7, Fig. 5] that connect the complementary wells [41] to peripheral portions of the deep well [39, Col. 8, Line 30, Fig. 5], wherein a combination of the complementary wells [41] and the implant portions [38] have a depth that is less than a maximum depth associated with the adjusted well depression of the deep well [39].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the inventions to incorporate the teachings of Kung et al. into the teachings of Kitahara and Shibata et al. to include wherein forming the complementary wells includes forming implant portions that connect the complementary wells to peripheral portions of the deep well, wherein a combination of the complementary wells and the implant portions have a depth that is less than a maximum depth associated with the adjusted well depression of the deep well, for the purpose of improving electrical connection strength between complementary wells and the adjusted bottom well. Also, variations in depth of implant portions can reduce connection resistance and reduce susceptibility of leakage.
Response to Arguments
Applicant's arguments filed December 2, 2025 have been fully considered but they are not persuasive. Applicant argues on page 2, Section: A. Response to the Section 103 Rejection of Claims 1-9 (Kitahara, Shibata), in remarks filed December 2, 2025 that the current prior art of record does not teach the amendments to independent claim 1. Examiner disagrees with Applicant due to new considerations of previously cited primary reference Kitahara (US 20040159893 A1), and new considerations of previously cited secondary reference Shibata et al. (US 7084465 B2).
Applicant argues on page 2, Section: B. Response to the Section 103 Rejection of Claim 10 (Kitahara, Shibata, Kung), in remarks filed December 2, 2025 that claim 10 depends on independent claim 1 and due to the amendments to independent claim 1, claim 10 should also be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 2, Section: C. Dependent Claims, (Although Section “C” is not labelled in remarks, due to the presence of a Section “D” on page 3, Examiner assumes “Dependent Claims” is the title for a Section “C”) in remarks filed December 2, 2025 that due to the amendments to independent claim 1, all rejected dependent claims are now in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 3, Section: D. Rejoinder, in remarks filed December 2, 2025 that due to the amendments to independent claim 1, currently withdrawn claims 11-20 should be rejoined and put in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
In summary, the amendments to independent claim 1 can be overcome by new considerations of previously cited primary reference Kitahara (US 20040159893 A1), and new considerations of previously cited secondary reference Shibata et al. (US 7084465 B2). All claims directly or indirectly dependent on independent claim 1 are also rejected for at least the reasons mentioned above. Claims 11-20 are not in condition for allowance and will not be rejoined.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 02/19/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815