DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 09/09/2026 Amendment.
Claims 1-23 are pending. Claims 18-20 have been withdrawn. Claims 1-17, 21-23 are examined.
Claim Rejections - 35 USC § 112
Claims 1-17, 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a subsequent read of the second memory cell returns the second distribution based on the mark without reprogramming the second memory cell” on lines 13-15. It is not clear to Examiner what this mean. For purpose of examination, Examiner interprets it as -- a subsequent read of the second memory cell returns the second memory cell to the second distribution based on the mark without reprogramming the second memory cell--.
Claim 11 recites similar limitation “a subsequent read of the second memory cell returns the second distribution based on the mark without reprogramming the second memory cell” on lines 10-12. Same rejection and interpretation are applied as in claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-13, 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,164,626 to Di Vincenzo et al. (hereafter Di Vincenzo) in view of US 5,815,439 to Korsh et al. (hereafter Korsh).
Regarding independent claim 1, Di Vincenzo teaches a memory device comprising:
a memory array, the memory array comprising a set of memory cells (FIG. 11: memory array 1120); and
a memory controller configured to read data from the memory array (FIG. 11: memory controller 1140), the memory controller configured to:
sense a first distribution of the set of memory cells (FIG. 8B: applying read voltage VDM1 and sensing if memory cells corresponding to data point 802 snapped),
detect a missing cell in the first distribution (read voltage VDM1 is adjusted according to pre-determined number of cells in the given logic state, i.e. with missing cell in the first distribution, see 21:45-53),
increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution (FIGS. 8D-8E: applying read voltage VDM2 to the missing memory cells corresponding to data point 804),
implicitly detect that a second memory cell in a second distribution was read while sensing the first distribution (FIGS. 8D: sensing memory cells corresponding to data points 804 and 808, wherein memory cell corresponding to data point 808 changing logic from 0 to 1 is detected by access circuit for reprogramming purpose at a later time with read voltage VDM3, see 17:18-32), and
FIGS. 8E-8F: applying read voltage VDM3 to memory cell corresponding to data point 808, the data point 808 returns to original state “0” without programming. Data point 808 was originally having state “0” as in FIG. 8B and is returning to state “0” as in FIG. 8F).
Di Vincenzo teaches that the second memory cell is subsequently read and returned to the original distribution (i.e. restore) instead of masked and marked.
Korsh teaches a method for detecting whether a memory cell VT has drifted undesirably out of range, a restore cycle condition is established and conditional status flag is set (see 8:19-45). The restore cycle operation may be immediately performed on the memory cell, or at a later time by storing address and the type of restore required in registers and address buffer, i.e. mask and mark (see 14:15-26). It is seen that if the restore cycle operation is performed at a later time, the original state of the memory cell VT is preserved for the time being.
Since Di Vincenzo and Korsh are both from the same field of endeavor, the purpose disclosed by Korsh would have been recognized in the pertinent art of Di Vincenzo.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that it is choice to immediately perform a restore cycle operation on an out-of-range memory cell, or mask and mark then reprogram it at a later preferred time as suggested by Korsch.
Regarding dependent claim 2, Di Vincenzo teaches wherein sensing a first distribution comprises applying a positive read voltage to the set of memory cells and sensing a subset of the set of memory cells that conduct (FIGS. 7-9: applying positive voltage of VDM1 to memory cell(s) corresponding to range 810).
Regarding dependent claim 3, Di Vincenzo teaches wherein the set of memory cells comprises single-level cell memory cells (see FIG. 4 and 7:55-63).
Regarding dependent claim 4, Di Vincenzo teaches wherein the first distribution comprises either a binary one state or binary zero state (FIG. 8B: logic 1).
Regarding dependent claim 10, Di Vincenzo teaches wherein the set of memory cells comprise chalcogenide-based memory cells (see 3:11-18).
Regarding independent claim 11, Di Vincenzo teaches a method comprising:
sense a first distribution of the set of memory cells (FIG. 8B: applying read voltage VDM1 and sensing if memory cells corresponding to data point 802 snapped),
detect a missing cell in the first distribution (read voltage VDM1 is adjusted according to pre-determined number of cells in the given logic state, i.e. with missing cell in the first distribution, see 21:45-53),
increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution (FIGS. 8D-8E: applying read voltage VDM2 to the missing memory cells corresponding to data point 804),
implicitly detect that a second memory cell in a second distribution was read while sensing the first distribution (FIGS. 8D: sensing memory cells corresponding to data points 804 and 808, wherein memory cell corresponding to data point 808 changing logic from 0 to 1 is detected by access circuit for reprogramming purpose at a later time with read voltage VDM3, see 17:18-32), and
FIGS. 8E-8F: applying read voltage VDM3 to memory cell corresponding to data point 808, the data point 808 returns to original state “0” without programming. Data point 808 was originally having state “0” as in FIG. 8B and is returning to state “0” as in FIG. 8F).
Di Vincenzo teaches that the second memory cell is subsequently read and returned to the original distribution (i.e. restore) instead of masked and marked.
Korsh teaches a method for detecting whether a memory cell VT has drifted undesirably out of range, a restore cycle condition is established and conditional status flag is set (see 8:19-45). The restore cycle operation may be immediately performed on the memory cell, or at a later time by storing address and the type of restore required in registers and address buffer, i.e. mask and mark (see 14:15-26). It is seen that if the restore cycle operation is performed at a later time, the original state of the memory cell VT is preserved for the time being.
Since Di Vincenzo and Korsh are both from the same field of endeavor, the purpose disclosed by Korsh would have been recognized in the pertinent art of Di Vincenzo.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that it is a choice to immediately perform a subsequent read on an out-of-range memory cell to return it to the original distribution (i.e. restore), or mask and mark then restore it at a later preferred time as suggested by Korsch.
Regarding dependent claims 12-13, 21 and 23, see rejections applied to claims 2-4 and 10 above.
Claims 5-6, 8, 14-15, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Di Vincenzo in view of Korsch in view of US 9,558,823 to Khwa et al. (hereafter Khwa).
Di Vincenzo and Korsh teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 5, Khwa teaches a memory device comprising multi-level cell (MLC) memory cells (see 8-27). FIG. 9 shows drifts and overlapping regions between resistance ranges of the MLC memory cells cause errors 920 and 930. A drift recovery of a drifted resistance range described in FIGS. 11A-11F is done by applying recovery pulse of FIG. 12B. The recovery pulse comprises first pulse shape 1210 and second pulse shape 1240, similar to VDM1 and VDM2 of Di Vincenzo.
Since Di Vincenzo, Korsh and Khwa are all from the same field of endeavor, the purpose disclosed by Di Vincenzo and Korsh would have been recognized in the pertinent art of Khwa.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the method taught in Di Vincenzo and Korsh to the MLC memory cells of Khwa in order to correct errors of each of overlapping regions of the MLC memory cells of Khwa causing by resistance drifting.
Regarding dependent claim 6, Di Vincenzo and Khwa suggest the memory controller further configured to: sense a second distribution of the set of memory cells; detect a second missing cell in the second distribution; and increase a voltage on the second missing cell causing the second missing cell to be read as part of the second distribution (each of the overlapping regions causing errors 920 and 930 in FIG. 9 of Khwa would require same steps recited in claim 1 taught by Di Vinzenzo).
Regarding dependent claim 8, Khwa teaches wherein the first distribution comprises a set state, and second distribution comprises a reset state (FIG. 9: the first two resistance ranges may be considered as set states and the last two resistance ranges as reset states).
Regarding dependent claims 14-15, 22, see rejections applied to claims 5-6, 8 above.
Claims 7, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Di Vincenzo in view of Korsh in view of Khwa in view of US 10,825,514 to Kim et al. (hereafter Kim).
Di Vincenzo, Korsch and Khwa teach, as applied in prior rejection of claim 6, all claimed subject matter except further limitations set forth on the following claim(s).
Regarding dependent claim 7, Kim teaches, in FIG. 2, memory device comprising multi-level cell (MLC) memory cells comprising positive set state p-SET, negative set state n-SET, positive reset state p-RESET and negative reset state n-RESET. The negative set state n-SET is programmed with negative set pulse of FIG. 7 and considered intermediate resistance between positive set state p-SET and positive reset state p-RESET programmed by positive set and reset pulses of FIG. 6 (also see 6:12-19). FIG. 5 shows drifts of resistance ranges of the states. It is understood that the p-SET is read with positive read voltage, n-SET is read with negative read voltage.
Since Di Vincenzo, Korsh, Khwa and Kim are all from the same field of endeavor, the purpose disclosed by Di Vincenzo, Korsh, Khwa would have been recognized in the pertinent art of Kim.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply the method taught in Di Vincenzo and Korsh to the MLC memory cells of Kim for the purpose of recovery between drifted resistance ranges of the MLC memory cells.
Regarding dependent claim 16, see rejection applied to claim 7 above.
Claims 9, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Di Vincenzo in view of Korsh in view of PGPub. 2015/0317203 to Zhou (hereafter Zhou).
Di Vincenzo and Korsh teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 9, Zhou teaches a memory device comprising an encoder/decoder (FIG. 1: encoder/decoder 110) for encoding/decoding a codeword, wherein the codeword comprises binary balanced error-correcting codes (see FIG. 5 and corresponding description).
Since Di Vincenzo, Korsh and Zhou are all from the same field of endeavor, the purpose disclosed by Zhou would have been recognized in the pertinent art of Di Vincenzo and Korsh.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to employ the encoder/decoder of Zhou as the ECC 1142 in FIG. 11 of Di Vincenzo in order to easily set the reference levels of VDM1, VDM2 without significant increase in latency and energy cost of reading data (see FIG. 3 and paragraph [0009]).
Regarding dependent claim 17, see rejections applied to claim 9 above.
Response to Arguments
Applicant's arguments filed 02/19/2025 have been fully considered.
Claim Rejections - 35 USC § 112
Applicant’s amendment to independent claims 1 and 11 has introduced new claim rejections under 35 USC § 112 as stated above.
Claim Rejections - 35 USC § 103
Applicant argues:
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Examiner respectfully disagrees with Applicant’s argument. Claim 1 calls for “a subsequent read of the second memory cell returns the second memory cell to the second distribution … without reprogramming the second memory cell”, which is understood as restoring the memory cell to the second distribution using a read voltage. Di Vincenzo describes, in col. 17 ll. 33-40, that VDM1, VDM2 and VDM3 as read voltages, rather than programming voltages. Di Vincenzo also describes, in col. 13 ll. 25-32, the memory cells are read using read sequence comprising VDM1, VDM2 and VDM3. As the result, the application of VDM3 to data point 808 in FIGS 8E-8F of Di Vincenzo cannot be considered an intended reprogram operation, as Applicant alleges.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 9, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
