DETAILED ACTION
Claims 1-19 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 1/14/2026.
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Withdrawn objections and rejections
The specification objection has been withdrawn.
New and Maintained Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-10, 12, and 15-19 are rejected under 35 U.S.C. 102(a)(1 & 2) as being anticipated by Henry et al. (U.S. 2015/0067666).
As per claim 1:
Henry disclosed a processing device comprising:
a first processor core comprising a register to indicate a hardware capability of the processing device to propagate a microcode update from the first processor core to a second processor core (Henry: Figures 1-2, 24, and 26 elements 102-103, 108, 116, 222-226, 2439, 2499, and 2626, paragraphs 39-40, 45, 47, 53, 280-281, 284-287, and 314)(The uncore (i.e. first core) includes core sync registers that indicate a hardware capability to propagate a microcode update from the uncore memory elements to the core PRAM and PATCH CAM.); and
the second processor core (Henry: Figure 24 element 102, paragraph 280).
As per claim 2:
Henry disclosed the processing device of claim 1, wherein the register comprises a field to indicate a type of the uniform microcode update (Henry: Figures 2 and 26 elements 226 and 2624, paragraphs 53 and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory.).
As per claim 4:
Henry disclosed the processing device of claim 1, wherein the register comprises a field to indicate that configuration by a basic input/output system (BIOS) is specified to enable the microcode update to take place (Henry: Figures 2 and 26 elements 226 and 2624, paragraphs 53 and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Sync code 24 enables the update from the uncore to the core to take place.).
As per claim 5:
Henry disclosed the processing device of claim 1, wherein the register comprises a field to indicate that configuration by a basic input/output system (BIOS) has been completed (Henry: Figures 2 and 26 elements 226 and 2628, paragraphs 53, 284, and 313-315)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Sync code 25 indicates that the update from the uncore to the core to has completed. The process is completed in response to system software, such as BIOS, running.).
As per claim 6:
Henry disclosed The processing device of claim 1, wherein the register is accessible to a basic input/output system (BIOS) or an operating system but not an user-application program (Henry: Figures 2 and 26 elements 226 and 2628, paragraphs 53, 284, and 313-315)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Sync code 25 indicates that the update from the uncore to the core to has completed. The process is completed in response to system software, such as BIOS or OS, running and not user-level programs.).
As per claim 7:
Henry disclosed the processing device of claim 1, comprising an additional register to indicate a status of the microcode update (Henry: Figures 1-2 and 26 elements 106, 108A-N, 226, 244, and 2624, paragraphs 47-49, 52-53, and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Multiple uncore sync registers are used to indicate the status of the microcode update. Additionally, a status register tracks wakeup events.).
As per claim 8:
Henry disclosed the processing device of claim 7, wherein the additional register comprises a field to indicate whether a most recent attempt to update the microcode resulted in a partial update (Henry: Figures 1-2 and 26 elements 106, 108A-N, 226, 244, and 2624-2628, paragraphs 47-49, 52-53, and 313-315)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Multiple uncore sync registers are used to indicate the status of the microcode update. The sync condition of ‘25” being written to a subset of core sync registers indicates that the update is pending and partial.).
As per claim 9:
Henry disclosed the processing device of claim 7, wherein the additional register comprises a field to indicate whether an authentication failure occurred on some portion of the microcode update after different portion of the microcode update had been committed (Henry: Figures 1-3 elements 106, 108A-N, 226, 244, 248, and 306, paragraphs 47-49, 52-53, and 65)(A status register tracks wakeup events. The status register includes error codes for when deadlock occurs.).
As per claim 10:
Henry disclosed the processing device of claim 1, wherein the first processor core comprises another register to indicate a presence of the register to indicate the hardware capability to perform the microcode update (Henry: Figures 1-2, 24, and 26 elements 102-103, 108, 222-226, 2439, 2499, and 2626, paragraphs 39-40, 45, 47, 53, and 280-281, 284-287, and 314)(The uncore (i.e. first core) includes core sync registers that indicate a hardware capability to propagate a microcode update from the uncore memory elements to the core PRAM and PATCH CAM. A second core sync register reads upon the “another register.”).
As per claim 12:
Henry disclosed one or more tangible, non-transitory, machine-readable media comprising instructions that, when executed (Henry: Figure 26 element 2602, paragraph 301), cause operations comprising:
reading a first field of a first register of a processing core to determine that the processing core supports a uniform microcode update of a defined scope (Henry: Figures 1-2 and 26 elements 108A-N, 226 and 2624, paragraphs 45, 53, and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Reading a sync code 24 enables the update from the uncore to the core to take place, which supports propagating a uniform microcode update from the uncore to the cores.); and
initiating the uniform microcode update to take place according to the defined scope based on the first field of the first register (Henry: Figures 1-2 and 26 elements 108A-N, 226 and 2624, paragraphs 45, 53, and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Reading a sync code 24 enables the update from the uncore to the core to take place, which supports propagating a uniform microcode update from the uncore to the cores. The uniform microcode update occurs after all sync codes are 24 for each core.).
As per claim 15:
Henry disclosed the one or more machine-readable media of claim 12, wherein the instructions, when executed, cause operations comprising:
reading a second field of the first register to determine whether the processing core is specified to be configured before a microcode update is to occur (Henry: Figures 2 and 26 elements 212-214 and 2624, paragraphs 51-53 and 313-314)(The sleep/sel wake fields are read to determine if and how cores are to be woken up for wakeup events.); and
in response to determining that the processing core is specified to be configured before the microcode update is to occur, reading a third field of the first register to determine whether the processing core is configured (Henry: Figures 2 and 26 elements 222 and 2624, paragraphs 51-53 and 313-314)(The S bit being set indicates a sync is configured for processing.).
As per claim 16:
Henry disclosed the one or more machine-readable media of claim 12, wherein the instructions, when executed, cause the one or more processors to perform operations comprising:
in response to determining that the processing core supports the uniform microcode update of the defined scope, reading a second field of the first register to determine the defined scope (Henry: Figures 2 and 26 elements 226 and 2624, paragraphs 53 and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory.).
As per claim 17:
Henry disclosed the one or more machine-readable media of claim 12, wherein the instructions comprise a basic input/output system (BIOS) or an operating system (OS) of the processing system (Henry: Figures 2 and 26 elements 226 and 2628, paragraphs 53, 284, and 313-315)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Sync code 25 indicates that the update from the uncore to the core to has completed. The process is completed in response to system software, such as BIOS or OS, running and not user-level programs.).
As per claim 18:
Henry disclosed the one or more machine-readable media of claim 12, wherein the instructions, when executed, cause operations comprising initiating the uniform microcode update by executing a write model specific register instruction (WRMSR) to a defined register that causes a microcode update in one of the one or more cores (Henry: Figures 1-2 and 26 elements 108A-N, 202, 2602, and 2608, paragraphs 45, 47, 52-53, 301, and 305)(The WRMSR instruction causes updates the sync register.)
As per claim 19:
Henry disclosed the one or more machine-readable media of claim 18, wherein the instructions, when executed, cause operations comprising reading a first field of a second register of the processing core to determine whether the uniform microcode update completed successfully (Henry: Figures 1-2 and 26 elements 108A-N, 226, and 2628, paragraphs 53, 284, and 313-315)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Sync code 25 indicates that the update from the uncore to the core to has completed. The patch core step is performed after detecting all core updates by seeing the sync code 25 is in all core sync registers (i.e. second register).).
New and Maintained Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Henry et al. (U.S. 2015/0067666), in view of Official Notice.
As per claim 3:
Henry disclosed the processing device of claim 2, wherein the type of the microcode update comprises at least one of a package scope or a platform scope (Henry: Figures 1-2 and 26 elements 102A-N, 103, 226 and 2624, paragraphs 40, 53, and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Official notice is given that processor cores can be within a same system package for the advantage of reduced communication costs. Thus, it would have been obvious to one of ordinary skill in the art to implement the cores and uncore on the same package. This allows for the microcode update to be performed on a package scope.).
As per claim 11:
Henry disclosed the processing device of claim 1, wherein the first processor core and the second processor core are disposed in a first package and communicatively coupled on a same platform to a third processor core and a fourth processor core of a second package, wherein the register is to indicate that the hardware capability is to perform the uniform microcode update by propagating the microcode update from the first package to the second package (Henry: Figures 1-2 and 26 elements 102A-N, 103, 226 and 2624, paragraphs 40, 53, and 313-314)(The sync condition field indicates a uniform microcode update to each of the processor cores from the uncore memory. Official notice is given that processor cores can be within multiple system packages for the advantage of reduced communication costs. Thus, it would have been obvious to one of ordinary skill in the art to implement a subset of the cores and uncore in a first package and the remaining cores in a second package. This allows for the microcode update to be performed between packages.).
Response to Arguments
The arguments presented by Applicant in the response, received on 1/14/2026 are not considered persuasive.
Applicant argues regarding claims 1 and 12:
“For example, Henry does not describe "a first processor core comprising a register to indicate a hardware capability of the processing device to propagate a microcode update from the first processor core to a second processor core." The Office Action cites the "uncore" as being the first core. A PHOSITA would not consider an uncore to be a processor core and to prove that, conveniently, neither does Henry. The "uncore portion 103 coupled to the cores 102 and that it is distinct from the cores 102. The uncore 103 includes a control unit 104, fuses 114, a private random access memory (PRAM) 116, and a shared cache memory 119, for example, a level-2 (L2) and/or level-3 (L3) cache memory, shared by the cores 102." That is one reason Henry does not describe what is claimed. The Office Action also cites elements 222-226 and none of those appear to be relevant. For example, bit 222 is used to put a core to sleep and then wake when a sync condition occurs. 224 is a C bit field. 226 is a sync condition or C-state field. None of those fields appear to relate to the cited PATCH CAM or PRAM. Note that PRAM has nothing to do with updating of capabilities (it stores data) and the PATCH CAM is loaded with "CAM data 2508... [that] includes one or more entries each of which comprises a pair of microcode fetch addresses. The first address is of the microcode instruction to be patched and is the content matched by the fetch address." These bits and fields are not describe a capability, nor are they describing anything going from core to core. Henry always requires the uncore and its additional overhead to ucode patch.”
This argument is not found to be persuasive for the following reason. The uncore broadly reads upon the claimed processor core that comprises a register. The synchronization registers include information providing data for indicating a hardware capability of the uncore to transfer microcode updates from the uncore PRAM to the coupled processor cores. Thus, reading upon the claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACOB PETRANEK/Primary Examiner, Art Unit 2183