DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority The present application, 17898722, filed 08/30/2022 claims foreign priority to JP2021-203159, filed 12/15/2021. Information Disclosure Statement The information disclosure statement (IDS) submitted on 08/30/2022 and 10/27/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claims 2 and 4-6 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected. A. In claim 2 line 5, “the operation result” should read “the invalid operation result” instead for consistency of claim terminologies and better clarity. Claim 4 recites the same limitations in lines 10-11 and is objected to for the same reason. Claims 5-6 inherit the same deficiency as claim 4 by reason of dependence. Claim Interpretation The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B. See MPEP 2111.04 for more information. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim s 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “the sub arithmetic circuit” in line 8; “the subregion” in lines 9, 10 and 13; and “ the register” in line 12. There is insufficient antecedent basis for these limitations in the claim. It is unclear which specific sub arithmetic circuit, subregion and register from the plurality of sub arithmetic circuits; plurality of subregions; and plurality of registers these are meant to refer to respectively . For purposes of examination, these are interpreted as a corresponding sub arithmetic circuit in line 8; a subregion in line 9; and a register in claim 12. Claim 7 recites the same limitations and is rejected for the same reason . Claims 2-3 and 6 recite “the subregion” in lines 4, 3 and 10 respectively and are rejected for the same reason. Claim 4 recites “the register” in line 5 and is rejected for the same reason. Claims 2-6 inherit the same deficiency as claim 1 by reason of dependence. Claim 3 inherit the same deficiency as claim 2 by reason of dependence. Claims 5-6 inherit the same deficiency as claim 4 by reason of dependence. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1 and 7 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Gove et al. (US 20120216011 A1), hereinafter Gove. Regarding claim 1, Gove teaches an arithmetic processing device comprising: an arithmetic circuit capable of operating as a plurality of sub arithmetic circuits according to a bit width of data to be calculated (Gove Figs. 2-5 and paragraph [0011] “The vector unit may include a plurality of lanes and a plurality of computing units to operate on the data elements of the source vectors”; arithmetic circuit – vector unit; plurality of sub arithmetic circuits - plurality of computing units; paragraph [0035] “computing unit 310 may operate on a first portion of source vector registers 330 and 331, computing unit 320 may operate on a second portion of registers 330 and 331”; paragraph [0047]) ; a plurality of registers each of which includes a plurality of subregions that corresponds to the plurality of sub arithmetic circuits, respectively (Gove Figs. 2 , 3 and 5; plurality of registers – vector register file including the source and target vector register files; paragraph [0041] “Source vector register 530 is shown containing the element pattern "8-22-4-2-X-X-X-X", and source vector register 535 is shown containing the element pattern "1-2-3-5-X-X-X-X"; plurality of subregions – regions storing each element; paragraph [0011] “one or more source vectors may include a plurality of data elements, and each data element may be operated on within a lane of a vector unit” ) ; a mask circuit that masks, when an operation that uses a part of the plurality of sub arithmetic circuits is executed, storage of invalid operation result data output from the sub arithmetic circuit that does not receive data to be subject to the operation in the subregion (Gove Figs. 2 and 5 and paragraph [0033] “Only results computed by vector unit 216 for selected or occupied elements from registers 208 and 210 may be transferred through mask 218 to register 204”; paragraph [0043] “A similar circuit or function may be implemented in mask 550 to filter the values that are output from vector unit 510 before they are written to target vector register 520”; mask circuit – circuit implementing mask 218/550) ; and a data replacement circuit that replaces data, output from the subregion in which the storage is masked, with a zero-value to output the zero-value to the arithmetic circuit when the operation that uses the data retained in the register that includes the subregion in which the storage is masked (Gove Figs. 2 and 5 and paragraph [0032] “Any deselected elements may be converted by mask 214 to a do not care value, such as zero, or may be blocked … Mask 214 may also contain AND logic gates or other circuitry to either pass through, modify, or block elements of the source vector registers”; paragraph [0043] “mask 540 may operate by performing a logical AND operation on the elements of source vector registers 530 and 535 before the data elements of registers 530 and 535 are passed as inputs to vector unit 510. If there is a '1 ' bit in mask 540, then for each source register the result of the AND operation will be the value of the corresponding element in that source register. If there is a '0' bit in mask 540, then the result of the AND operation for the corresponding element will have a '0' value … the deselected data elements in source vector registers 530 and 535 may be set to '0' or another predefined value”; data replacement circuit – mask circuit 214/540) . Regarding claim 7, it is directed to a method practiced by the device of claim 1 . All steps performed by the method of claim 7 would be practiced by device of claim 1 . Claim 1 analysis applies equally to claim 7 . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Gove as applied to claim 1 above, and further in view of Masanori et al. (JP 2008134926 A), hereinafter Masanori. Regarding claim 2, Gove teaches all the limitations of claim 1 as stated above. Gove does not explicitly teach wherein each of the plurality of subregions of the registers operates in synchronization with a clock, and the mask circuit stops a supply of the clock to the subregion in which the storage of the operation result data is masked . However, on the same field of endeavor, Masanori discloses each of a plurality of subregions of registers operating in synchronization with a clock, and a mask circuit stopping a supply of the clock to the subregion to prevent storage of invalid data (Masanori page 1 bottom paragraph to page 2; page 5 middle “when the bit width designation signal BTB indicates that the upper 8 bits of the data DO to D15 for the reception register 10 are invalid, even if the input data to the synchronization register 30 Even if there is a change in ROB to RD15, the synchronization clock CLK2b is not supplied to the synchronization register 30. Therefore, it is possible to prevent the synchronization register 30 from taking in the invalid upper bit input data ROB to RD15 and consuming power wastefully”; page 8 middle “If any of the upper bit string, middle bit string, and lower bit string becomes invalid, the synchronization clock supply to the synchronization register that handles the invalid bit string can be forcibly cut off”). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gove and generalize the teaching of Masanori by synchronizing each of the plurality of subregions of the registers with a clock, and configure the mask circuit to stop a supply of the clock to the subregion in which the storage of the operation result data is masked to prevent storage of invalid data and in order to avoid unnecessary switching operation of the target vector register and reduce power consumption (Masanori page 2 top and page 5 middle). Therefore, the combination of Gove as modified in view of Masanori teaches wherein each of the plurality of subregions of the registers operates in synchronization with a clock, and the mask circuit stops a supply of the clock to the subregion in which the storage of the operation result data is masked. Regarding claim 3, Gove as modified in view of Masanori teaches all the limitations of claim 2 as stated above. Gove does not explicitly teach further comprising: a clock stop circuit that stops the supply of the clock to the subregion that retains the data to be replaced with the zero value by the data replacement circuit . However, on the same field of endeavor, Masanori discloses a clock stop circuit that stops a supply of a clock to a subregion of a register that retains data to be replaced (Masanori page 2 bottom paragraph and page 3 bottom paragraph “Various configurations are conceivable for the configuration of the clock gating control circuit 40. The clock gating control circuit 40 according to the present embodiment includes a latch 41 and an AND gate 42 as shown … The clock gating control circuit 50 is a circuit having the same configuration as that of the clock gating control circuit 40”; clock stop circuit – clock gating control circuit). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Gove and generalize the teaching of Masanori including a clock gating control circuit to stop the supply of the clock to the subregion that retains the data to be replaced with the zero value by the data replacement circuit in order reduce power consumption (Masanori page 2 top and page 5 middle). Therefore, the combination of Gove as modified in view of Masanori teaches further comprising: a clock stop circuit that stops the supply of the clock to the subregion that retains the data to be replaced with the zero value by the data replacement circuit. Allowable Subject Matter Claim s 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejections discussed above. The following is a statement of reasons for the indication of allowable subject matter: Claim 4 is directed to an arithmetic processing device comprising, among other things, a decoder that decodes an instruction and outputs an instruction code of the decoded instruction, a logical register number included in the decoded instruction, a physical register number that indicates the register to be used in association with the logical register number, and a bit width of data to be used to execute the instruction; and a renaming table that retains the physical register number and the bit width in association with the logical register number, wherein the mask circuit determines whether or not to mask the storage of the operation result data in each of the subregions on a basis of the bit width output from the decoder together with the physical register number, and the data replacement circuit determines whether or not to replace the data output from each of the subregions with the zero value on a basis of the bit width read from the renaming table together with the physical register number . Gove is the closest prior art found. Gove teaches a device comprising a vector unit configured to execute single instruction multiple-data (SIMD) instructions comprising a plurality of computing units; associated registers comprising a plurality of subregions; a write mask circuit configured to mask storage of invalid output result from the computing units to a target vector register; and a read mask circuit configured to deselect invalid operands provided to corresponding computing units by converting the values to zero . Ta kayama et al. (US 6802017 B1) discloses a processor comprising a 32-bit ALU capable of processing 32-bit, 16-bit or 8-bit data sizes comprising four of 8-bit ALUs; a register file comprising a plurality of register each configured to store data corresponding to the 8-bit ALUs; drivers 12a-12d configured t o mask invalid operation result data from the 8-bit ALUs for storage to corresponding subregions of a register in the register file; and drivers 5a5d and 6a-6d for providing data from subregions of input registers to the 8-bit ALUs such that only valid data are read from the register by enabling all drivers if 32-bit data, read out; enabling half of the drivers if 16-bit data, read out and enabling one driver if 8-bit data. Further, Takayama discloses the processor further comprising a decoder for decoding the individual instructions given from an instruction register. Takayama is cited in the IDS submitted on 10/27/2025 . However, none of the prior art references cited taken, alone or in combination, teaches the specific combination of claim 4. In particular, none of the prior art references cited explicitly teach or suggest a decoder that decodes an instruction and outputs an instruction code of the decoded instruction, a logical register number included in the decoded instruction, a physical register number that indicates the register to be used in association with the logical register number, and a bit width of data to be used to execute the instruction; and a renaming table that retains the physical register number and the bit width in association with the logical register number, wherein the mask circuit determines whether or not to mask the storage of the operation result data in each of the subregions on a basis of the bit width output from the decoder together with the physical register number, and the data replacement circuit determines whether or not to replace the data output from each of the subregions with the zero value on a basis of the bit width read from the renaming table together with the physical register number as recited in claim 4. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Colwell et al. ( US 6047369 A) generally related to a device comprising an instruction fetch and decode unit and a register renaming table comprising three columns. The first indicating size of data represented by each entry (row), for example, two bits wide and will indicate either storage of a 32-bit width of data (i.e. eax), a 16-bit width of data (i.e., ax), an 8-bit width of data of the upper byte of the lower word (i.e., ah) and an 8-bit width of data of the lower byte of the lower word (i.e., al) for each of the 12 entries of the RAM array. The third column for each entry representing a pointer to a particular physical register which has been assigned to contain data for the logical register associated with the given entry of the pointer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Carlo Waje whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5767 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:00-6:00 M-F . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT James Trujillo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-3677 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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