DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-7 are pending in this application. Claims 1-2 and 6-7 are currently amended; claims 3-5 are original.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the register” in line 4. There is insufficient antecedent basis for these limitations in the claim. For purposes of examination, this is interpreted as register. Claims 5-6 inherit the same deficiency as claim 4 by reason of dependence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Takayama et al. (US 6802017 B1), hereinafter Takayama. Takayama is cited in the IDS submitted on 10/27/2025.
Regarding claim 1, Takayama teaches an arithmetic processing device comprising:
an arithmetic circuit capable of operating as a plurality of sub arithmetic circuits according to a bit width of data to be calculated (Takayama Fig. 1 and col 2 lines 46-57 “The 32-bit ALU is subdivided into four 8-bit ALUs 1a, 1b, 1c and 1d … A ripple-carry 32-bit ALU is implementable when all of these four 8-bit ALUS 1a through 1d and all of these three gates 11a through 11c are enabled. A 16-bit ALU is implementable when only two 8-bit ALUs 1c and 1d and only one gate 11c are enabled. Also, just one ALU 1d may be enabled”; arithmetic circuit – 32-bit ALU; plurality of sub arithmetic circuits - four 8-bit ALUs 1a, 1b, 1c and 1d);
a plurality of registers each of which includes a plurality of subregions that corresponds to the plurality of sub arithmetic circuits, respectively (Takayama Fig. 1 and col 2 lines 64 to col 3 line 17; The processor further includes a 32-bit register file 2 consisting of eight registers R0 through R7. Each of these registers R0 through R7 includes: data A, B, C and D (DA, DB, DC and DD) sections 2a, 2b, 2c and 2d for retaining 8-bit data each”; plurality of registers - eight registers R0 through R7; plurality of subregions - DA, DB, DC and DD sections);
a mask circuit that masks, with a first operation having a first data width being executed using a part of the plurality of sub arithmetic circuits storage of invalid operation result data from a sub-arithmetic circuit that is not used for the first operation in a corresponding subregion of a destination register for the first operation (Takayama Fig. 1 and col 4 lines 41-49 “The data representing the operation results of the ALUs 1a through 1d is provided to 8-bit drivers 12a, 12b, 12c and 12d for driving the C bus 33, respectively. If 32-bit data should be provided to the C bus 33, then all of these drivers 12a through 12d are enabled. Alternatively, if 16-bit data should be provided to the C bus 33, then only the drivers 12c and 12d are enabled. And if 8-bit data should be provided to the C bus 33, then just the driver 12d is enabled. The data that will be retained in the register file 2 is provided through the C bus 33”; mask circuit - 8-bit drivers 12a, 12b, 12c and 12d; only 12d is enabled or 12c and 12d are enables when the operation result is 8-bit or 16-bit data respectively; first data width - 8-bit or 16-bit); and
a data replacement circuit configured to, with a second operation having a second data width wider than the first data width is executed using data retained in the destination register after the first operation, replace data, output from the subregion in which the storage is masked, with a zero-value, and to output the zero-value to the arithmetic circuit (Takayama Fig. 1 and col 4 lines 12-26 “The processor further includes a 32-bit extender for extending the size of the data latched in the latches 8a through 8d and providing resultant data to the right-hand-side inputs of the ALUs 1a through 1d, respectively. The 32-bit extender is subdivided into four 8-bit extenders (EA2, EB2, EC2 and ED2) 10a, 10b, 10c and 10d. An extender for extending the size of 8- or 16-bit data into 32 bits is implementable when all of these four 8-bit extenders 10a through 10d are enabled. An extender for extending the size of 8-bit data into 16 bits is implementable when only the two 8-bit extenders 10c and 10d are enabled. If the data to have its size extended is signed, then sign extension is carried out. Conversely, if the data to have its size extended is unsigned, then zero extension is carried out”; col 7 lines 1-16 “8-bit operand data is read out from the DD section 2d of the register Rn, passed through the driver 6d and the LS 8-bit part of the B bus 32 and then latched in the latch 8d. Next, the 8-bit data latched in the latch 8d has its size extended by the extenders 10c and 10d into 16 bits … if the 8-bit data retained in the register Rn is unsigned data, then zero extension is carried out on the high-order 8 bits”; col 7 line 40 to col 8 line 16; col 10 lines 50-55 “If the Rn data is greater in size than the Rm data, then the Rm data, retained in the latches 8a through 8d, has its size extended by the extenders 10a through 10d up to the size of the Rn data and then provided to the right-hand-side inputs of the ALUs 1a through 1d”; data replacement circuit – 32-bit extender; second data width - 16-bit or 32-bit).
Regarding claim 7, it is directed to a method practiced by the device of claim 1. All steps performed by the method of claim 7 would be practiced by device of claim 1. Claim 1 analysis applies equally to claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Takayama as applied to claim 1 above, and further in view of Masanori1 et al. (JP 2008134926 A), hereinafter Masanori.
Regarding claim 2, Takayama teaches all the limitations of claim 1 as stated above.
Takayama does not explicitly teach wherein each of the plurality of subregions of the registers operates in synchronization with a clock, and the mask circuit stops a supply of the clock to the subregion in which the storage of the invalid operation result data is masked.
However, on the same field of endeavor, Masanori discloses each of a plurality of subregions of registers operating in synchronization with a clock, and a mask circuit stopping a supply of the clock to the subregion to prevent storage of invalid data (Masanori page 1 bottom paragraph to page 2; page 5 middle “when the bit width designation signal BTB indicates that the upper 8 bits of the data D0 to D15 for the reception register 10 are invalid, even if the input data to the synchronization register 30 Even if there is a change in ROB to RD15, the synchronization clock CLK2b is not supplied to the synchronization register 30. Therefore, it is possible to prevent the synchronization register 30 from taking in the invalid upper bit input data ROB to RD15 and consuming power wastefully”; page 8 middle “If any of the upper bit string, middle bit string, and lower bit string becomes invalid, the synchronization clock supply to the synchronization register that handles the invalid bit string can be forcibly cut off”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Takayama and generalize the teaching of Masanori by synchronizing each of the plurality of subregions of the registers with a clock, and configure the mask circuit to stop a supply of the clock to the subregion in which the storage of the invalid operation result data is masked to prevent storage of invalid data and in order to avoid unnecessary switching operation of the register and reduce power consumption (Masanori page 2 top and page 5 middle).
Therefore, the combination of Takayama as modified in view of Masanori teaches wherein each of the plurality of subregions of the registers operates in synchronization with a clock, and the mask circuit stops a supply of the clock to the subregion in which the storage of the invalid operation result data is masked.
Regarding claim 3, Takayama as modified in view of Masanori teaches all the limitations of claim 2 as stated above.
Takayama does not explicitly teach further comprising: a clock stop circuit that stops the supply of the clock to the subregion that retains the data to be replaced with the zero value by the data replacement circuit.
However, on the same field of endeavor, Masanori discloses a clock stop circuit that stops a supply of a clock to a subregion of a register that retains data to be replaced (Masanori page 2 bottom paragraph and page 3 bottom paragraph “Various configurations are conceivable for the configuration of the clock gating control circuit 40. The clock gating control circuit 40 according to the present embodiment includes a latch 41 and an AND gate 42 as shown … The clock gating control circuit 50 is a circuit having the same configuration as that of the clock gating control circuit 40”; clock stop circuit – clock gating control circuit).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Takayama and generalize the teaching of Masanori including a clock gating control circuit to stop the supply of the clock to the subregion that retains the data to be replaced with the zero value by the data replacement circuit in order reduce power consumption (Masanori page 2 top and page 5 middle).
Therefore, the combination of Takayama as modified in view of Masanori teaches further comprising: a clock stop circuit that stops the supply of the clock to the subregion that retains the data to be replaced with the zero value by the data replacement circuit.
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejections discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
The reasons for the indication of allowable subject matter are the same reasons provided in the non-final office action submitted on 03/03/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
1 See provided Machine Translation for the claim mapping.
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