DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 12/23/25, which has been entered.
1. REJECTIONS NOT BASED ON PRIOR ART
a. DEFICIENCIES IN THE CLAIMED SUBJECT MATTER
Claim Rejections - 35 USC ' 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-18, and 20-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitations of “the quantity is based on a first counter of a plurality of counters mapped to a plurality of non-overlapping ranges of logical addresses” in lines 10-12. There is insufficient antecedent basis for this limitation in the claim. The Examiner notes “the quantity” could refer to “a quantity of times that a range of logical addresses comprising a logical address of the data has been accessed” or “a quantity of invalid data included in a set of previously selected blocks”. It appears that “the quantity” refers to “a quantity of times that a range of logical addresses comprising a logical address of the data has been accessed”, but this is not clear. Thus, the claim is indefinite as the Examiner is unsure to which “quantity” “the quantity” could refer to but has been construed as noted above. The other independent claims have a similar limitation and similar deficiency, and the dependent claims inherit their deficiencies of their respective independent claim.
2. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 10-13, 16-17, 18, 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 20160011815) in view of Kim (US 20170286008) and Bottei (US 20170052719).
With respect to claim 1, the Klein reference teaches an apparatus, comprising:
one or more memory devices comprising non-volatile memory cells; (see fig. 1, non-volatile solid state memory media 110) and
processing circuitry associated with the one or more memory devices, paragraph 29, where hardware and firmware elements in the controller 250 or otherwise associated with the flash media 260) wherein the processing circuitry is configured to cause the apparatus to:
track one or more parameters associated with data to be written to a memory system; (paragraph 29, where hardware and firmware elements in the controller 250 or otherwise associated with the flash media 260 can be used to partition the different volumes 252, 254 and 256 and assign their desired different service levels relating to data retention and write endurance, and/or internal components such as a flash management system can be used to relax P/E cycle count limitations and/or switch between error detection and error correction for the different volumes 252, 254 and 256 to assign their desired different service levels)
select a block of the memory system for storing the data, wherein the block is selected from a plurality of blocks of the memory system in accordance with the type of data and a quantity of times that the block has been erased; (paragraph 30, where when a volume needs one or more new blocks to write incoming data, it receives such blocks 320 from a wear level allocator 300 according to a data type associated with a service level 310 associated with that volume. As a new erased block becomes available to the volume, the blocks 320 will have an erase count that is less than that required by the service level 310 specified for the particular data type to be stored in the volume) and
write the data to the block in response to selecting the block. (paragraph 30, where when a volume needs one or more new blocks to write incoming data, it receives such blocks 320 from a wear level allocator 300 according to a data type associated with a service level 310 associated with that volume. As a new erased block becomes available to the volume, the blocks 320 will have an erase count that is less than that required by the service level 310 specified for the particular data type to be stored in the volume)
However, the Klein reference does not explicitly teach to: wherein one or more parameters comprising a quantity of times that a range of logical addresses comprising a logical address of the data has been accessed, a quantity of invalid data included in a set of previously selected blocks, or a combination thereof, the quantity is based on a first counter of a plurality of counters mapped to a plurality of non-overlapping ranges of logical addresses; each range of the plurality of non-overlapping ranges is associated with a respective counter, of the plurality of counters, for tracking a respective quantity of times that a corresponding range has been accessed; wherein the set of previously selected blocks is maintained in a list stored to the memory system and corresponds to a threshold quantity of blocks recently selected by the memory system; and to predict a type of data associated with the data according to the tracked one or more parameters satisfying one or more thresholds; and wherein the block is selected from a plurality of blocks of the memory system in accordance with the type of predicted data. (emphasis added)
The Kim reference teaches it is conventional to predict a type of data associated with the data according to the tracked one or more parameters; and wherein the block is selected from a plurality of blocks of the memory system in accordance with the type of predicted data. (paragraph 107, where when a record block is written, the block write type big data analysis controller 262 predicts the read frequency of the record block and controls the record block to be stored in one or more of the memory, SSD and HDD, selected in response to the read frequency)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Klein reference to have to predict a type of data associated with the data according to the tracked one or more parameters satisfying one or more thresholds; and wherein the block is selected from a plurality of blocks of the memory system in accordance with the type of predicted data, as taught by the Kim reference.
The suggestion/motivation for doing so would have been to have efficient storage and real-time analysis of big data. (Kim, abstract)
However, the combination of the Klein and Kim references does not explicitly teach the one or more parameters comprising a quantity of times that a range of logical addresses comprising a logical address of the data has been accessed, a quantity of invalid data included in a set of previously selected blocks, or a combination thereof, wherein: the quantity is based on a first counter of a plurality of counters mapped to a plurality of non-overlapping ranges of logical addresses; each range of the plurality of non-overlapping ranges is associated with a respective counter, of the plurality of counters, for tracking a respective quantity of times that a corresponding range has been accessed; and the set of previously selected blocks is maintained in a list stored to the memory system and corresponds to a threshold quantity of blocks recently selected by the memory system.
The Boitei reference teaches it is conventional to have one or more parameters comprising a quantity of invalid data included in a set of previously selected blocks, wherein the set of previously selected blocks is maintained in a list stored to the memory system and corresponds to a threshold quantity of blocks recently selected by the memory system. (paragraph 55, based on the information retrieved from the page map table, a set of target memory blocks is identified such that, number of invalid pages in each memory block is more than equal to a maximum invalid page threshold. In other words, those memory blocks in which the number of invalid pages is above a given threshold are selected. For example, the total number of memory blocks in the flash memory is 24 and the maximum invalid page threshold may be fixed at 40. Moreover, 12 of these 24 memory blocks have more than 40 invalid pages and are thus identified as the set of target memory blocks)
The Examiner further notes the limitation of “a quantity of times that a range of logical addresses comprising a logical address of the data has been accessed, or a combination thereof, wherein: the quantity is based on a first counter of a plurality of counters mapped to a plurality of non-overlapping ranges of logical addresses; each range of the plurality of non-overlapping ranges is associated with a respective counter, of the plurality of counters, for tracking a respective quantity of times that a corresponding range has been accessed” is an optional limitation based on the ‘one or more parameters’ limitations and thus is not required by the claim language based on the broadest reasonable interpretation of the claimed subject matter.
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Klein and Kim references to have one or more parameters comprising a quantity of invalid data included in a set of previously selected blocks, wherein the set of previously selected blocks is maintained in a list stored to the memory system and corresponds to a threshold quantity of blocks recently selected by the memory system, as taught by the Bottei reference.
The suggestion/motivation for doing so would have been to have recycling based on maximum invalid pages and minimum valid pages using the page map table; and as a result, more invalid pages are freed and less valid pages are required to be copied to a free memory block. (Boitei, paragraph 58)
Therefore it would have been obvious to combine the Klein, Kim, and Bottei references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to:
select a second block of the memory system for storing second data of a second predicted type of data in accordance with the second predicted type of data and a second quantity of times that the second block has been erased, wherein the second quantity of times that the second block has been erased is greater than the quantity of times that the block has been erased in accordance with the type of data being associated with a first expected life duration that is less than a second expected life duration associated with the second predicted type of data; and write the second data to the second block in accordance with selecting the second block. (Klein, paragraph 30, where when a volume needs one or more new blocks to write incoming data, it receives such blocks 320 from a wear level allocator 300 according to a data type associated with a service level 310 associated with that volume. As a new erased block becomes available to the volume, the blocks 320 will have an erase count that is less than that required by the service level 310 specified for the particular data type to be stored in the volume)
With respect to claim 3, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: select a third block of the memory system for storing third data of a third type of data in accordance with the third type of data and a third quantity of times that the third block has been erased, wherein the third quantity of times that the third block has been erased is less than the quantity of times that the block has been erased in accordance with the type of data being associated with a first expected life duration that is greater than a third expected life duration associated with the third type of data; and write the third data to the third block in response to selecting the third block. (Klein, paragraph 30, where when a volume needs one or more new blocks to write incoming data, it receives such blocks 320 from a wear level allocator 300 according to a data type associated with a service level 310 associated with that volume. As a new erased block becomes available to the volume, the blocks 320 will have an erase count that is less than that required by the service level 310 specified for the particular data type to be stored in the volume)
With respect to claim 10, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: maintain the list of the set of previously selected blocks, wherein to determine the type of data, the processing circuitry is configured to cause the apparatus to: predict a quantity of invalid data in the set of previously selected blocks. (Klein, paragraph 31, where a garbage collection process 400 can be performed on the blocks 442, 444 and 446 in the background to erase dirty blocks or merge blocks with high levels of dirty data. A dirty block, in other words, a block in which all pages therein are dirty, is erased and sent to a free pages pool. Also according to a nonlimiting embodiment of the invention, following a request for one or more free blocks for a volume (and, therefore, requiring a particular data type and service level), one or more blocks 410 can be selected as candidates for merger and erase according to their dirty level, erase count and data type 420 associated with a service level consistent with the volume [i.e. the amount of dirty pages are determined and thus the amount of ‘invalid’ amount of pages are determined within a block])
With respect to claim 11, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 10, wherein the processing circuitry is further configured to cause the apparatus to: determine that the quantity of invalid data in the set of previously selected blocks satisfies a threshold quantity of invalid data, wherein the type of data is predicted in response to determining that the quantity of invalid data satisfies the threshold quantity of invalid data; (Klein, paragraph 31, where a garbage collection process 400 can be performed on the blocks 442, 444 and 446 in the background to erase dirty blocks or merge blocks with high levels of dirty data. A dirty block, in other words, a block in which all pages therein are dirty, is erased and sent to a free pages pool. Also according to a nonlimiting embodiment of the invention, following a request for one or more free blocks for a volume (and, therefore, requiring a particular data type and service level), one or more blocks 410 can be selected as candidates for merger and erase according to their dirty level, erase count and data type 420 associated with a service level consistent with the volume [i.e. the amount of dirty pages are determined to meet a threshold and thus the amount of ‘invalid’ amount of pages are determined within a block]) and
determine that the quantity of times that the block has been erased is less than a threshold erase quantity in response to predicting determining the type of data, wherein the block is selected in response to that the quantity of times that block has been erased being less than the threshold erase quantity. (Klein, paragraph 30, where when a volume needs one or more new blocks to write incoming data, it receives such blocks 320 from a wear level allocator 300 according to a data type associated with a service level 310 associated with that volume. As a new erased block becomes available to the volume, the blocks 320 will have an erase count that is less than that required by the service level 310 specified for the particular data type to be stored in the volume)
With respect to claim 12, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 10, wherein the processing circuitry is further configured to cause the apparatus to: determine that the quantity of invalid data in the set of previously selected blocks fails to satisfy a threshold quantity of invalid data, wherein the type of data is predicted in response to determining that the quantity of invalid data fails to satisfy the threshold quantity of invalid data; (Klein, paragraph 31, where a garbage collection process 400 can be performed on the blocks 442, 444 and 446 in the background to erase dirty blocks or merge blocks with high levels of dirty data. A dirty block, in other words, a block in which all pages therein are dirty, is erased and sent to a free pages pool. Also according to a nonlimiting embodiment of the invention, following a request for one or more free blocks for a volume (and, therefore, requiring a particular data type and service level), one or more blocks 410 can be selected as candidates for merger and erase according to their dirty level, erase count and data type 420 associated with a service level consistent with the volume [i.e. the amount of dirty pages are determined to meet a threshold and thus the amount of ‘invalid’ amount of pages are determined within a block]) and
determine that the quantity of times that the block has been erased is greater than a threshold erase quantity in response to prediction the type of data, wherein the block is selected in response to the quantity of times that block has been erased being greater than the threshold erase quantity. (Klein, paragraph 30, where when a volume needs one or more new blocks to write incoming data, it receives such blocks 320 from a wear level allocator 300 according to a data type associated with a service level 310 associated with that volume. As a new erased block becomes available to the volume, the blocks 320 will have an erase count that is less than that required by the service level 310 specified for the particular data type to be stored in the volume [i.e. the second volume has blocks that are greater than the erase threshold for the first volume])
With respect to claim 13, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 10, wherein the list of the set of previously selected blocks is stored to a memory device of the memory system that comprises volatile memory cells. (Klein, paragraph 26, where different data types include (but are not limited to) data that may be stored in volatile and non-volatile memory spaces of a conventional host system, and the different applications include (but are not limited to) log files, databases, temporary databases, and indexes associated with the DBMS 200)
With respect to claim 16, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 1, wherein the data is written in response to a write command received from a host system. (Klein, paragraph 30, where there is an incoming write)
With respect to claim 17, the combination of the Klein, Kim, and Bottei references teaches the apparatus of claim 1, wherein the data is written as part of a garbage collection operation associated with moving the data from a second block to the block. (Klein, paragraph 34, where there is garbage collection and merging of data)
Claims 18 and 23 are the non-transitory computer-readable medium implementation of the claims above, and rejected under the same rationale as shown in the rejections above.
Claim 25 is the method implementation of the claims above, and rejected under the same rationale as shown in the rejections above.
Claims 5-9 and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 20160011815) in view of Kim (US 20170286008) and Bottei (US 20170052719) as shown in the rejections above, and further view of Garratt (US 20100153616).
With respect to claim 5, the combination of the Klein, Kim, and Bottei references does not explicitly teach the apparatus of claim 1, wherein, to determine the type of data, the processing circuitry is configured to cause the apparatus to: identify a segment of a mapping of the memory system, the mapping for translating logical addresses to physical addresses of the memory system, the segment comprising the range of logical addresses comprising the logical address of the data; and determine a value of the first counter, the first counter for tracking a quantity of times that respective data is written to a respective logical address included in the segment, wherein the type of data is predicted in accordance with the value of the first counter.
The Garratt reference teaches it is conventional to have wherein:
to determine the type of data, the processing circuitry is configured to cause the apparatus to: identify a segment of a mapping of the memory system, the mapping for translating logical addresses to physical addresses of the memory system, the segment comprising the range of logical addresses comprising the logical address of the data; and determine a value of the first counter, the first counter for tracking a quantity of times that respective data is written to a respective logical address included in the segment, wherein the type of data is predicted in accordance with the value of the first counter. (paragraph 15, where write requests, including data and corresponding logical addresses are received from a host process or host system; and see fig. 2; and paragraphs 26-28, where determination is made as to whether the logical address is a relatively high-use address. The determination may include retrieving a value from a table or other data structure, indicative of prior usage of the logical address. At 306, where the logical address is a relatively high-use address, the logical address is mapped to higher-endurance memory cells 206 in FIG. 2. At 308, where the logical address is a relatively low-use address, the logical address is mapped to lower-endurance memory cells 208 in FIG. 2)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify combination of the Klein, Kim, and Bottei references to determine the type of data, the processing circuitry is configured to cause the apparatus to: identify a segment of a mapping of the memory system, the mapping for translating logical addresses to physical addresses of the memory system, the segment comprising the range of logical addresses comprising the logical address of the data; and determine a value of the first counter, the first counter for tracking a quantity of times that respective data is written to a respective logical address included in the segment, wherein the type of data is predicted in accordance with the value of the first counter, as taught by the Garratt reference.
The suggestion/motivation for doing so would have been to have improved endurance that may be obtained with a relatively small percentage of higher-endurance memory cells, at a relatively low cost. (Garratt, abstract)
Therefore it would have been obvious to combine the Klein, Kim, Bottei, and Garratt references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 6, the combination of the Klein, Kim, Bottei, and Garatt references teaches the apparatus of claim 5, wherein the processing circuitry is further configured to cause the apparatus to: receive a write command comprising second data having a second logical address included in the segment; and increment the value of the first counter based on the second data having the second logical address included in the segment, wherein the value of the first counter is associated with the incrementing. (Garratt, see fig. 2; and paragraphs 26-28, where determination is made as to whether the logical address is a relatively high-use address. The determination may include retrieving a value from a table or other data structure, indicative of prior usage of the logical address. At 306, where the logical address is a relatively high-use address, the logical address is mapped to higher-endurance memory cells 206 in FIG. 2. At 308, where the logical address is a relatively low-use address, the logical address is mapped to lower-endurance memory cells 208 in FIG. 2; and paragraph 51, where there are logical addresses with corresponding write counts)
With respect to claim 7, the combination of the Klein, Kim, Bottei, and Garatt references teaches the apparatus of claim 5, wherein the processing circuitry is further configured to cause the apparatus to: compare the value of the first counter to respective values of the plurality of counters associated with a plurality of segments of the mapping, wherein, to predict the type of data, the processing circuitry is configured to cause the apparatus to: determine the value of the first counter relative to the respective values of the plurality of counters in accordance with the comparing. (Garratt, see fig. 2; and paragraphs 26-28, where determination is made as to whether the logical address is a relatively high-use address. The determination may include retrieving a value from a table or other data structure, indicative of prior usage of the logical address. At 306, where the logical address is a relatively high-use address, the logical address is mapped to higher-endurance memory cells 206 in FIG. 2. At 308, where the logical address is a relatively low-use address, the logical address is mapped to lower-endurance memory cells 208 in FIG. 2; [i.e. there is a ‘comparison’ based on usage])
With respect to claim 8, the combination of the Klein, Kim, Bottei, and Garatt references teaches the apparatus of claim 5, wherein the processing circuitry is further configured to cause the apparatus to: compare the value of the first counter to a threshold associated with the predicted type of data, wherein to predict the type of data, the processing circuitry is configured to cause the apparatus to: determine whether the first value of the first counter satisfies the threshold. (Garratt, paragraph 36, where the count value associated with the logic address is compared to the threshold)
With respect to claim 9, the combination of the Klein, Kim, Bottei, and Garatt references teaches the apparatus of claim 5, wherein respective values of the plurality of counters comprising the first counter and associated with a plurality of segments of the mapping are stored to a memory device of the memory system that comprises volatile memory cells. (Klein, paragraph 26, where different data types include (but are not limited to) data that may be stored in volatile and non-volatile memory spaces of a conventional host system, and the different applications include (but are not limited to) log files, databases, temporary databases, and indexes associated with the DBMS 200)
Claims 20-22 are the non-transitory computer-readable medium implementation of the claims above, and rejected under the same rationale as shown in the rejections above.
Claims 14-15 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Klein (US 20160011815) in view of Kim (US 20170286008) and Bottei as shown in the rejections above, and further view of Agarwal (US 20210149583).
With respect to claim 14, the combination of the Klein, Kim, and Bottei references does not explicitly teach the apparatus of claim 1, wherein, to determine the type of data, the processing circuitry is configured to cause the apparatus to: receive, from a host system, a write command comprising the data and an indication of the type of data, wherein the type of data is in accordance with the indication of the type of data and predicted the type of data.
The Agarwal reference teaches it is conventional to have:
wherein, to determine the type of data, the processing circuitry is configured to cause the apparatus to: receive, from a host system, a write command comprising the data and an indication of the type of data, wherein the type of data is determined in accordance with the indication of the type of data and predicted the type of data. (paragraph 65, where if the controller identifies the tracked pattern recurring in subsequent read commands, the controller may load the predicted control page in advance of executing the subsequent command. When the controller later executes the subsequent command, the controller may identify the logical address from the predicted control page and sense the corresponding data 119 as described above. If the prediction is successful, the controller may update a stored frequency indicating a success of the control page pattern)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Klein, Kim, and Bottei references to have wherein, to determine the type of data, the processing circuitry is configured to cause the apparatus to: receive, from a host system, a write command comprising the data and an indication of the type of data, wherein the type of data is determined in accordance with the indication of the type of data and predicted the type of data, as taught by the Agarwal reference.
The suggestion/motivation for doing so would have been to allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. (Agarwal, abstract)
Therefore it would have been obvious to combine the Klein, Kim, Bottei, and Agarwal references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 15, the combination of the Klein, Kim, Bottei, and Agarwal references teaches the apparatus of claim 14, wherein the type of data is predicted in accordance with a weighted combination of the indication of the type of data and the predicted type of data. (Agarwal, paragraph 65, where the controller may also apply an offset to the control pages in the pattern, such as a weighted average or minimum or maximum value of the control pages, and store the offset in the memory. The offset may be used to identify control page patterns and predicted control pages in different ranges of control pages)
Claim 24 is the non-transitory computer-readable medium implementation of the claims above, and rejected under the same rationale as shown in the rejections above.
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 10-14 of the remarks) and amendments with respect to claims 1-3, 5-18, and 20-25 have been considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Boitei reference as shown in the rejections above to teach some of the newly added limitations. The Examiner further notes the arguments pertaining to the newly added limitations “wherein the quantity is based on a first counter of a plurality of counters mapped to a plurality of non-overlapping ranges of logical addresses; each range of the plurality of non-overlapping ranges is associated with a respective counter, of the plurality of counters, for tracking a respective quantity of times that a corresponding range has been accessed” is based on an optional limitation of “track one or more parameters associated with data to be written to a memory system, the one or more parameters comprising a quantity of times that a range of logical addresses comprising a logical address of the data has been accessed …”, in which another parameter has been taught as shown in the rejections above as shown by the Boitei reference.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights