DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-21 are pending in the application and are currently being examined. Claims 1, 3-5, and 12-14 have been amended.
Response to Arguments
Applicant’s arguments, see pages 6-8, filed 3/3/2026, with respect to the rejection(s) of claim(s) 1-21 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the newly amended limitation of "a first end portion extending past a first surface of the interposer board toward the first PCB second surface and having a second end portion extending past a second surface of the interposer board toward the substrate".
Examiner agrees after reviewing the argument from the applicant that the prior art of record does not teach a generally accepted C-shape. Examiner also agrees that the prior art of record does not teach the newly amended limitation the newly amended limitation of "a first end portion extending past a first surface of the interposer board toward the first PCB second surface and having a second end portion extending past a second surface of the interposer board toward the substrate”. However, Examiner respectfully disagrees that the claims are allowable over the prior art, and directs Applicant to the rejection to follow.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 6-7, 12-15, 17-19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Azeroual et al. (US 2020/0388598 A1, hereafter Azeroual) in view of Ho et al. (US 2021/0066831 A1, hereafter Ho) and in view of Drury et al. (US 2022/0104361 A1, hereafter Drury).
Regarding claim 1, Figs. 1A and 2A of Azeroual teaches an apparatus, comprising:
a first printed circuit board (PCB) (164 Fig. 1B, [0028], and 156 in Fig. 2A) including a component (160, [0028]) mounted on a first PCB first surface (166, [0028]) and contacts (180, [0028]) of a first PCB second surface (opposite first surface [0028]);
an interposer board (152, [0026]) having connector pins (220, [0043]) through the interposer board (152) to connect the contacts (180) of the first PCB second surface to a substrate (112, [0026]), the connector pins (220) being compression-based connector pins ([0026], [0043]).
Azeroual is silent on the compression-based connector pins to have a C-shape being a loop with a gap on one side having a first end portion extending past a first surface of the interposer board toward the first PCB second surface and having a second end portion extending past a second surface of the interposer board toward the substrate.
However, Ho teaches a similar compression-based connector pin that has a C-shape (see annotated Fig. 4) with a first end portion extending past a first upper surface and a second end portion extending past a second bottom surface (see annotated Fig. 4). This connector pin is used for physical and electrical connectivity, much like the pins in Azeroual [0042]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the connector pin of Azeroual to be formed similar to the electrical connectors of Ho in order to reduce the volume of the electrical connector, as Ho teaches in [0005-0006].
Azeroual in view of Ho fail to teach a plate to cover the first PCB and secure the first PCB and the interposer board to the substrate, the plate to compress the connector pins of the interposer board, including to compress the first end portion toward the first surface of the interposer board, but does teach bolts being used to apply a compression force to secure the first PCB (164) and the interposer board (152) to the substrate (112) (see [0044] and Fig. 2B).
However, Drury teaches a similar apparatus (Figs. 8A [0038]) comprising a plate (30, [0030], Fig. 4A). This plat, while not present in Fig. 8A, is an obvious variant as Drury states, “[d]epending on the configuration of the PCBs and interposer, any combination of stiffener supports and spacer elements may be implemented to inhibit warpage and maintain separation distances” [0039]. Thus, plate 30 may be present in Fig. 8A to cover a first PCB (50C, [0038], similar to 60 [0030] in Fig. 4A) and secure the first PCB (50C) and an interposer board (10A, [0038]) to a substrate (56, [0038]), the plate (30) to compress connector pins (see 16 and 18 [0029] for labeling in Fig. 4A) of the interposer board (10A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the plate of Drury between the first PCB and bolts of Azeroual, as taught by Drury, in order to prevent warping and protect the apparatus from EM interference [0041], as taught by Drury.
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Regarding claim 17, Azeroual in view of Ho in view of Drury teaches the computer system of claim 12, and Duruy, further teaches screws (54, [0005]) to secure the plate (30, [0030]) to the system board (52C, [0036]), the screws (54) electrically connecting to a ground plane (36, [0041]) (see Fig. 10) of the system board (52C).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Azeroual in view of Ho in view of Drury to further incorporate the teachings of Drury for the same reasons discussed above regarding claim 12.
Regarding claim 18, Azeroual in view of Ho in view of Drury teaches the computer system of claim 17, and Duruy, further teaches the system comprising: standoffs (28, [0039]) (see Fig. 8A; see 20 in Fig. 4A).
Drury does not explicitly teach including standoffs (28) that extend from a top of the plate (30, [0030], Fig. 4A) on top of the first PCB module (50C, [0036]) to the system board (52C, [0036]) through which the screws (54, [0005]) connect to the system board (52C).
However, Drury does teach the plurality of spacer elements (28) (see also 26 in Fig. 5A [0033]) are placed so as to maintain proper separation distances to apply sufficient compression without warping the components therein [0030] and provide proper spacing so as not to crush components under compression force [0031].
Where Azeroual teaches the memory module (156, [0027])having memory chips (160, [0028]) distinctly rising above the surface of (156) (see Fig. 2A), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include standoffs to prevent crushing the raised components and provide adequate distances for the desired compression force, as taught by Drury [0030-0031].
Regarding claim 19, Azeroual in view of Ho in view of Drury teaches the computer system of claim 12, and Duruy, further teaches wherein the plate (30, [0030], Fig. 4A) further comprises sidewalls (where plate 30 can be used in combination with spacers 28, [0039]) to extend from a top of the plate (30) on top of the module (50C, [0036])to the system board (52C, [0036]) (Fig. 8A and Fig. 4A).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Azeroual in view of Ho in view of Drury to further incorporate the teachings of Drury for the same reasons discussed above regarding claim 12.
Regarding claim 21, Azeroual in view of Ho in view of Drury teaches the computer system of claim 12, wherein one or more of:
the processor (120, [0019]) comprises a multicore processor (“one or more packet processors” [0020]);
the computer system further includes a display communicatively coupled to the processor of the substrate;
the computer system further includes a network interface communicatively coupled to the processor (120) of the substrate (112, [0026]); or
the computer system further includes a battery to power the computer system.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Azeroual in view of Ho in view of Drury as applied to claim 4 above, and further in view of Wertz (US 7473104 B1).
Regarding claim 5, Azeroual in view of Drury teaches the apparatus of claim 4.
Azeroual in view of Ho in view of Drury does not teach wherein the connector pins (220, [0043]) have a conductor in a closed loop shape, wherein, when uncompressed, the closed loop has two closed electrical paths, wherein the conductor is to slide along itself on one side to make a smaller closed loop in response to compression of the connector pins (200 of Azeroual, modified as in annotated Fig. 4 of Ho).
Rather, Azeroual in view of Ho in view of Drury teaches an open loop shape (a loop with a gap) having one closed electrical path when uncompressed.
Wertz teaches an apparatus (Figs. 3 and 4) comprising connector pins (220) have a conductor (1, Col. 2, line 35) in a closed loop shape (Fig. 3; where the segments are joined to define a single loop), wherein, when uncompressed (Fig. 3; where Fig. 4 is after engaging a compression force), the closed loop has two closed electrical paths (Fig. 3), wherein the conductor is to slide along itself on one side to make a smaller closed loop in response to compression of the connector pins 1 (see Fig. 4 compared to Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention incorporate the teachings of Wertz to make the dual compression connector pins [0042] of Azeroual to be the connector pins of Wertz in order to provide a two half contact that can reduce the minimum pitch between contacts (Col. 1, lines 65-67).
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Claims 8-9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Azeroual in view of Ho in view of Drury as applied to claims 1, 6 and 12 above, and further in view of Schnell et al. (US 2023/0014167 A1, hereafter Schnell1).
Regarding claim 8, Azeroual in view of Ho in view of Drury teaches the apparatus of claim 6.
Azeroual in view of Ho in view of Drury does not teach a compression attached memory module (CAMM) board to which the memory module (160, [0028]) is mounted to CAMM board first surface contacts, and wherein the interposer board (152, [0026]) is to connect between CAMM board second surface contacts and the compute SOC (120, [0019]), wherein the CAMM board includes routing to electrically align a first pinout of the memory module (160) to a second pinout of the compute SOC (120), where the first pinout is different from the second pinout.
Schnell1 teaches an apparatus (Fig. 2; [0018]) comprising a compression attached memory module (CAMM) board (210, [0018]) to which a memory module (218, [0021]) is mounted to CAMM board first surface contacts [0021,0024], and wherein a interposer board (204, [0018]) is to connect between CAMM board second surface contacts [0019] and a compute SOC (202, [0018]), wherein the CAMM board (210) includes routing (see Figs. 4A/B) to electrically align a first pinout of the memory module (218) to a second pinout of the compute SOC 202, where the first pinout is different from the second pinout [0024] (Figs. 4A/B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the CAMM of Schnell1 in the device of Azeroual in order to have more efficient routing [0024], as taught by Schnell1.
Regarding claim 9, Azeroual in view of Ho in view of Drury in view of Schnell1 teaches the apparatus of claim 8, and Azeroual further teaches wherein the memory module (160, [0028]) includes multiple dynamic random access memory (DRAM) devices ([0054]; Fig. 1B).
Regarding claim 16, Azeroual in view of Ho in view of Drury teaches the computer system of claim 12. Azeroual does not teach a compression attached memory module (CAMM) board to which the memory module (156, [0027]) is mounted to CAMM board first surface contacts, and wherein the interposer board (152, [0026]) is to connect between CAMM board second surface contacts and the substrate (112, [0026]), wherein the CAMM board includes routing to electrically align a first pinout of the memory module to a second pinout of the substrate (112), where the first pinout is different from the second pinout.
Schnell1 teaches compute system (Fig. 2; [0018]) comprising a compression attached memory module (CAMM) board (210, [0018]) to which a memory module (218, [0021]) is mounted to CAMM board first surface contacts [0021,0024], and wherein a interposer board (204, [0018]) is to connect between CAMM board second surface contacts [0019] and a substrate (206, [0018]), wherein the CAMM board (210) includes routing (see Figs. 4A/B) to electrically align a first pinout of the memory module (218) to a second pinout of the substrate (206) (specifically the chip (202) on the substrate) [0024], where the first pinout is different from the second pinout [0024] (Figs. 4A/B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the CAMM of Schnell1 in the device of Azeroual in order to have more efficient routing [0024], as taught by Schnell1.
Claims 10-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Azeroual in view of Ho in view of Drury as applied to claims 1-9 and 12 above, and further in view of Schnell et al. (US 2023/0309227 A1, hereafter Schnell2).
Regarding claim 10, Azeroual in view of Ho in view of Drury and Schnell1 teaches the apparatus of claim 9. Azeroual does not explicitly teach wherein the DRAM devices (160, [0028]) comprise DRAM devices compatible with a double data rate version 5 (DDR5) standard.
Schnell2 teaches an apparatus (Figs. 8 & 14) comprising a memory module the includes multiple DRAM devices (see Figs. 8 & 14) wherein the DRAM devices are compatible with a double data rate version 5 (DDR5) standard [0092].
Given Azeroual does not explicitly teach the kind of memory, and Schnell2 teaches a similar apparatus with memory compatible with DDR5, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the memory device of Azeroual compatible with DDR5, as taught by Schnell2, given Azeroual does not explicitly teach the type of memory, and Schnell2 teaches DDR5 is suitable to serve as a memory module in a similar device to provide fast and efficient memory within the apparatus (see MPEP 2144.07).
Regarding claim 11, Azeroual in view of Ho, Drury, Schnell and Schnell2 teaches the apparatus of claim 10, and Schnell2 further teaches wherein the DRAM devices comprise DRAM devices compatible with a low power double data rate (LPDDR) standard [0092].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further include the teachings of Schnell2 for the same reasons discussed above regarding claim 10.
Regarding claim 20, Azeroual in view of in view of Ho in view of Drury teaches the computer system of claim 12.
Azeroual does not explicitly teach wherein the memory module (156, [0027]) includes multiple dynamic random access memory (DRAM) devices (Fig. 1B) compatible with a double data rate version 5 (DDR5) standard or DRAM device compatible with a low power double data rate (LPDDR) standard.
Schnell2 teaches a compute system (Figs. 8 & 14) comprising a memory module the includes multiple DRAM devices (see Figs. 8 & 14) wherein the DRAM devices are compatible with a double data rate version 5 (DDR5) standard [0092], and wherein the DRAM devices are compatible with a low power double data rate (LPDDR) standard [0092].
Given Azeroual does not explicitly teach the kind of memory, and Schnell2 teaches a similar apparatus with memory compatible with DDR5 (and/or LPDDR5), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the memory device of Azeroual compatible with (LP)DDR5, as taught by Schnell2, given Azeroual does not explicitly teach the type of memory, and Schnell2 teaches (LP)DDR5 is suitable to serve as a memory module in a similar device to provide fast and efficient memory within the compute system (see MPEP 2144.07).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
