DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8 June 2026 has been entered.
Status of the Claims
Amendment filed 8 June 2026 is acknowledged. Claim 2 has been canceled. Claims 1 and 4-6 have been amended. Claims 1 and 3-8 are pending.
Information Disclosure Statement
Information disclosure statement filed 1 May 2026 has been fully considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sanuki (US Patent Application Publication 2017/0256584, hereinafter Sanuki ‘584) of record.
With respect to claim 1, Sanuki ‘584 teaches (FIGs. 2 and 3) a semiconductor device as claimed, comprising:
a plurality of first conductive lines (14 which also includes element 12) extending in a first direction (top-to-bottom) different from a second direction (a diagonal running through the plurality of memory cells MTJ from top-left to bottom-right), a third direction (an opposing diagonal running through the plurality of memory cells MTJ from bottom-left to top-right) and a fourth direction (left-to-right), wherein the first direction is perpendicular to the fourth direction ([0019]);
a plurality of second conductive lines (50) extending in the fourth direction (left-to-right) to intersect the plurality of first conductive lines (14 which also includes element 12) to form intersection regions and being spaced apart from the plurality of first conductive lines ([0027]); and
a plurality of memory cells (MTJ) disposed relative to the plurality of first conductive lines (14 which also includes element 12) and the plurality of second conductive lines (50) so as to overlap the intersection regions, each of the plurality of memory cells being connected to one of the plurality of first conductive lines at a lower end of the memory cell and to one of the second conductive lines at an upper end of the memory cell, and each of the plurality of memory cells including a variable resistance element (30) configured to switch between different resistance states based on a voltage or current applied through the lower end and the upper end of the memory cell ([0022]),
wherein the plurality of memory cells (MTJ) are arranged along lines that are parallel to the first direction (top-to-bottom), the second direction (a diagonal running through the plurality of memory cells MTJ from top-left to bottom-right) and the third direction (an opposing diagonal running through the plurality of memory cells MTJ from bottom-left to top-right), and the plurality of memory cells being respectively positioned at vertices of an imaginary equilateral triangle having three sides parallel to the first direction, the second direction, and the third direction ([0022]),
wherein each first conductive line (14 which also includes element 12) overlaps the plurality of memory cells (MTJ) arranged along a line parallel to the first direction (top-to-bottom) ([0019, 0022]), and
wherein each second conductive line (50) partially overlaps each of the memory cells (MTJ) arranged in the fourth direction ([0022, 0027]).
With respect to claim 3, Sanuki ‘584 teaches wherein, when the memory cells (MTJ) arranged in a line in the first direction (top-to-bottom) are a column of memory cells, a plurality of columns of memory cells are arranged in the fourth direction (left-to-right), the second conductive line (50) overlaps a first portion of the memory cell of an odd-numbered column among the plurality of columns of memory cells and a second portion of the memory cell of an even-numbered column among the plurality of columns of memory cells, and the first portion and the second portion face to each other ([0019, 0022, 0027]).
With respect to claim 4, Sanuki ‘584 teaches wherein a pitch of the plurality of first conductive lines (14 which also includes element 12) is smaller than a pitch of the plurality of second conductive lines (50) ([0019, 0027]).
With respect to claim 5, Sanuki ‘584 teaches wherein a pitch of the plurality of first conductive lines (14 which also includes element 12) is smaller than a pitch of the plurality of memory cells (MTJ) ([0019, 0022]).
With respect to claim 6, Sanuki ‘584 teaches wherein a pitch of the plurality of second conductive lines (50) and a pitch of the plurality of memory cells (MTJ) are the same ([0022, 0027]).
With respect to claim 7, Sanuki ‘584 teaches wherein, in the first direction (top-to-bottom), a center of the second conductive line (50) and a center of the memory cell (MTJ) are misaligned ([0022, 0027]).
With respect to claim 8, Sanuki ‘584 teaches wherein, in the fourth direction (left-to-right), a center of the first conductive line (14 which also includes element 12) and a center of the memory cell (MTJ) are aligned ([0019, 0022]).
Response to Arguments
Applicant’s arguments with respect to amended claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights