DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 2 February 2026 is acknowledged. Claims 9-18 have been canceled. Claim 1 has been amended. Claims 1-8 are pending.
Drawings & Specification
The amendments to the drawings and the title were received on 2 February 2026. These amendments to the drawings and the title are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Fujimoto (US Patent Application Publication 2010/0133497, hereinafter Fujimoto ‘497) in view of Fuhrmann et al. (US Patent Application Publication 2004/0022100, hereinafter Fuhrmann ‘100), both of record.
With respect to claim 1, Fujimoto ‘497 teaches (FIG. 5) a semiconductor device substantially as claimed, comprising:
a plurality of first conductive lines (2) extending in a first direction (y) different from a second direction (a diagonal of x and y running through centers of memory cells 3 shown by pitch W), a third direction (another diagonal of x and y running through centers of memory cells 3 shown by pitch W) and a fourth direction (x), wherein the first direction is perpendicular to the fourth direction ([0046]);
a plurality of second conductive lines (1) extending in the fourth direction (x) to intersect the first conductive lines (2) to form intersection regions and being spaced apart from the plurality of first conductive lines ([0046]); and
a plurality of memory cells (3) disposed relative to the first conductive lines (2) and the second conductive lines (1) so as to overlap the intersection regions, the plurality of memory cells being arranged along lines that are parallel to the first direction (y), the second direction (a diagonal of x and y running through centers of memory cells 3 shown by pitch W) and the third direction (another diagonal of x and y running through centers of memory cells 3 shown by pitch W), and the plurality of memory cells being respectively positioned at vertices of an imaginary equilateral triangle having three sides parallel to the first direction, the second direction, and the third direction ([0046-0047]),
wherein each first conductive line (2) overlaps the plurality of memory cells (3) arranged along a line parallel to the first direction (y) ([0046]), and
wherein each second conductive line (1) overlaps at least some of the plurality of memory cells (3) in at least some of the intersection regions ([0046]).
Thus, Fujimoto ‘497 is shown to teach all the features of the claim with the exception of wherein centers of the at least some of the intersection regions are positioned on boundaries of the at least some of the plurality of memory cells and are arranged along the fourth direction.
However, Fuhrmann ‘100 teaches (FIG. 5) centers of at least some of intersection regions of first (1) and second (2) conductive lines are positioned on boundaries of at least some of a plurality of memory cells (3) and are arranged along a fourth direction ([0037]) to save area on a semiconductor substrate ([0008]). Further, such a modification would have involved a mere change in size or proportion of a component. A change in size or proportion is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04 IV. A.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed centers of the at least some of the intersection regions of Fujimoto ‘497 positioned on boundaries of the at least some of the plurality of memory cells and arranged along the fourth direction as taught by Fuhrmann ‘100 to save area on a semiconductor substrate, and because such a modification would have involved a mere change in size or proportion of a component.
With respect to claim 2, Fujimoto ‘497 teaches wherein the second conductive line (1) partially overlaps each of the memory cells (3) arranged in the fourth direction (x) ([0046]).
With respect to claim 3, Fujimoto ‘497 teaches wherein, when the memory cells (3) arranged in a line in the first direction (y) are a column of memory cells, a plurality of columns of memory cells are arranged in the fourth direction (x), the second conductive line (1) overlaps a first portion of the memory cell of an odd-numbered column among the plurality of columns of memory cells and a second portion of the memory cell of an even-numbered column among the plurality of columns of memory cells, and the first portion and the second portion face to each other ([0046]).
With respect to claim 4, Fujimoto ‘497 teaches wherein a pitch (B) of the first conductive lines (2) is smaller than a pitch (W) of the second conductive lines (1) ([0048]).
With respect to claim 5, Fujimoto ‘497 teaches wherein a pitch (B) of the first conductive lines (2) is smaller than a pitch (W) of the memory cells (3) ([0048]).
With respect to claim 6, Fujimoto ‘497 teaches wherein a pitch (W) of the second conductive lines (1) and a pitch (W) of the memory cells (3) are the same ([0048]).
With respect to claim 7, Fujimoto ‘497 teaches wherein, in the first direction (y), a center of the second conductive line (1) and a center of the memory cell (3) are misaligned ([0046]).
With respect to claim 8, Fujimoto ‘497 teaches wherein, in the fourth direction (x), a center of the first conductive line (2) and a center of the memory cell (3) are aligned ([0046]).
Response to Arguments
Applicant’s amendments to the drawings and the title are sufficient to overcome the objections to the drawings and the title made in the non-final rejection filed 10 July 2025. The objections to the drawings and the title have been withdrawn.
Applicant’s amendments to claim 1 are sufficient to overcome the 35 U.S.C. 112(b) rejection of claims 1-8 made in the non-final rejection filed 10 July 2025. The 35 U.S.C. 112(b) rejection of claims 1-8 has been withdrawn.
Applicant’s arguments with respect to the prior art rejection of amended claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893