DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 March 2026 has been entered.
Status of the Claims
Amendment filed 16 March 2026 is acknowledged. Claims 1, 2, and 5 have been amended. Claims 1-20 are pending. Claims 10-16 remain withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sandhu et al. (US Patent Application Publication 2019/0027477, hereinafter Sandhu ‘477) in view of Kim (US Patent Application Publication 2020/0312552, hereinafter Kim ‘552) and Han (US Patent Application Publication 2022/0037326, hereinafter Han ‘326), all three of record.
With respect to claim 1, Sandhu ‘477 teaches (FIG. 1) a semiconductor memory device substantially as claimed, comprising:
a first conductor layer (48) extending along a plane, the plane including a first direction and a second direction intersecting the first direction ([0025]);
a first capacitor (12 associated with memory cell 62a) ([0011]);
a second capacitor (12 associated with memory cell 62b), the first capacitor and the second capacitor arranged along a front surface of the first conductor layer (48) ([0011]); and
a first transistor (16 associated with memory cell 62a) electrically connected to the first capacitor (12 associated with memory cell 62a) ([0013]),
a second transistor (16 associated with memory cell 62b) electrically connected to the second capacitor (12 associated with memory cell 62b) ([0013]),
wherein the first capacitor (12 associated with memory cell 62a) includes:
a first electrode (18 associated with memory cell 62a) extending in a third direction, the third direction crossing each of the first direction and the second direction, the first electrode electrically connected to the first transistor (16 associated with memory cell 62a) ([0014]);
a dielectric layer (20 associated with memory cell 62a) disposed on an outer periphery of the first electrode (18 associated with memory cell 62a), and on the first conductive layer (48) ([0014]);
a second electrode (22) disposed on an outer periphery of the dielectric layer (20 associated with memory cell 62a), the second electrode electrically connected to the first conductor layer (48), the dielectric layer disposed on an outer periphery of the second electrode (no frame of reference is supplied in the claim from which to define an inner or outer periphery, and thus the second electrode 22 and the dielectric layer 20 are disposed on the outer peripheries of each other) ([0014]); and
a first insulating layer (40 associated with memory cell 62a) disposed between the first electrode (18 associated with memory cell 62a) and the first conductor layer (48), the first insulating layer (e.g. silicon dioxide) containing a material different from a material contained in the dielectric layer (20; e.g. zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, strontium titanate (STO), etc.) ([0018, 0021]),
wherein the second capacitor (12 associated with memory cell 62b) includes:
a third electrode (18 associated with memory cell 62b) extending in the third direction, the third electrode electrically connected to the second transistor (16 associated with memory cell 62a), the dielectric layer (20 associated with memory cell 62a) disposed on an outer periphery of the third electrode ([0014]); and
a second insulating layer (40 associated with memory cell 62b) disposed between the third electrode (18 associated with memory cell 62b) and the first conductor layer (48) ([0018, 0021]).
Thus, Sandhu ‘477 is shown to teach all the features of the claim with the exception of:
a second conductor layer extending in the first direction;
wherein the first transistor is electrically connected to the second conductor layer;
wherein the second transistor is electrically connected to the second conductor layer; and
wherein the second capacitor includes the second electrode.
However, Han ‘326 teaches (FIG. 10B) a semiconductor memory device comprising a second conductor layer (81) extending in a first direction, wherein transistors (defined at channel 72) are electrically connected to the second conductor layer to function as a word line or bit line of said transistors ([0079, 0085]).
Further, Kim ‘552 teaches (FIG. 3A) first and second capacitors sharing a second electrode (207) ([0035]) in an arrangement that improves the characteristics and yield of the capacitors ([0095]), and allows for the interconnection between said capacitors without an additional metallization or etching step.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor memory device of Sandhu ‘447 further comprising a second conductor layer extending in the first direction; wherein the first transistor is electrically connected to the second conductor layer; and wherein the second transistor is electrically connected to the second conductor layer as taught by Han ‘326 to function as a word line or bit line of said first and second transistors; and to have formed the second capacitor of Sandhu ‘477 including the second electrode as taught by Kim ‘552 in an arrangement that improves the characteristics and yield of the capacitors, and allows for the interconnection between said capacitors without an additional metallization or etching step.
With respect to claim 2, Sandhu ‘477 teaches wherein the first insulating layer (40 associated with memory cell 62a) is in contact with the first electrode (18 associated with memory cell 62a) and the first conductor layer (48) ([0021]).
With respect to claim 3, Sandhu ‘477 teaches wherein the first insulating layer (40 associated with memory cell 62a) contains silicon oxide ([0021]).
With respect to claim 4, Sandhu ‘477 teaches wherein the first insulating layer (40 associated with memory cell 62a) and the first electrode (18 associated with memory cell 62a) have substantially the same shape when viewed from the third direction ([0014, 0021]).
With respect to claim 5, Sandhu ‘477, Han ‘326, and Kim ‘552 teach the device as described in claim 1 above, but primary reference Sandhu ‘477 does not explicitly teach the additional limitation wherein the second electrode includes a first portion and a second portion, the second portion covered with the first portion, the first portion in contact with the first conductor layer, the second portion containing a material different from a material contained in the first portion.
However, Kim ‘552 teaches (FIG. 3A) a second electrode (207 and 207L) including a first portion (207L) and a second portion (207), the second portion covered with the first portion, and the second portion containing a material different from a material contained in the first portion ([0042]) to reduce the resistance of the electrode ([0079]). When the bilayer second electrode (207 and 207L) of Kim ‘552 is applied to the second electrode (22) of Sandhu ‘477, this would result in the first portion (207L of Kim ‘552) being in contact with the first conductor layer (48 of Sandhu ‘477).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the second electrode of Sandhu ‘477, Han ‘326, and Kim ‘552 including a first portion and a second portion, the second portion covered with the first portion, the first portion in contact with the first conductor layer, the second portion containing a material different from a material contained in the first portion as taught by Kim ‘552 to reduce the resistance of the electrode.
With respect to claim 6, Sandhu ‘477 teaches wherein a cross section of the first electrode (18 associated with memory cell 62a) perpendicular to the third direction has a circular shape (see FIG. 25; [0066]).
With respect to claim 7, Sandhu ‘477, Han ‘326, and Kim ‘552 teach the device as described in claim 1 above, but primary reference Sandhu ‘447 does not explicitly teach the additional limitation wherein the first transistor includes a channel layer containing an oxide semiconductor.
However, Han ‘326 teaches (FIG. 10B) transistors connected to capacitors (CAP1 and CAP2) including a channel layer (42A and 72) containing an oxide semiconductor as a material having high electron mobility, low leakage current, and low deposition temperature ([0046, 0080]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first transistor of Sandhu ‘477, Han ‘326, and Kim ‘552 including a channel layer containing an oxide semiconductor as taught by Han ‘326 as an art-recognized material suitable for the intended use as a channel material having high electron mobility, low leakage current, and low deposition temperature.
With respect to claim 17, Sandhu ‘477 teaches wherein the columnar first electrode (18 associated with memory cell 62a) includes an inner electrode (24 associated with memory cell 62a) and an outer electrode (26 associated with memory cell 62a), the outer electrode being outside of the inner electrode and being of a material different from that of the inner electrode ([0016]).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sandhu ‘477, Han ‘326, and Kim ‘552 as applied to claim 1 above, and further in view of Tanaka et al. (US Patent Application Publication 2017/0271341, hereinafter Tanaka ‘341) of record.
With respect to claim 8, Sandhu ‘477, Han ‘326, and Kim ‘552 teach the device as described in claim 1 above, with primary reference Sandhu ‘477 teaching the additional limitation further comprising: circuits (14 associated with memory cell 62a) disposed on a substrate, wherein the first transistor (16 associated with memory cell 62a) is electrically connected to the circuits ([0012]).
Thus, Sandhu ‘477 is shown to teach all the features of the claim with the exception of wherein the circuits include a sense amplifier.
However, Tanaka ‘341 teaches (FIG. 8) circuits formed in a substrate (11) below transistors and capacitors and including a sense amplifier (SA0-SA3) to amplify memory signals ([0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the circuits of Sandhu ‘477, Han ‘326, and Kim ‘552 including a sense amplifier as taught by Tanaka ‘341 to amplify memory signals.
With respect to claim 9, Sandhu ‘477 teaches wherein the first transistor (16 associated with memory cell 62a) is disposed between the circuits (14 associated with memory cell 62a) and the first capacitor (12 associated with memory cell 62a) ([0012]).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sandhu ‘477, Han ‘326, and Kim ‘552 as applied to claim 17 above, and further in view of Kawasaki et al. (US Patent 5,240,558, hereinafter Kawasaki ‘558) of record.
With respect to claim 18, Sandhu ‘477, Han ‘326, and Kim ‘552 teach the device as described in claim 17 above with the exception of the additional limitation wherein the inner electrode is of an amorphous silicon material.
However, Kawasaki ‘558 teaches (FIG. 8) one of tungsten or amorphous silicon as an art-recognized capacitor electrode (34) material (col. 3, ln. 58 – col. 4, ln. 4). It has been held as obvious to substitute equivalents known for the same purpose. Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980). See MPEP 2144.06 II. One of ordinary skill in the art could substitute the tungsten capacitor inner electrode (24 associated with memory cell 62a) material of Sandhu ‘477 with the amorphous silicon capacitor electrode (34) material of Kawasaki ‘558 with a reasonable expectation of success. Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the inner electrode of Sandhu ‘477, Han ‘326, and Kim ‘552 of an amorphous silicon material as taught by Kawasaki ‘558 as an art-recognized substitute material suitable for the intended use as a capacitor electrode material.
With respect to claim 19, Sandhu ‘477 teaches wherein the outer electrode (26 associated with memory cell 62a) is of a titanium nitride material ([0016]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sandhu ‘477, Han ‘326, and Kim ‘552 as applied to claim 5 above, and further in view of Lee (US Patent 5,846,859, hereinafter Lee ‘859) of record.
With respect to claim 20, Sandhu ‘477, Han ‘326, and Kim ‘552 teach the device as described in claim 5 above with the exception of the additional limitation wherein the second portion is of an amorphous silicon material.
However, Lee ‘859 teaches an amorphous silicon carbide capacitor electrode to improve the reliability of the capacitor, to provide excellent resistance to electrode oxidation, and to prevent the diffusion of oxygen atoms through a grain boundary (col. 1, ln. 66 – col. 2, ln. 9). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the second portion of Sandhu ‘477, Han ‘326, and Kim ‘552 of an amorphous silicon material as taught by Lee ‘859 as an art-recognized material suitable for the intended use as a capacitor electrode material that improves the reliability of the capacitor, provides excellent resistance to electrode oxidation, and prevents the diffusion of oxygen atoms through a grain boundary.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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