Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the
basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 9, 10, 14, 15, 19, and 22 are rejected under 35 U.S.C. 102(a)(1) as
being anticipated by CN-111816686-A by Yuan (hereinafter YUAN).
Claim 1. YUAN discloses a display device (Fig. 1 and 2) comprising:
a plurality of substrates each including a transparent conducting oxide material (2, which can
be transparent oxides that conduct, as they serve as electrodes; see at least p. 7, para.
2 of the attached translated description);
a subpixel positioned on each respective substrate (Fig. 2 components positioned on 2);
a plurality of transistors respectively disposed on the plurality of substrates and provided
in the plurality of subpixels, respectively (11, positioned on both sides of 3);
a plurality of data lines extending in a column direction between the each of the plurality
of substrates (Data1); and
a plurality of light-emitting elements respectively disposed in the plurality of subpixels
and electrically connected to the plurality of transistors (20, connected to 11 by 9), wherein the plurality of substrates are spaced apart from one another (the Fig. 2/1, further seen as Fig. 1/33, are spaced apart), and wherein each of the plurality of data lines have a majority of their area that does not
overlap any substrate of the plurality of substrates and is disposed in space between the
substrates at location where there are spaced apart from one another (Datal does not overlap 33).
Claim 2. YUAN discloses the display device of claim 1, wherein the plurality of
substrates extends in a column direction (subpixels arranged in array, p. 2 para. 3, line 2).
Claim 6. YUAN discloses the display device of claim 1, wherein there is one subpixel on
each substrate (2 has one subpixel on it) and each of the plurality of substrates are spaced apart
from one another so as to correspond to the plurality of subpixels, respectively (the 2 are spaced
apart from one another).
Claim 9. YUAN discloses the display device of claim 6, wherein the plurality of
substrates is arranged in a matrix shape so as to correspond to a selected shape of the plurality of
subpixels, respectively (subpixels arranged in array, p. 2 para. 3, line 2, and they are on the 2 in a
one-to-one shape correspondence).
Claim 10. YUAN discloses the display device of claim 1, further comprising:
a plurality of reference lines (Fig. 1/VDD) extending in a column direction between the
plurality of substrates and configured to transmit reference voltages to the plurality of subpixels
(p. 6, para. 9, line 3),wherein the plurality of reference lines is disposed in the region in which the plurality of substrates is spaced apart from one another (VDD do not overlap the 2, as shown by the outline33, p. 6, para. 6, line 5).
Claim 14. YUAN discloses the display device of claim 1, wherein all of the area of the
column portion of the data line does not overlap any substrate of the plurality of substrates (Fig.
2/Data1 does not overlap Fig. 2/2 as further seen as Fig. 1/33).
Claim 15. YUAN discloses a display device (Fig. 1 and 2) comprising:
a plurality of substrates each including a transparent conductive oxide (2, which can be transparent oxides that conduct, as they serve as electrodes; see at least p. 7, para. 2);
a pixel area on each substrate having at least one subpixel within the pixel area of the
substrate (Fig. 2 subpixel components arranged on 2);
a plurality of transistors electrically connected to and disposed in each subpixels,
respectively (11, positioned on both sides of 3);
a plurality of signal lines extending in a column direction between the plurality of
substrates and configured to transmit alternating current voltages (Datal - signal lines are
necessarily alternating current by definition - p.6, para. 9, lines 6-7); and
a plurality of light-emitting elements respectively disposed in the plurality of subpixels
and electrically connected to the plurality of transistors, respectively (20, connected to 11 by 9),
wherein each of the plurality of substrates are spaced apart from one another (the Fig.
2/2, further seen as Fig. 1/33, are spaced apart), and
wherein each of the plurality of signal lines have a majority of their area not overlapping
any substrate and disposed in a region in which the plurality of substrates are spaced apart from
one another (Data1 do not overlap the (the Fig. 2/2 or Fig. 1/33 and are located where the 2 are
spaced apart).
Claim 19. YUAN discloses a display device (Fig. 1 and 2) comprising:
a base layer (1);
a plurality of substrates positioned on the base layer, each of the substrates including a transparent conductive oxide and the plurality of substrates being spaced apart from each other (2, which can be transparent oxides, spaced apart, that conduct, as they serve as electrodes; see at least p. 7, para. 2);
a pixel area on each substrate (Fig. 2 components arranged on 2);
a plurality of transistors electrically connected to and disposed in each pixel area,
respectively (11, positioned on both sides of 3 and electrically connected by 9); and
a plurality of data signal lines extending in a column direction between the plurality of
substrates and configured to transmit a data signal (Data1, p.6, para. 9, lines 6-7), each of the
data lines having a majority of their area located in position between the substrates and not
overlapping any substrate (Datal does not overlap 33).
Claim 22. YUAN discloses the display device of claim 19 further including a plurality of
reference signal lines (Fig. 1/VDD) extending in a column direction between the plurality of
substrates and configured to transmit a reference signal (p.6, para. 9, line 3), each of the
reference signal lines having a majority of their area located in position between the substrates
and not overlapping any substrate (VDD do not overlap the 2, as shown by the outline 33, p.6,
para. 6, line 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35
U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over YUAN as applied above in view of US-9911799-B2 by Cho (hereinafter CHO).
YUAN discloses the display device of claim 9.
YUAN does not disclose wherein a rim of the substrate, which faces a respective data
line is generally parallel for portions of its length to the respective data line.
CHO teaches wherein a rim of the substrate, which faces a respective data line is
generally parallel for portions of its length to the respective data line (Fig. 2/DL are parallel to
left and right edges of 10a). It is well-known in the art to arrange the pixels (Fig. 2/EP, col. 7 line 31) in an orthogonal array parallel to edges of the display panel. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the parallel data lines of CHO into the display panel of YUAN to get the best display effect.
Claims 13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over YUAN as applied above.
Claim 13. YUAN discloses the display device of claim 1.
YUAN does not disclose wherein the conductive oxide layer is a transparent oxide
semiconductor layer.
YUAN does teach the use of ZnO (which is transparent), among others, as a transparent
semiconducting layer (Fig. 2/11, p.9, para. 9, lines 1-2). It is a matter of simple substitution to
provide a semiconducting transparent oxide layer for a conducting one, to obtain the predictable
result of a charge-transporting material with transparency (see MPEP § 2141 (III)). Thus, it
would have been obvious to one of ordinary skill in the art before the effective filing date of the
instant application to incorporate the transparent semiconductor of Fig. 2/11 into the substrate 2
of Fig. 2 to combine transparency and electrical conduction.
Claim 21. YUAN discloses the display device of claim 19.
YUAN does not disclose wherein each substrate is comprised of a semiconductor oxide
layer.
YUAN does not disclose wherein each substrate is comprised of a semiconductor oxide
layer. YUAN does teach the use of ZnO (which is transparent), among others, as a transparent
semiconducting layer (Fig. 2/11, p.9, para. 9, lines 1-2). It is a matter of simple substitution to
provide a semiconducting transparent oxide layer for a conducting one, to obtain the predictable
result of a charge-transporting material with transparency (see MPEP § 2141 (III)). Thus, it
would have been obvious to one of ordinary skill in the art before the effective filing date of the
instant application to incorporate the transparent semiconductor of Fig. 2/11 into the substrate 2
of Fig. 2 to combine transparency and electrical conduction.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over YUAN as applied above in view of US-8748889-B2 by Sasaki (hereinafter SASAKI).
YUAN discloses the display device of claim 19.
YUAN does not disclose wherein the base layer is transparent polarizing plate.
SASAKI teaches wherein the base layer is transparent polarizing plate (col. 19, lines 50-
51). There is a motivation to provide an anti-reflection property to the device so as to reduce
glare (col. 21, lines 25-26). Thus, it would have been obvious to one of ordinary skill in the art
before the effective filing date of the instant application to incorporate the polarizing substrate of
SASAKI into the display device of YUAN to improve the display effect.
Response to Arguments
Applicant's arguments filed 09/11/25 have been fully considered but they are not persuasive.
Applicant’s only arguments are as follows: The Office Action cites capacitor electrode (2 ) of Yuan (CN ‘686) as allegedly a conductive oxide. However, Yuan does not teach the electrode (2) is transparent.
Examiner’s responses are as follows: Yuan explicitly discloses the material of (first) capacitor electrode (2) may be a metal oxide of the like, the material can be transparent material (see at least see at least p. 7, para. 2 of the attached translated description).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOAN TON whose telephone number is (571)272-2303. The examiner can normally be reached M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool.
To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOAN TON/Supervisory Patent Examiner, Art Unit 2882