DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendments Applicant’s amendments filed on 3/5/2026 have been entered. Response to Arguments Applicant’s arguments regarding Claims 1-14 have been fully considered and are persuasive. Therefore, the prior art rejections of Claims 1-14 have been withdrawn. However, a new ground of rejection, which was necessitated by Applicant’s amendments has been found and now follows. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 , and 10- 1 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al (US 2022/0384311). Regarding Claim 1, Oh et al discloses a semiconductor device (NFET and PFET [0055]-[0056] Fig 8 ) , comprising: a first source/drain (first source/drain 160 [0057] of the first active region AR111 [0055] Fig 8 ) of a first semiconductor device (device in region AR11 Fig 8 ) ; a second source/drain (first source/drain 160 [0055] of the third active region AR12 [0056] Fig 8 ) of a second semiconductor device (device in region AR12 Fig 8 ) ; a source/drain contact (first source/drain contact CA1 [0078] Fig 8 ) adjoining a first side of the first source/drain (160 AR11 Fig 8 ) ; a frontside (frontside wiring structure FS [0027] Fig 8 ) via (shown in annotated Fig 8 ) adjoining the source/drain contact (CA1 Fig 8 ) ; a backside electric contact (first power wiring PW11 that is place d inside the first element separation trenches 100t1 [0133] Fig 8 ) adjoining a first side of the second source/drain (160 Ar12 Fig 8 ) , wherein the backside electric contact (PW11 in 100t1 Fig 8 ) is on a side opposite the source/drain contact (CA1 Fig 8 ) ; a conductive alignment region (region of first through via TV1 [0131] Fig 8 ) having a vertical length that extends from a back- end-of-line (BEOL) side (region of backside wiring structure BS [0027] and portion of substrate 100 [0028] shown in annotated Fig 8 ) to a backside power delivery network (BSPDN) side (region of backside wiring patterns BM3 [0094] Fig 8 ), a backside interconnect (first super via pattern SV1 [0094] Fig 8 ) electrically connected to the conductive alignment region (region of TV1 Fig 8 ) , wherein the backside interconnect (SV1 Fig 8 ) is on a same side of the first source/drain (160 AR11 Fig 8 ) and the second source/drain (160 AR12) as the backside electric contact (PW11 in 100t1 Fig 8 ) ; and an alignment region via (shown in annotated Fig 8 ) electrically connected to the conductive alignment region (region of TV1 Fig 8 ) , wherein the alignment region via (shown in annotated Fig 8 ) is on a same side of the first source/drain (160 AR11 Fig 8 ) and the second source/drain (160 AR12 Fig 8 ) as the source/drain contact and frontside (FS region Fig 8 ) via (shown in annotated Fig 8 ) . Regarding Claim 10, Oh et al discloses a semiconductor device (NFET and PFET [0055]-[0056] Fig 2) , comprising: a dielectric cover layer (interlayer insulating films 110 and 210 [0071] Fig 2) on an interlayer dielectric (ILD) layer (inter-wiring insulating films 311 and 313 [0073] Fig 2) ; an isolation region (field insulating film 105 [0071] and side portions of through insulating film 194 [00 111 ] Fig 2) on the dielectric cover layer (1 10 and 210 Fig 2) ; a backside ILD layer (inter-wiring insulating films 322 and 324 [0094] Fig 2) on the isolation region ( side portions of 1 94 and 105 Fig 2) ; an alignment region via (shown in annotated Fig 2) in the interlayer dielectric (ILD) layer (311 and 313) ; a conductive alignment region (region of first through via TV1 [0131] Fig 2) in the dielectric cover layer (110 and 210 Fig 2) having a vertical length that extends from a back- end-of-line (BEOL) side (region of backside wiring structure BS [0027] and portion of substrate 100 [0028] shown in annotated Fig 2) to a backside power delivery network (BSPDN) side (region of backside wiring patterns BM3 [0094] Fig 2), wherein the conductive alignment region (region of TV1 Fig 2) is on and in electrical contact with the alignment region via (shown in annotated Fig 2) ; a metallization dielectric layer (inter-wiring insulating films 321, 323, 325 [0094] Fig 2) on the backside ILD layer (322 and 324 Fig 2) ; and a backside interconnect (first super via pattern SV1 [0094] Fig 2) in the metallization dielectric layer (321, 323, 325 Fig 2) , wherein the backside interconnect (SV1 Fig 2) is on and in electrical contact with the conductive alignment region (region of TV1 Fig 2) . Regarding Claim 11, Oh et al discloses the limitations of claim 10 as explained above. Oh et al further discloses further comprising a plurality of semiconductor devices (device in region AR11 and device in region AR12 Fig 2) in the dielectric cover layer (110 and 210 Fig 2) . Regarding Claim 12, Oh et al discloses the limitations of claim 11 as explained above. Oh et al further discloses further comprising a first source/drain (first source/drain 160 [0057] of the first active region AR111 [0055] Fig 2) of a first semiconductor device (device in region AR11 Fig 2) of the plurality of semiconductor devices (device in region AR11 and device in region AR12 Fig 2) , and a source/drain contact (first source/drain contact CA1 [0078] Fig 2) adjoining a first side of the first source/drain (first source/drain 160 [0057] of the first active region AR111 [0055] Fig 2) . Regarding Claim 13, Oh et al discloses the limitations of claim 12 as explained above. Oh et al further discloses further comprising a second source/drain (first source/drain 160 [0055] of the third active region AR12 [0056] Fig 2) of a second semiconductor device (device in region AR12 Fig 2) of the plurality of semiconductor devices (device in region AR11 and device in region AR12 Fig 2) , and a backside electric contact (first power wiring PW11 that is place d inside the first element separation trenches 100t1 [0133] Fig 2) adjoining the second source/drain (160 AR12 Fig 2) , wherein the backside electric contact (PW11 in 100t1 Fig 2) is on a side opposite the source/drain contact (first source/drain contact CA1 [0078] Fig 2) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claim s 2 - 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al (US 2022/0384311) in view of Chiang et al (US 2022/0367462). Regarding Claim 2, Oh et al discloses the limitations of claim 1 as explained above. Oh et al does not directly disclose further comprising a sacrificial plug adjoining the first source/drain of the first semiconductor device, wherein the sacrificial plug is on an opposite side of the first source/drain from the source/drain contact. Chiang et al, in the related art of semiconductor devices that include FET transistors, discloses further comprising a sacrificial plug (semiconductor layer 239 [0071] Fig 16B) adjoining the source/drain (source/drain features 260 [0047]) , wherein the sacrificial plug (239) is on an opposite side of the source/drain (260) from the source/drain contact (conductive features 366 [0065]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh et al to include a sacrificial plug as taught by Chiang et al in order to remove it during etching and form the tranches for backside vias [0071]. Further, a person of ordinary skill in the art would have recognized that having a sacrificial plug allows for other portions of the device to be formed prior to forming the trench, and having a backside source contact in the trench is advantageous for providing more electrical function when connected to the BEOL region of the device while meeting smaller size parameters (see MPEP 2143.I(D)). T he combination of Oh et al and Chiang et al now discloses further comprising a sacrificial plug (semiconductor layer 239 [0071] Fig 16B Chiang et al) adjoining the first source/drain (260 Chiang et al ) of the first semiconductor device (device in region AR11 Fig 8 Oh et al); wherein the sacrificial plug (239 Chiang et al) is on an opposite side of the first source/drain (260 Chiang et al ) from the source/drain contact (first source/drain contact CA1 [0078] Fig 8 Oh et al ). Regarding Claim 3, the combination of Oh et al and Chiang et al discloses the limitations of claim 2 as explained above. The combination of Oh et al and Chiang et al further discloses further comprising a lower conductive line (first power wiring PW11 [0133] Oh et al ) electrically connected to the frontside via (shown in annotated Fig 8 Oh et al ) , and a metallization layer via (backside via pattern BV2 [0094] Fig 8 Oh et al) electrically connected to the backside electric contact (first power wiring PW11 that is place d inside the first element separation trenches 100t1 [0133] Fig 8 Oh et al) . Regarding Claim 4 , the combination of Oh et al and Chiang et al discloses the limitations of claim 3 as explained above. The combination of Oh et al and Chiang et al further discloses further comprising an upper level metal line (backside wiring pattern BM1 [0094] Fig 8 Oh et al) electrically connected to the backside interconnect (first super via pattern SV1 [0094] Fig 8 Oh et al) , wherein the upper level metal line (BM1 Fig 8 Oh et al) is configured to provide a voltage to the backside interconnect (SV1 Fig 8 Oh et al) . Regarding Claim 5 , the combination of Oh et al and Chiang et al discloses the limitations of claim 4 as explained above. The combination of Oh et al and Chiang et al further discloses further comprising a backside ILD layer (inter-wiring insulating films 322 and 324 [0094] Fig 4 Oh et al) on isolation regions ( field insulating film 105 [0071] and side portions of through insulating film 194 [00111] Fig 8 Oh et al) , and a metallization dielectric layer (inter-wiring insulating films 321, 323, 325 [0094] Fig 8 Oh et al) on the backside ILD layer (322 and 324 Fig 8 Oh et al) , wherein the backside electric contact ( first power wiring PW11 that is place d inside the first element separation trenches 100t1 [0133] Fig 8 Oh et al) is in the backside ILD layer (322 and 324 Fig 8 Oh et al) , and the backside interconnect (first super via pattern SV1 [0094] Fig 8 Oh et al) is in the metallization dielectric layer (321, 323, 325 Fig 8 Oh et al) . Regarding Claim 6, the combination of Oh et al and Chiang et al discloses the limitations of claim 5 as explained above. The combination of Oh et al and Chiang et al further discloses further comprising metallization layer vias (backside via patterns BV1 and BV2 [0094] Fig 8 Oh et al) and metallization layer lines (backside wiring patterns BM1, BM2, BM3 Fig 8 Oh et al) in the metallization dielectric layer (321, 323, 325 Fig 8 Oh et al) , wherein on of the metallization layer vias (BV1 and BV2 Fig 8 Oh et al) and metallization layer lines is on and in electrical contact with the backside electric contact (first power wiring PW11, PW12, PW21, and PW22 that is place d inside the first element separation trenches 100t1 and 100t2 [0133] Fig 8 Oh et al) . Regarding Claim 7, the combination of Oh et al and Chiang et al discloses the limitations of claim 6 as explained above. The combination of Oh et al and Chiang et al further discloses wherein the semiconductor devices (device in region AR11, AR12, AR21, AR22, AR23 Fig 8 Oh et al) are transistor devices (transistors [0033] Oh et al) . Regarding Claim 8, the combination of Oh et al and Chiang et al discloses the limitations of claim 7 as explained above. The combination of Oh et al and Chiang et al further discloses further comprising a dielectric cover layer (interlayer insulating films 110 and 210 [0071] Fig 8 Oh et al) on the first semiconductor device (device in region AR11 Fig 8 Oh et al) and the second semiconductor device (device in region AR12 Fig 8 Oh et al) , wherein the source/drain contact (first source/drain contact CA1 [0078] Fig 8 Oh et al) and the conductive alignment region (region of first through via TV1 [0131] Fig 8 Oh et al) is in the dielectric cover layer (interlayer insulating films 110 and 210 [0071] Fig 8 Oh et al) . Regarding Claim 9, the combination of Oh et al and Chiang et al discloses the limitations of claim 8 as explained above. The combination of Oh et al and Chiang et al further discloses further comprising a plurality of isolation regions (field insulating film 105 [0071] and side portions of through insulating film 194 [00111] Fig 8 Oh et al) , wherein the isolation regions (portions of 194 and 105 Fig 8 Oh et al) are on opposite sides of the sacrificial plug (semiconductor layer 239 [0071] Fig 16B Chiang et al) , and on opposite sides of the conductive alignment region (region of first through via TV1 [0131] Fig 8 Oh et al) . Regarding Claim 14, Oh et al discloses the limitations of claim 13 as explained above. Oh et al does not directly disclose further comprising a sacrificial plug adjoining the first source/drain of the first semiconductor device, wherein the sacrificial plug is on an opposite side of the first source/drain from the source/drain contact. Chiang et al, in the related art of semiconductor devices that include FET transistors, discloses further comprising a sacrificial plug (semiconductor layer 239 [0071] Fig 16B) adjoining the source/drain (source/drain features 260 [0047]) , wherein the sacrificial plug (239) is on an opposite side of the source/drain (260) from the source/drain contact (conductive features 366 [0065]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Oh et al to include a sacrificial plug as taught by Chiang et al in order to remove it during etching and form the tranches for backside vias [0071]. Further, a person of ordinary skill in the art would have recognized that having a sacrificial plug allows for other portions of the device to be formed prior to forming the trench, and having a backside source contact in the trench is advantageous for providing more electrical function when connected to the BEOL region of the device while meeting smaller size parameters (see MPEP 2143.I(D)). T he combination of Oh et al and Chiang et al now discloses further comprising a sacrificial plug (semiconductor layer 239 [0071] Fig 16B Chiang et al) adjoining the first source/drain (260 Chiang et al ) of the first semiconductor device (device in region AR11 Fig 2 Oh et al); wherein the sacrificial plug (239 Chiang et al) is on an opposite side of the first source/drain (260 Chiang et al ) from the source/drain contact (first source/drain contact CA1 [0078] Fig 2). Related Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhang et al (US 2021/0320122 ) which discloses a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view [ 0006 ], and THEN et al (US 2019/0198627 ) which discloses the enabling of the reduction of capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer [ 0009 ]. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT DAVID PAUL SEDOROOK whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4158 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT Monday - Friday 7:30 am -5pm . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.P.S./ Examiner, Art Unit 2812 /William B Partridge/ Supervisory Patent Examiner, Art Unit 2812