DETAILED ACTION
Claims 1-11 are presented for examination. Claims 1, 6, 7, and 9-11 stand currently amended.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Finality of Office Action
The following is a brief summary description of new ground(s) of rejection (if any) and the reason why those new ground(s) are made necessary by this amendment:
No new grounds of rejection are presented herein.
Response to Arguments
Applicant's remarks filed 31 March 2026 have been fully considered and Examiner’s response is as follows:
Applicant remarks page 9 argues:
It is respectfully submitted, however, that Liu does not disclose or suggest the features recited in claim 1 with respect to causing a value of a first resistance, which is connected between a second electrode and a fourth electrode, to change according to a value of a first voltage between a first electrode and the second electrode.
Examiner’s rejection expressly states “Liu does not explicitly disclose a resistance between the second electrode (e.g. source) and the fourth electrode (e.g. field plate); however, in analogous art of MOSFETs, Kondo figure 2 shows” the limitation. Applicant’s argument here addressed to Liu individually and fails to discuss the combination of references upon which Examiner’s rejection is based. In particular, Applicant’s argument fails to traverse or even discuss Kondo figure 2 of which Examiner has relied.
Claim Rejections - 35 USC § 112
Claim 7 has been appropriately corrected. Accordingly, Examiner's rejection of claims 7-8 under § 112 is withdrawn.
Claim Rejections - 35 USC § 101
Claim 10 has been appropriately corrected. Accordingly, Examiner's rejection of claim 10 under § 101 is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6, and 9-11
Claims 1-4, 6, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, T., et al. “Modeling and Analysis of SiC MOSFET Switching Oscillations” IEEE J. Emerging & Selected Topics in Power Electronics, vol. 4, no. 3 (2016) [herein “Liu”] in view of US patent 9,947,751 B2 Kobayashi, et al. [herein “Kobayashi”] and US patent 12,328,925 B2 Kondo [herein “Kondo”].
Claim 1 recites “1. A simulation method of a semiconductor device.” Liu title discloses “Modeling and Analysis of SiC MOSFET Switching Oscillations.” Modeling and analysis of a SiC MOSFET is a simulation of a semiconductor device. Liu abstract further discloses “Both circuit simulation and experimental measurement are carried out to validate these simple equivalent circuit models.”
Claim 1 further recites “the semiconductor device including: a first electrode; a second electrode; a semiconductor part located between the first electrode and the second electrode; an insulating member located inside the semiconductor part; a third electrode located inside the insulating member; and a fourth electrode located between the first electrode and the third electrode and located inside the insulating member.” Liu title discloses “SiC MOSFET.”
But Liu does not explicitly disclose the particular structure of a MOSFET semiconductor; however, in analogous art of MOSFETs, Kobayashi column 4 lines 29-41 teaches:
As illustrated in FIG. 1, the semiconductor device 100 includes an n- type (first conductivity type) semiconductor region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n+ type source region 3 (third semiconductor region), an n+ type drain region 4, a gate electrode 10, a field plate electrode (hereinafter, referred to as FP electrode) 20 (first electrode), an insulating part 31 (first insulating part), an insulating part 32 (second insulating part), an insulating part 33, a gate insulating part 35, a drain electrode 40, and a source electrode 41 (second electrode).
The drain electrode 40 is provided at a lower surface of the semiconductor device 100.
The drain electrode (40) corresponds with a claimed first electrode.
The source electrode (41) (second electrode) corresponds with a claimed second electrode.
The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) combined with adjoining p-n junction (2-3) corresponds with a claimed semiconductor part located between the first electrode and the second electrode.
The insulating part 31 (first insulating part) corresponds with an insulating member located inside the semiconductor part.
The gate electrode (10) corresponds with a claimed third electrode located inside the insulating member.
The field plate electrode (hereinafter, referred to as FP electrode) 20 corresponds with a claimed fourth electrode located between the first electrode (e.g. drain) and third electrode (e.g. gate) and inside the insulating member (e.g. protective film).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu and Kobayashi. One having ordinary skill in the art would have found motivation to use a particular SiC MOSFET into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “a semiconductor device in which a self-turning ON phenomenon is suppressed.” See Kobayashi column 3 lines 16-18.
Claim 1 further recites “the semiconductor part including: a first semiconductor layer connected to the first electrode, the first semiconductor layer being of a first conductivity type.” See Kobayashi column 4 lines 29-41. The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) corresponds a first semiconductor layer connected to the first electrode (e.g. drain) of a first conductivity type. An n-type is a first conductivity type.
Claim 1 further recites “a second semiconductor layer connected to the second electrode, the second semiconductor layer being of the first conductivity type.” Kobayashi column 4 lines 33-34 teach “an n+ type source region 3 (third semiconductor region)” which corresponds with a second semiconductor layer connected to the second electrode (source) of the same n-type first conductivity type.
Claim 1 further recites “and a third semiconductor layer contacting the first and second semiconductor layers, the third semiconductor layer being of a second conductivity type.” Kobayashi column 4 lines 31-33 teach “a p-type (second conductivity type) base region 2 (second semiconductor region).” The p-type base region (2) corresponds with a third semiconductor layer contacting the first and second semiconductor layers (e.g. 1 and 3 of Kobayashi figure 1). The p-type conductivity is a second conductivity type.
Claim 1 further recites “and the method comprising: causing a value of a first resistance to change according to a value of a first voltage between the first electrode and the second electrode, the first resistance being connected between the second electrode and the fourth electrode.” Liu page 748 right column discloses “MOSFET capacitances
C
G
D
,
C
G
S
, and
C
D
S
are voltage-dependent and nonlinear in nature, and their values can be obtained from the device datasheet.” Liu page 748 section III discloses “Accordingly, for the turn-ON process, the capacitance values used for the calculation are taken when
V
D
S
is around zero. During turn-OFF process, the capacitance values are taken when
V
D
S
equals to the dc power supply voltage.” The drain-source voltage (
V
D
S
) being different values is the corresponding calculations changing according to a first voltage. Here, the
V
D
S
is a first voltage.
Liu page 749 left column second paragraph discloses:
The development of the equivalent circuit is intended to model VDS oscillations during turn-ON and turn-OFF. For turn-ON, by treating the switch as a resistor, the voltage across this equivalent resistor can approximated to be VDS.
Liu page 749 right column teaches:
The turn-ON equivalent resistance is then calculated
R
e
q
1
=
R
e
q
O
N
+
R
D
S
O
N
These resistances corresponding to whether it is ON or OFF is the resistance values depend upon the voltage at either “around zero” or voltage at equal to the dc power supply voltage. See Liu page 748 section III and cited immediately above.
But Liu does not explicitly disclose a resistance between the second electrode (e.g. source) and the fourth electrode (e.g. field plate); however, in analogous art of MOSFETs, Kondo figure 2 shows an equivalent circuit diagram for a semiconductor device with a field plate. Kondo figure 2 shows “Rfp” between the field plate (FP) and source. The resistance Rfp corresponds with a resistance between a second electrode (e.g. source) and the fourth electrode (e.g. field plate).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu, Kobayashi, and Kondo. One having ordinary skill in the art would have found motivation to use a field plate into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “By controlling the displacement current, the soft recovery of the semiconductor device 100 is controlled.” See Kondo column 5 lines 31-33.
Claim 2 further recites “2. The method according to claim 1, wherein the value of the first resistance increases as the value of the first voltage increases.” Kondo column 5 lines 51-52 teach “When the resistance (Rfp) value is large, the voltage Vds is reduced only during the recovery period.” This is the opposite of the relationship between Rfp and Vds claimed here.
However, Liu page 748 last paragraph discloses “because it is reverse-biased and is blocking voltage, the junction capacitance CJ is charged.” Accordingly, for a reverse-biased MOSFET a person of ordinary skill in the art would understand this relationship is inverted and thus the value of the first resistance (e.g. Rfp) would increase along with and increase in the first voltage (e.g. Vds).
Claim 3 further recites “3. The method according to claim 1, wherein the value of the first resistance is calculated by a formula including the first voltage.” Liu page 749 left column second paragraph discloses:
The development of the equivalent circuit is intended to model VDS oscillations during turn-ON and turn-OFF. For turn-ON, by treating the switch as a resistor, the voltage across this equivalent resistor can approximated to be VDS.
Liu page 749 right column teaches:
The turn-ON equivalent resistance is then calculated
R
e
q
1
=
R
e
q
O
N
+
R
D
S
O
N
The voltage across the equivalent resistor being approximated as VDS corresponds in converse with the resistance equation of the equivalent resistor being proportional to
R
D
S
O
N
as an equation approximated to be proportional to VDS. Accordingly, this equation for the equivalent resistance corresponds with a formulae including the first voltage VDS.
Claim 4 further recites “4. The method according to claim 3, wherein the formula is a quadratic equation.” Liu page 749 right column below equation (8) discloses “This second-order circuit will present voltage or current ringing along with the energy exchange process. Eventually, after a certain amount of time, all the energies will be dissipated in the equivalent resistor.” A second-order circuit corresponds with a quadratic because quadratics are second order.
Claim 6 further recites “6. The method according to claim 1, wherein: the value of the first resistance that corresponds to the value of the first voltage is acquired by referring to a data structure, and the data structure includes a correspondence between the value of the first voltage and the value of the first resistance.” Liu page 748 right column second paragraph discloses “MOSFET capacitances CGD, CGS, and CDS are voltage-dependent and nonlinear in nature, and their values can be obtained from the device datasheet.” The device datasheet is a data structure to determine corresponding values. The values being “voltage-dependent” is the values having a correspondence with the first voltage. Liu page 749 right column discloses “For this second-order equivalent circuit model, all the three components can be either obtained from the datasheet or calculated from provided equations.”
But Liu does not explicitly disclose a resistance between the second electrode (e.g. source) and the fourth electrode (e.g. field plate); however, in analogous art of MOSFETs, Kondo figure 2 shows an equivalent circuit diagram for a semiconductor device with a field plate. Kondo figure 2 shows “Rfp” between the field plate (FP) and source. The resistance Rfp corresponds with a resistance between a second electrode (e.g. source) and the fourth electrode (e.g. field plate).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu, Kobayashi, and Kondo. One having ordinary skill in the art would have found motivation to use a field plate into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “By controlling the displacement current, the soft recovery of the semiconductor device 100 is controlled.” See Kondo column 5 lines 31-33. As combined, it would have been obvious to obtain such a Rfp resistance value from a datasheet as taught by Liu.
Claim 9 recites “9. A simulation device of a semiconductor device.” Liu title discloses “Modeling and Analysis of SiC MOSFET Switching Oscillations.” Modeling and analysis of a SiC MOSFET is a simulation of a semiconductor device. Liu abstract further discloses “Both circuit simulation and experimental measurement are carried out to validate these simple equivalent circuit models.”
Claim 9 further recites “the semiconductor device including: a first electrode; a second electrode; a semiconductor part located between the first electrode and the second electrode; an insulating member located inside the semiconductor part; a third electrode located inside the insulating member; and a fourth electrode located between the first electrode and the third electrode and located inside the insulating member.” Liu title discloses “SiC MOSFET.”
But Liu does not explicitly disclose the particular structure of a MOSFET semiconductor; however, in analogous art of MOSFETs, Kobayashi column 4 lines 29-41 teaches:
As illustrated in FIG. 1, the semiconductor device 100 includes an n- type (first conductivity type) semiconductor region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n+ type source region 3 (third semiconductor region), an n+ type drain region 4, a gate electrode 10, a field plate electrode (hereinafter, referred to as FP electrode) 20 (first electrode), an insulating part 31 (first insulating part), an insulating part 32 (second insulating part), an insulating part 33, a gate insulating part 35, a drain electrode 40, and a source electrode 41 (second electrode).
The drain electrode 40 is provided at a lower surface of the semiconductor device 100.
The drain electrode (40) corresponds with a claimed first electrode.
The source electrode (41) (second electrode) corresponds with a claimed second electrode.
The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) combined with adjoining p-n junction (2-3) corresponds with a claimed semiconductor part located between the first electrode and the second electrode.
The insulating part 31 (first insulating part) corresponds with an insulating member located inside the semiconductor part.
The gate electrode (10) corresponds with a claimed third electrode located inside the insulating member.
The field plate electrode (hereinafter, referred to as FP electrode) 20 corresponds with a claimed fourth electrode located between the first electrode (e.g. drain) and third electrode (e.g. gate) and inside the insulating member (e.g. protective film).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu and Kobayashi. One having ordinary skill in the art would have found motivation to use a particular SiC MOSFET into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “a semiconductor device in which a self-turning ON phenomenon is suppressed.” See Kobayashi column 3 lines 16-18.
Claim 9 further recites “the semiconductor part including: a first semiconductor layer connected to the first electrode, the first semiconductor layer being of a first conductivity type.” See Kobayashi column 4 lines 29-41. The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) corresponds a first semiconductor layer connected to the first electrode (e.g. drain) of a first conductivity type. An n-type is a first conductivity type.
Claim 9 further recites “a second semiconductor layer connected to the second electrode, the second semiconductor layer being of the first conductivity type.” Kobayashi column 4 lines 33-34 teach “an n+ type source region 3 (third semiconductor region)” which corresponds with a second semiconductor layer connected to the second electrode (source) of the same n-type first conductivity type.
Claim 9 further recites “and a third semiconductor layer contacting the first and second semiconductor layers, the third semiconductor layer being of a second conductivity type.” Kobayashi column 4 lines 31-33 teach “a p-type (second conductivity type) base region 2 (second semiconductor region).” The p-type base region (2) corresponds with a third semiconductor layer contacting the first and second semiconductor layers (e.g. 1 and 3 of Kobayashi figure 1). The p-type conductivity is a second conductivity type.
Claim 9 further recites “and the simulation device causing a value of a first resistance to change according to a value of a first voltage between the first electrode and the second electrode, the first resistance being connected between the second electrode and the fourth electrode.” Liu page 748 right column discloses “MOSFET capacitances
C
G
D
,
C
G
S
, and
C
D
S
are voltage-dependent and nonlinear in nature, and their values can be obtained from the device datasheet.” Liu page 748 section III discloses “Accordingly, for the turn-ON process, the capacitance values used for the calculation are taken when
V
D
S
is around zero. During turn-OFF process, the capacitance values are taken when
V
D
S
equals to the dc power supply voltage.” The drain-source voltage (
V
D
S
) being different values is the corresponding calculations changing according to a first voltage. Here, the
V
D
S
is a first voltage.
Liu page 749 left column second paragraph discloses:
The development of the equivalent circuit is intended to model VDS oscillations during turn-ON and turn-OFF. For turn-ON, by treating the switch as a resistor, the voltage across this equivalent resistor can approximated to be VDS.
Liu page 749 right column teaches:
The turn-ON equivalent resistance is then calculated
R
e
q
1
=
R
e
q
O
N
+
R
D
S
O
N
These resistances corresponding to whether it is ON or OFF is the resistance values depend upon the voltage at either “around zero” or voltage at equal to the dc power supply voltage. See Liu page 748 section III and cited immediately above.
But Liu does not explicitly disclose a resistance between the second electrode (e.g. source) and the fourth electrode (e.g. field plate); however, in analogous art of MOSFETs, Kondo figure 2 shows an equivalent circuit diagram for a semiconductor device with a field plate. Kondo figure 2 shows “Rfp” between the field plate (FP) and source. The resistance Rfp corresponds with a resistance between a second electrode (e.g. source) and the fourth electrode (e.g. field plate).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu, Kobayashi, and Kondo. One having ordinary skill in the art would have found motivation to use a field plate into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “By controlling the displacement current, the soft recovery of the semiconductor device 100 is controlled.” See Kondo column 5 lines 31-33.
Claim 10 recites “10. A computer storing a simulation program of a semiconductor device.” Liu title discloses “Modeling and Analysis of SiC MOSFET Switching Oscillations.” Modeling and analysis of a SiC MOSFET is a simulation of a semiconductor device. Liu abstract further discloses “Both circuit simulation and experimental measurement are carried out to validate these simple equivalent circuit models.”
Claim 10 further recites “the semiconductor device including: a first electrode; a second electrode; a semiconductor part located between the first electrode and the second electrode; an insulating member located inside the semiconductor part; a third electrode located inside the insulating member; and a fourth electrode located between the first electrode and the third electrode and located inside the insulating member.” Liu title discloses “SiC MOSFET.”
But Liu does not explicitly disclose the particular structure of a MOSFET semiconductor; however, in analogous art of MOSFETs, Kobayashi column 4 lines 29-41 teaches:
As illustrated in FIG. 1, the semiconductor device 100 includes an n- type (first conductivity type) semiconductor region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n+ type source region 3 (third semiconductor region), an n+ type drain region 4, a gate electrode 10, a field plate electrode (hereinafter, referred to as FP electrode) 20 (first electrode), an insulating part 31 (first insulating part), an insulating part 32 (second insulating part), an insulating part 33, a gate insulating part 35, a drain electrode 40, and a source electrode 41 (second electrode).
The drain electrode 40 is provided at a lower surface of the semiconductor device 100.
The drain electrode (40) corresponds with a claimed first electrode.
The source electrode (41) (second electrode) corresponds with a claimed second electrode.
The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) combined with adjoining p-n junction (2-3) corresponds with a claimed semiconductor part located between the first electrode and the second electrode.
The insulating part 31 (first insulating part) corresponds with an insulating member located inside the semiconductor part.
The gate electrode (10) corresponds with a claimed third electrode located inside the insulating member.
The field plate electrode (hereinafter, referred to as FP electrode) 20 corresponds with a claimed fourth electrode located between the first electrode (e.g. drain) and third electrode (e.g. gate) and inside the insulating member (e.g. protective film).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu and Kobayashi. One having ordinary skill in the art would have found motivation to use a particular SiC MOSFET into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “a semiconductor device in which a self-turning ON phenomenon is suppressed.” See Kobayashi column 3 lines 16-18.
Claim 10 further recites “the semiconductor part including: a first semiconductor layer connected to the first electrode, the first semiconductor layer being of a first conductivity type.” See Kobayashi column 4 lines 29-41. The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) corresponds a first semiconductor layer connected to the first electrode (e.g. drain) of a first conductivity type. An n-type is a first conductivity type.
Claim 10 further recites “a second semiconductor layer connected to the second electrode, the second semiconductor layer being of the first conductivity type.” Kobayashi column 4 lines 33-34 teach “an n+ type source region 3 (third semiconductor region)” which corresponds with a second semiconductor layer connected to the second electrode (source) of the same n-type first conductivity type.
Claim 10 further recites “and a third semiconductor layer contacting the first and second semiconductor layers, the third semiconductor layer being of a second conductivity type.” Kobayashi column 4 lines 31-33 teach “a p-type (second conductivity type) base region 2 (second semiconductor region).” The p-type base region (2) corresponds with a third semiconductor layer contacting the first and second semiconductor layers (e.g. 1 and 3 of Kobayashi figure 1). The p-type conductivity is a second conductivity type.
Claim 10 further recites “and the simulation program causing the computer to acquire a value of a first resistance based on a first voltage between the first electrode and the second electrode, the first resistance being connected between the second electrode and the fourth electrode.” Liu page 748 right column discloses “MOSFET capacitances
C
G
D
,
C
G
S
, and
C
D
S
are voltage-dependent and nonlinear in nature, and their values can be obtained from the device datasheet.” Liu page 748 section III discloses “Accordingly, for the turn-ON process, the capacitance values used for the calculation are taken when
V
D
S
is around zero. During turn-OFF process, the capacitance values are taken when
V
D
S
equals to the dc power supply voltage.” The drain-source voltage (
V
D
S
) being different values is the corresponding calculations changing according to a first voltage. Here, the
V
D
S
is a first voltage.
Liu page 749 left column second paragraph discloses:
The development of the equivalent circuit is intended to model VDS oscillations during turn-ON and turn-OFF. For turn-ON, by treating the switch as a resistor, the voltage across this equivalent resistor can approximated to be VDS.
Liu page 749 right column teaches:
The turn-ON equivalent resistance is then calculated
R
e
q
1
=
R
e
q
O
N
+
R
D
S
O
N
These resistances corresponding to whether it is ON or OFF is the resistance values depend upon the voltage at either “around zero” or voltage at equal to the dc power supply voltage. See Liu page 748 section III and cited immediately above.
But Liu does not explicitly disclose a resistance between the second electrode (e.g. source) and the fourth electrode (e.g. field plate); however, in analogous art of MOSFETs, Kondo figure 2 shows an equivalent circuit diagram for a semiconductor device with a field plate. Kondo figure 2 shows “Rfp” between the field plate (FP) and source. The resistance Rfp corresponds with a resistance between a second electrode (e.g. source) and the fourth electrode (e.g. field plate).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu, Kobayashi, and Kondo. One having ordinary skill in the art would have found motivation to use a field plate into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “By controlling the displacement current, the soft recovery of the semiconductor device 100 is controlled.” See Kondo column 5 lines 31-33.
Claim 11 recites “11. A data structure used in a simulation of a semiconductor device.” Liu title discloses “Modeling and Analysis of SiC MOSFET Switching Oscillations.” Modeling and analysis of a SiC MOSFET is a simulation of a semiconductor device. Liu abstract further discloses “Both circuit simulation and experimental measurement are carried out to validate these simple equivalent circuit models.”
Liu page 749 right column discloses “For this second-order equivalent circuit model, all the three components can be either obtained from the datasheet or calculated from provided equations.” The datasheet is a data structure used in this simulation and analysis.
Claim 11 further recites “the semiconductor device including: a first electrode; a second electrode; a semiconductor part located between the first electrode and the second electrode; an insulating member located inside the semiconductor part; a third electrode located inside the insulating member; and a fourth electrode located between the first electrode and the third electrode and located inside the insulating member.” Liu title discloses “SiC MOSFET.”
But Liu does not explicitly disclose the particular structure of a MOSFET semiconductor; however, in analogous art of MOSFETs, Kobayashi column 4 lines 29-41 teaches:
As illustrated in FIG. 1, the semiconductor device 100 includes an n- type (first conductivity type) semiconductor region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n+ type source region 3 (third semiconductor region), an n+ type drain region 4, a gate electrode 10, a field plate electrode (hereinafter, referred to as FP electrode) 20 (first electrode), an insulating part 31 (first insulating part), an insulating part 32 (second insulating part), an insulating part 33, a gate insulating part 35, a drain electrode 40, and a source electrode 41 (second electrode).
The drain electrode 40 is provided at a lower surface of the semiconductor device 100.
The drain electrode (40) corresponds with a claimed first electrode.
The source electrode (41) (second electrode) corresponds with a claimed second electrode.
The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) combined with adjoining p-n junction (2-3) corresponds with a claimed semiconductor part located between the first electrode and the second electrode.
The insulating part 31 (first insulating part) corresponds with an insulating member located inside the semiconductor part.
The gate electrode (10) corresponds with a claimed third electrode located inside the insulating member.
The field plate electrode (hereinafter, referred to as FP electrode) 20 corresponds with a claimed fourth electrode located between the first electrode (e.g. drain) and third electrode (e.g. gate) and inside the insulating member (e.g. protective film).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu and Kobayashi. One having ordinary skill in the art would have found motivation to use a particular SiC MOSFET into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “a semiconductor device in which a self-turning ON phenomenon is suppressed.” See Kobayashi column 3 lines 16-18.
Claim 11 further recites “the semiconductor part including: a first semiconductor layer connected to the first electrode, the first semiconductor layer being of a first conductivity type.” See Kobayashi column 4 lines 29-41. The n– type (first conductivity type) semiconductor region (1) (first semiconductor region) corresponds a first semiconductor layer connected to the first electrode (e.g. drain) of a first conductivity type. An n-type is a first conductivity type.
Claim 11 further recites “a second semiconductor layer connected to the second electrode, the second semiconductor layer being of the first conductivity type.” Kobayashi column 4 lines 33-34 teach “an n+ type source region 3 (third semiconductor region)” which corresponds with a second semiconductor layer connected to the second electrode (source) of the same n-type first conductivity type.
Claim 11 further recites “and a third semiconductor layer contacting the first and second semiconductor layers, the third semiconductor layer being of a second conductivity type.” Kobayashi column 4 lines 31-33 teach “a p-type (second conductivity type) base region 2 (second semiconductor region).” The p-type base region (2) corresponds with a third semiconductor layer contacting the first and second semiconductor layers (e.g. 1 and 3 of Kobayashi figure 1). The p-type conductivity is a second conductivity type.
Claim 11 further recites “and the data structure comprising: a value of a first voltage between the first electrode and the second electrode; and a value of a first resistance corresponding to the value of the first voltage, the first resistance being connected between the second electrode and the fourth electrode.” Liu page 749 right column discloses “For this second-order equivalent circuit model, all the three components can be either obtained from the datasheet or calculated from provided equations.” The datasheet is a data structure used in this simulation and analysis.
Liu page 748 right column discloses “MOSFET capacitances
C
G
D
,
C
G
S
, and
C
D
S
are voltage-dependent and nonlinear in nature, and their values can be obtained from the device datasheet.” Liu page 748 section III discloses “Accordingly, for the turn-ON process, the capacitance values used for the calculation are taken when
V
D
S
is around zero. During turn-OFF process, the capacitance values are taken when
V
D
S
equals to the dc power supply voltage.” The drain-source voltage (
V
D
S
) being different values is the corresponding calculations changing according to a first voltage. Here, the
V
D
S
is a first voltage.
Liu page 749 left column second paragraph discloses:
The development of the equivalent circuit is intended to model VDS oscillations during turn-ON and turn-OFF. For turn-ON, by treating the switch as a resistor, the voltage across this equivalent resistor can approximated to be VDS.
Liu page 749 right column teaches:
The turn-ON equivalent resistance is then calculated
R
e
q
1
=
R
e
q
O
N
+
R
D
S
O
N
These resistances corresponding to whether it is ON or OFF is the resistance values depend upon the voltage at either “around zero” or voltage at equal to the dc power supply voltage. See Liu page 748 section III and cited immediately above.
But Liu does not explicitly disclose a resistance between the second electrode (e.g. source) and the fourth electrode (e.g. field plate); however, in analogous art of MOSFETs, Kondo figure 2 shows an equivalent circuit diagram for a semiconductor device with a field plate. Kondo figure 2 shows “Rfp” between the field plate (FP) and source. The resistance Rfp corresponds with a resistance between a second electrode (e.g. source) and the fourth electrode (e.g. field plate).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Liu, Kobayashi, and Kondo. One having ordinary skill in the art would have found motivation to use a field plate into the system of modeling and analysis of SiC MOSFET for the advantageous purpose of “By controlling the displacement current, the soft recovery of the semiconductor device 100 is controlled.” See Kondo column 5 lines 31-33.
Allowable Subject Matter
Claim 5, 7, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
A statement of reasons for the indication of allowable subject matter was previously presented in the office action dated 31 December 2025.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jay B Hann whose telephone number is (571)272-3330. The examiner can normally be reached M-F 10am-7pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Chavez can be reached at (571) 270-1104. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jay Hann/Primary Examiner, Art Unit 2186 30 April 2026
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