DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Objections
Claim 8 objected to because of the following informalities:
Lines 3-4 “an N+ type contact region” should read “the N+ type contact region”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 12, 14 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 12 lines 1-3 and claim 14 lines 1-3 discuss a relationship between a doping concentration of the P+ type shielding layer and a doping concentration of the P+ type contact region. Applicant’s disclosure does not provide support for a doping concentration of the P+ type shielding layer being less than a doping concentration of the P+ type contact region. Doping concentration relationships for other regions are provided by Applicant, but the disclosed relationships do not teach or show possession of a device with a doping concentration of the P+ type shielding layer being less than a doping concentration of the P+ type contact region. Applicant should identify items in the original disclosure that demonstrate possession of a device that fit claims 12 and 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-11, 13, 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. (US-10693002-B2).
Regarding claim 1, Kobayashi discloses a trench gate silicon carbide MOSFET with high reliability (fig. 34, col. 7 lines 51-55), comprising: an N+ type substrate (fig. 34 1, col. 7 lines 60-61); a drain electrode formed below the N+ type substrate (fig. 34 13 below 1, col. 10 lines 54-57); an N- type drift region formed above the N+ type substrate (fig. 34 2 above 1, col. 7 lines 58-59); a trench gate region (fig. 34 7, col. 7 lines 64-67); a gate dielectric layer (fig. 34 8, col. 8 lines 6-7); a first P type region formed above the N- type drift region (annotated fig. 34 P regions within 1P (not P+ or P++ regions) above 2); an N type equivalent resistance region formed above the first P type region (annotated fig. 34 1ER above 1P); an N+ type contact region formed above the N type equivalent resistance region (annotated fig. 34 1N above 1ER); a source electrode formed above an N+ type contact region (annotated fig. 34 12 above N+ regions within 1N); an isolation dielectric region formed above the trench gate region (fig. 34 11 above 7, col. 10 lines 43-45); and a P+ type contact region penetrating the N+ type contact region (fig. 34 23 penetrates N+ regions within 1N, col. 9 lines 20-25), the N type equivalent resistance region (annotated fig. 34 23 penetrates 1ER) and extending to the first P type region (fig. 34 23 extends to P regions within 1P (not P+ or P++ regions).
See annotated fig. 34. First P type region 1P is the portion of the P regions within 1P (not P+ or P++ regions) but the top of region 1P is slightly below the top of the P regions. N+ type contact region 1N is the portion of the N+ regions within 1N. Top of 1N coincides with top of N+ regions and bottom of 1N is slightly above bottom of N+ regions. Equivalent resistance region 1ER is the region between top of 1P/2P and bottom of 1N, including portions of N+, P, NOT INCLUDING portions of P++ or P+. Region 1ER has 2 distinct mirror image portions on left and right of annotated fig. 34. Total width of 1ER is 2 * 1P/2P or 1 * 1N. 1ER overlaps portions of N+ and P between 1P/2P and 1N.
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Annotated fig. 34
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Regarding claim 2, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 1, wherein the P+ type contact region is configured to penetrate the N+ type contact region (annotated fig. 34 23 penetrates N+ regions within 1N…), the N type equivalent resistance region (…1ER…), the first P type region (…P regions within 1P…) and extend to the N- type drift region (…and extends to 2).
def. to – used as a function word to indicate contact or proximity (Merriam-Webster def. 1c)
23 extends in the direction and vicinity of 2.
Regarding claim 3, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 1, wherein a doping concentration of the N type equivalent resistance region is greater than a doping concentration of the N- type drift region and less than a doping concentration of the N+ type contact region (N/P+ > N/P > N/P-, col. 7 lines 17-19).
N type equivalent resistance region includes portions of N+ and P. N+ and P combination will have lower concentration than strict N+ and higher concentration than strict N-.
Regarding claim 4, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 1, further comprising: a current diffusion region between the first P type region and the N- type drift region (fig. 34 3 between P regions within 1P (not P+ or P++ regions) and 2, col. 8 lines 17-19).
Regarding claim 5, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 4, the P+ type contact region is configured to penetrate the N+ type contact region (annotated fig. 34 23 penetrates N+ regions within 1N…), the N type equivalent resistance region (…1ER…) and the first P type region (…P regions within 1P…) and extend to the current diffusion region (…and extends to 3).
Regarding claim 6, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 4, the P+ type contact region is configured to penetrate the N+ type contact region (annotated fig. 34 23 penetrates N+ regions within 1N) and the N type equivalent resistance region (1ER), the first P type region (P regions within 1P), the current diffusion region (3) and extend to the N- type drift region (and extends to 2).
def. to – used as a function word to indicate contact or proximity (Merriam-Webster def. 1c)
23 extends in the direction and vicinity of 2.
Regarding claim 8, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 4, wherein a doping concentration of the current diffusion region (fig. 34 3 (N)) is greater than a doping concentration of the N- type drift region and less than a doping concentration of an N+ type contact region (N/P+ > N/P > N/P-, col. 7 lines 17-19).
Regarding claim 9, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 1, further comprising: a second N type region between the P+ type contact region and the N- type drift region (fig. 34 25 between 23 and 2, col. 31 lines 32-34).
Regarding claim 10, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 9, wherein a doping concentration of the second N type region is greater than a doping concentration of the N- type drift region (N/P+ > N/P > N/P-, col. 7 lines 17-19).
Regarding claim 11, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 1, further comprising: a P+ type shielding layer formed at a bottom of the gate dielectric layer (fig. 34 21 at bottom of 8, col. 8 lines 34-35).
Regarding claim 13, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 1, further comprising: a second P type region formed between the gate dielectric layer and the N type equivalent resistance region (annotated fig. 34 portions of P within 2P formed between 8 and 1ER in direction D); and a P+ type shielding layer formed at a bottom of the gate dielectric layer (annotated fig. 34 21 at bottom of 8, col. 8 lines 34-35).
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Annotated fig. 34
Regarding claim 15, Kobayashi discloses a trench gate silicon carbide MOSFET with high reliability (fig. 34, col. 7 lines 51-55), comprising: an N+ type substrate (fig. 34 1, col. 7 lines 60-61); a drain electrode formed below the N+ type substrate (fig. 34 13 below 1, col. 10 lines 54-57); an N- type drift region formed above the N+ type substrate (fig. 34 2 above 1, col. 7 lines 58-59); a trench gate region (fig. 34 7, col. 7 lines 64-67); a gate dielectric layer (fig. 34 8, col. 8 lines 6-7); a first P type region formed above the N- type drift region (annotated fig. 34 P regions within 1P (not P+ or P++ regions) above 2); an N type equivalent resistance region formed above the first P type region (annotated fig. 34 1ER above 1P); an N+ type contact region formed above the N type equivalent resistance region (annotated fig. 34 1N above 1ER); a source electrode formed above an N+ type contact region (annotated fig. 34 12 above N+ regions within 1N); an isolation dielectric region formed above the trench gate region (fig. 34 11 above 7, col. 10 lines 43-45); and a P+ type contact region penetrating the N+ type contact region (fig. 34 23 penetrates N+ regions within 1N, col. 9 lines 20-25), the N type equivalent resistance region (annotated fig. 34 23 penetrates 1ER) and extending to the first P type region (fig. 34 23 extends to P regions within 1P (not P+ or P++ regions); a second P type region between the gate dielectric layer and the N type equivalent resistance region (annotated fig. 34 portions of P within 2P formed between 8 and 1ER in direction D); a doping concentration of the N type equivalent resistance region is greater than a doping concentration of the N- type drift region and less than a doping concentration of the N+ type contact region; a doping concentration of the second P type region is greater than the doping concentration of the N- type drift region (N/P+ > N/P > N/P-, col. 7 lines 17-19).
See annotated fig. 34. First P type region 1P is the portion of the P regions within 1P (not P+ or P++ regions) but the top of region 1P is slightly below the top of the P regions. N+ type contact region 1N is the portion of the N+ regions within 1N. Top of 1N coincides with top of N+ regions and bottom of 1N is slightly above bottom of N+ regions. Equivalent resistance region 1ER is the region between top of 1P/2P and bottom of 1N. Region 1ER has 2 distinct mirror image portions on left and right of annotated fig. 34. Total width of 1ER is 2 * 1P/2P or 1 * 1N. 1ER overlaps portions of N+, P++, P, and P+ between 1P/2P and 1N.
N type equivalent resistance region includes portions of N+ and P. N+ and P combination will have lower concentration than strict N+ and higher concentration than strict N-.
Regarding claim 16, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 15, wherein the second P type region is formed at vertical sidewalls of a trench gate and is in contact with the first P type region (annotated fig. 34 P regions within 2P (not P+ or P++ regions) formed at vertical sidewalls of 9 and in indirect physical contact with P regions within 1P (not P+ or P++ regions), col. 7 lines 64-65).
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Regarding claim 17, Kobayashi discloses a trench gate silicon carbide MOSFET with high reliability (fig. 34, col. 7 lines 51-55), comprising: an N+ type substrate (fig. 34 1, col. 7 lines 60-61); a drain electrode formed below the N+ type substrate (fig. 34 13 below 1, col. 10 lines 54-57); an N- type drift region formed above the N+ type substrate (fig. 34 2 above 1, col. 7 lines 58-59); a trench gate region (fig. 34 7, col. 7 lines 64-67); a gate dielectric layer (fig. 34 8, col. 8 lines 6-7); a first P type region formed above the N- type drift region (annotated fig. 34 P regions within 1P (not P+ or P++ regions) above 2); an N type equivalent resistance region formed above the first P type region (annotated fig. 34 1ER above 1P); an N+ type contact region formed above the N type equivalent resistance region (annotated fig. 34 1N above 1ER); a source electrode formed above an N+ type contact region (annotated fig. 34 12 above N+ regions within 1N); an isolation dielectric region formed above the trench gate region (fig. 34 11 above 7, col. 10 lines 43-45); and a P+ type contact region penetrating the N+ type contact region (fig. 34 23 penetrates N+ regions within 1N, col. 9 lines 20-25), the N type equivalent resistance region (annotated fig. 34 23 penetrates 1ER) and extending to the first P type region (fig. 34 23 extends to P regions within 1P (not P+ or P++ regions); a second P type region between the gate dielectric layer and the N type equivalent resistance region (annotated fig. 34 portions of P within 2P formed between 8 and 1ER in direction D); a current diffusion region between the first P type region and the N- type drift region (fig. 34 3 between P regions within 1P (not P+ or P++ regions) and 2, col. 8 lines 17-19); a doping concentration of the N type equivalent resistance region is greater than a doping concentration of the N- type drift region and less than a doping concentration that of the N+ type contact region; a doping concentration of the second P type region is greater than the doping concentration of the N- type drift region; a doping concentration of the current diffusion region (N) is greater than the doping concentration of the N- type drift region and less than the doping concentration of the N+ type contact region (N/P+ > N/P > N/P-, col. 7 lines 17-19).
See annotated fig. 34. First P type region 1P is the portion of the P regions within 1P (not P+ or P++ regions) but the top of region 1P is slightly below the top of the P regions. N+ type contact region 1N is the portion of the N+ regions within 1N. Top of 1N coincides with top of N+ regions and bottom of 1N is slightly above bottom of N+ regions. Equivalent resistance region 1ER is the region between top of 1P/2P and bottom of 1N. Region 1ER has 2 distinct mirror image portions on left and right of annotated fig. 34. Total width of 1ER is 2 * 1P/2P or 1 * 1N. 1ER overlaps portions of N+, P++, P, and P+ between 1P/2P and 1N.
N type equivalent resistance region includes portions of N+ and P. N+ and P combination will have lower concentration than strict N+ and higher concentration than strict N-.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US-10693002-B2).
Regarding claim 7, Kobayashi discloses the trench gate silicon carbide MOSFET according to claim 4.
Kobayashi does not explicitly disclose wherein the current diffusion region is only formed on side walls of the gate dielectric layer and is not formed at a bottom of the gate dielectric layer.
Kobayashi discloses positioning the P+ regions 21 and 22 deeper in the device and terminating them within the N- drift region 2 (col. 8 lines 48-53, col. 9 lines 1-6).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to position the P+ regions 21 and 22 deeper within the device and terminate them within the N- drift region 2 (modified fig. 34).
One of ordinary skill in the art would have been motivated to make this modification to prevent the application of high electric field to the gate dielectric layer 8 (col. 9 lines 1-6).
After modification, current diffusion region is no longer formed at a bottom of the gate dielectric layer and only formed on side walls of the gate dielectric layer.
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Modified fig. 34 (rough example of proposed modification)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yen et al. (US-10418476-B2) discloses a silicon carbide semiconductor device with a design meant for improved current density and on-resistance. Xiao et al. (CN-112151619-A, “Xiao_English” included herewith) discloses a silicon carbide semiconductor device with a design meant for improved on-resistance and reduced cost and complexity.
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/A.E./Examiner, Art Unit 2828
/XINNING(Tom) NIU/Primary Examiner, Art Unit 2828