DETAILED ACTION
Claims 1-3 and 5-11 are currently pending.
The previous objection to claim 1 is withdrawn due to Applicant’s amendment.
Response to Arguments
Applicant’s arguments with respect to claims 1-3 and 5-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 5-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “earliest in time” in claim 1 is a relative term which renders the claim indefinite. The term “earliest in time” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Furthermore, claim 1 recites “performing a detection step on the back surface of the wafer before the first semiconductor process is performed”. It is unclear how the first semiconductor process can be performed earliest in time, while the detection step is performed even earlier.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou Chinese Publication 114140425 (hereafter “Zhou”), Phan et al. US Patent 6,724,476 (hereafter “Phan”) and Nakajima et al. US Publication 2014/0227807 (hereafter “Nakajima”).
Referring to claim 1, Zhou discloses a method for detecting the back surface of a wafer, comprising:
providing a wafer, the wafer comprises a front surface and a back surface (Page 3, Preferably, the to-be-detected crystal back image is obtained by scanning the wafer to be detected by the crystal back inspection machine);
performing a plurality of semiconductor processes on the front surface of the wafer, wherein a first one of the plurality of semiconductor processes is defined as a first semiconductor process which is an initial process performed earliest in time (Page 4, the grey value of each process layer is different);
performing a detection step on the back surface of the wafer (Page 2, step S01, obtaining the standard crystal back image after finishing each layer process, the standard crystal back image is a two-dimensional grey scale image), wherein the detection step comprises:
capturing a gray scale map of the back surface of the wafer (Page 2, step S01, obtaining the standard crystal back image after finishing each layer process, the standard crystal back image is a two-dimensional grey scale image);
according to a gray scale deviation of the gray scale map, finding out at least one defect on the back surface of the wafer, and transmitting a plurality of data of the at least one defect back to a system (Page 2, step S05, using conventional detection method to detect each block to be detected obtained in step S03, when a certain to-be-detected block is detected as abnormal, directly judging that the to-be-detected block is abnormal block, and outputting the detection result); and
the system performs a judgment step according to the data of the at least one defect (Page 2, when the grey difference value between the two is greater than or equal to the set grey scale threshold value, finally judging the to-be-detected block is abnormal block, and outputting the detection result).
While Zhou discloses performing a detection step on the back surface of the wafer, Zhou does not disclose expressly performing a detection step on the back surface of the wafer before the first semiconductor process is performed
Phan discloses performing a detection step on the back surface of the wafer before the first semiconductor process is performed (col. 6, lines 22-26, The defect metrology system 120 may inspect the water structure for particle defects at any time before the wafer structure 110 is coated with a photoresist layer. For example, the wafer structure 110 may be subjected to a pre-coat inspection 122).
Before the effective filing date of the claimed invention, it would have obvious to a person of ordinary skill in the art to detect the back surface of the wafer before the first semiconductor process is performed. The motivation for doing so would have been to improve semiconductor quality by frequently detecting defects because defects can occur at random and at various stages while manufacturing the semiconductor.
While Zhou discloses performing the first semiconductor process on the front surface of the wafer, Zhou does not disclose expressly adjusting process parameters of the first semiconductor process and performing the first semiconductor process again.
Nakajima discloses adjusting a plurality of process parameters of the first semiconductor process; and
performing the first semiconductor process on the front surface of the wafer again (paragraph 67, when the exposure shot is not corrected for the semiconductor substrate W1 at Step S41 despite the adhesion of the particle P onto the wafer stage 10, the EUV exposure apparatus 100 performs a lithographic process again for the semiconductor substrate W1. At this time, the EUV exposure apparatus 100 corrects the exposure shot and exposes the semiconductor substrate W1 to the EUV light).
Before the effective filing date of the claimed invention, it would have obvious to a person of ordinary skill in the art to perform a semiconductor process again after adjusting parameters. The motivation for doing so would have been to reduce waste by correcting semiconductor wafers. Therefore, it would have been obvious to combine Phan and Nakajima with Zhou to obtain the invention as specified in claim 1.
Referring to claim 2, Zhou discloses wherein the wafer further comprises a front surface, and the method further comprising:
performing a first semiconductor process on the front surface of the wafer, and then performing the detection step on the back surface of the wafer; and
performing a second semiconductor process on the front surface of the wafer, and then the detection step is performed on the back surface of the wafer again (Page 2, step S01, obtaining the standard crystal back image after finishing each layer process, the standard crystal back image is a two-dimensional grey scale image).
Referring to claim 7, Zhou discloses wherein the judgment step comprises:
according to the data of the at least one defect, a process node producing the at least one defect is determined (Page 2, step S01, obtaining the standard crystal back image after finishing each layer process, the standard crystal back image is a two-dimensional grey scale image [detecting defects after each layer is formed will indicate which layer process produced the defect]).
Referring to claim 11, Zhou discloses wherein a range is selected in the gray scale map, and if the gray scale deviation in the range exceeds a critical value, it is determined that the range contains at least one defect (Page 2, Preferably, the defect number of the to-be-detected crystal back image is determined based on the to-be-detected block of the abnormal block to count).
Claims 3, 5, 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou Chinese Publication 114140425, Phan et al. US Patent 6,724,476 and Nakajima et al. US Publication 2014/0227807 as applied to claim 1 and 2 above, and further in view of well known prior art.
Referring to claim 3, Zhou discloses performing the detection step, the first semiconductor process and the second semiconductor process, but does not disclose expressly wherein each is performed by a same machine.
Official Notice is taken that it is well known and obvious in the art to use one machine for performing a detection step, a first semiconductor process and a second semiconductor process (See MPEP 2144.03). The motivation for doing so would have been to incorporate the hardware for performing the semiconductor processing and detection in a single device to simplify the process of determining whether defects exist. Therefore, it would have been obvious to combine well known prior art with Zhou to obtain the invention as specified in claim 3.
Referring to claim 5, Zhou discloses detecting defects, but does not disclose expressly wherein the defects include strip defects, circular defects and bruised scars.
Official Notice is taken that it is well known and obvious in the art for wafer defects to include strip defects, circular defects and bruised scars (See MPEP 2144.03). The motivation for doing so would have been to recognize commonly occurring wafer defects in order to improve semiconductor quality. Therefore, it would have been obvious to combine well known prior art with Zhou to obtain the invention as specified in claim 5.
Referring to claim 6, Zhou discloses wherein the plurality of data of the defect comprise the total number of defects (Page 4, judge, the defect shape in the final output defect in the embodiment of the invention is the shape, size and number of the defect in the to-be-detected crystal back image), but does not disclose expressly wherein the plurality of data of the defect comprise the maximum length of the strip defect, the angle between the strip defect and a vertical line, the circumference of the circular defect and the area of the bruised scar.
Official Notice is taken that it is well known and obvious in the art to determine the maximum length of the strip defect, the angle between the strip defect and a vertical line, the circumference of the circular defect and the area of the bruised scar (See MPEP 2144.03). The motivation for doing so would have been to detect the extent of the defects in order to more accurately determine the quality of the semiconductor. Therefore, it would have been obvious to combine well known prior art with Zhou to obtain the invention as specified in claim 6.
Referring to claim 8, Zhou discloses detecting the total number of defects, but does not disclose expressly performing a correction step while the total number of defects is greater than a preset value.
Nakajima discloses performing a correction step while the total number of defects is greater than a preset value (paragraph 52, The arithmetic control part 23 determines whether the surface F1 of the semiconductor substrate W is distorted, that is, determines whether correction is necessary (S25). The arithmetic control part 23 can make the determination as to whether the surface F1 of the semiconductor substrate W is distorted by whether the height dz is equal to or larger than a preset threshold or is smaller than the preset threshold) (paragraph 67, when the exposure shot is not corrected for the semiconductor substrate W1 at Step S41 despite the adhesion of the particle P onto the wafer stage 10, the EUV exposure apparatus 100 performs a lithographic process again for the semiconductor substrate W1. At this time, the EUV exposure apparatus 100 corrects the exposure shot and exposes the semiconductor substrate W1 to the EUV light).
At the time of the effective filing date of the claimed invention, it would have obvious to a person of ordinary skill in the art to perform correction on a semiconductor wafer. The motivation for doing so would have been to reduce waste by correcting semiconductor wafers. Therefore, it would have been obvious to combine Nakajima with Zhou to obtain the invention as specified in claim 8.
Referring to claim 9, Nakajima discloses wherein the method further comprising: performing a subsequent process while the total number of defects does not exceed a preset value, and the correction step is not performed (paragraph 67, Needless to mention, there is no need to rework the semiconductor substrate W1 when the exposure shot is corrected for the semiconductor substrate W1).
Referring to claim 10, Zhou discloses wherein the method for capturing a gray scale map of the back surface of the wafer comprises:
converting the image into the gray scale map (Page 2, step S01, obtaining the standard crystal back image after finishing each layer process, the standard crystal back image is a two-dimensional grey scale image).
Zhou does not disclose expressly wherein the method for capturing a gray scale map of the back surface of the wafer comprises: photographing the back surface of the wafer to obtain a color image; converting the color image into the gray scale map.
Official Notice is taken that it is well known and obvious in the art to obtain a color image by photography (See MPEP 2144.03). The motivation for doing so would have been to increase the image quality of the photo in order to more accurately detect image features. Therefore, it would have been obvious to combine well known prior art with Zhou to obtain the invention as specified in claim 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER K HUNTSINGER whose telephone number is (571)272-7435. The examiner can normally be reached Monday - Friday 8:30 - 5:00.
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/PETER K HUNTSINGER/Primary Examiner, Art Unit 2682