DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed January 20, 2026 have been entered and considered.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 20, 2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A).
Regarding claim 1, Ki et al. teaches:
A light emitting diode (LED) module [118, paragraph [0045-0050], Fig. 3-6] comprising:
a substrate layer [120, paragraph [0058-0061], Fig. 3-6] comprising an active area [DA “Display Area”, paragraph [0049], [0059], Fig. 3-6] and a non-active area [NDA “non-display area, paragraph [0049], [0059], Fig. 3-6] excluding the active area [DA];
at least one wiring layer [GL “gate wiring”, DL “data wiring”, PL “power wiring”, paragraph [0050], Fig. 3] provided on the substrate layer [120, Fig. 3-6]; and
a test pad [TP, paragraph [0054-0055], Fig. 3-6] provided in the non-active area [NDA/TA, Fig. 4-6], and including at least one test line [TL, paragraph [0054-0055], Fig. 3-6] connected to the at least one wiring layer [GL, DL, PL, paragraph [0054], Fig. 3].
Ki et al. does not teach:
a line protective coating provided in contact with one side of the at least one test line, the line protective coating being configured to protect the at least one test line.
Quan et al. teaches:
a line protective coating [140, paragraph [0048], [0056], Fig. 1C] provided in contact with one side of the at least one test line [150, paragraph [0048], [0057-0060], Fig. 1C], the line protective coating [140, paragraph [0056], Fig. 1C] being configured to protect the at least one test line [150, Fig. 1C].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Quan et al. into the teachings of Ki et al. to include a line protective coating provided in contact with one side of the at least one test line, the line protective coating being configured to protect the at least one test line, for the purpose of inhibiting moisture and oxygen from penetrating the display panel.
Regarding claim 9, Ki et al. teaches:
A light emitting diode (LED) module inspection method, the LED module [118] comprising a plurality of layers [124, 128, 134, 170, Fig. 3-6], the LED module inspection method comprising:
laminating at least one wiring layer [GL, DL, PL, paragraph [0050-0051], Fig. 3-6] provided on a substrate layer [120, Fig. 3-6] among the plurality of layers on a substrate [120, Fig. 3-6];
obtaining a test current [“test signal”, paragraph [0078], [0088], Fig. 3-6] from a test pad [TP, paragraph [0054-0055], [0078], [0088], Fig. 3-6] connected to the at least one wiring layer [GL “gate wiring”, DL “data wiring”, PL “power wiring”, paragraph [0050], Fig. 3],
determining whether an error is generated in the LED module [118], based on the test current [“test signal”, paragraph [0078], [0088], Fig. 3-6],
wherein the substrate layer [120, Fig. 3-6] comprises an active area [DA, Fig. 3-6] and a non-active area [NDA, Fig. 3-6] excluding the active area [DA], and
wherein the test pad [TP, Fig. 3-6] is provided in the non-active area [NDA/TA, FIG. 3-6], and includes at least one test line [TL, paragraph [0054-0055], Fig. 3-6] connected to the at least one wiring layer [GL, DL, PL, Fig. 3-6].
Ki et al. does not teach:
a line protective coating provided in contact with one side of the at least one test line, the line protective coating being configured to protect the at least one test line.
Quan et al. teaches:
a line protective coating [140, paragraph [0048], [0056], Fig. 1C] provided in contact with one side of the at least one test line [150, paragraph [0048], [0057-0060], Fig. 1C], the line protective coating [140, paragraph [0056], Fig. 1C] being configured to protect the at least one test line [150, Fig. 1C].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Quan et al. into the teachings of Ki et al. to include a line protective coating provided in contact with one side of the at least one test line, the line protective coating being configured to protect the at least one test line, for the purpose of inhibiting moisture and oxygen from penetrating the display panel.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A) as applied to claim 1 above, and further in view of Gamota et al. (US 5682066 A).
Regarding claim 2, Ki et al. and Quan et al. teach the LED module of claim 1.
Ki et al. further teaches:
further comprising an LED [De, paragraph [0050-0051], Fig. 3-6] provided on the upper side of the substrate layer [120, Fig. 3-6].
wherein the at least one wiring layer [GL, DL, PL, paragraph [0050-0051], Fig. 3] is connected to the LED [De, paragraph [0050-0051], Fig. 3-6].
Ki et al. and Quan et al do not teach:
further comprising an LED configured to emit light toward the substrate layer.
Gamota et al. teaches:
further comprising an LED [18, Col. 2, Lines 11-26; Col. 4, Lines 10-14, Fig. 1] configured to emit light toward the substrate layer [14, Col. 2, Lines 11-26; Col. 4, Lines 10-14, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Gamota et al. into the teachings of Ki et al. and Quan et al. to include further comprising an LED configured to emit light toward the substrate layer, for the purpose of increasing luminance while using the same current, and increasing efficiency of the device.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A), and Gamota et al. (US 5682066 A) as applied to claim 2 above, and further in view of Jang et al. (KR 101892213 B1).
Regarding claim 3, Ki et al., Quan et al. and Gamota et al. teach the LED module of claim 2.
Ki et al. further teaches:
Comprising an upper insulating layer [146, paragraph [0072-0074], Fig. 3-6] including upper electrodes [144, paragraph [0070-0071], Fig. 3-6] provided on an upper side of the LED [De, Fig. 3-6] and connected to the LED [De, Fig. 3-6].
Ki et al., Quan et al. and Gamota et al. do not teach:
A plurality of upper electrodes.
Jang et al. teaches:
A plurality of upper electrodes [181, 182, 183, 184, paragraph [0061-0062], Fig. 13-17].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jang et al. into the teachings of Ki et al., Quan et al. and Gamota et al. to include a plurality of upper electrodes, for the purpose of increasing density, electrically connecting features within the device to drive the LED module, and improving performance and resilience. See also, MPEP 2144.04(VI)(B) Duplication of Parts.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A), Gamota et al. (US 5682066 A) and Jang et al. (KR 101892213 B1) as applied to claim 3 above, and further in view of Kasai (US 6864863 B2).
Regarding claim 4, Ki et al., Quan et al., Gamota et al. and Jang et al. teach the LED module of claim 3.
Ki et al. further teaches:
Wherein the upper insulating layer [146, paragraph [0072-0074], Fig. 3-6] is provided on at least one of the upper electrodes [144, Fig. 3-6];
Ki et al., Quan et al., Gamota et al., and Jang et al. disclose the above claimed subject matter.
However, Ki et al., Quan et al. and Gamota et al. do not teach:
a plurality of upper electrodes.
Jang et al. further teaches:
a plurality of upper electrodes. [181, 182, 183, 184, Fig. 20-24].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jang et al. into the teachings of Ki et al., Quan et al., Gamota et al. and Jang et al. to include a plurality of upper electrodes, for the purpose of increasing density, electrically connecting features within the device to drive the LED module, and improving performance and resilience. See also, MPEP 2144.04(VI)(B) Duplication of Parts.
Ki et al., Quan et al., Gamota et al., and Jang et al. do not teach:
Wherein the LED module further comprises a film on glass (FOG) electrode provided on an upper side of the upper insulating layer.
Kasai teaches:
Wherein the LED module further comprises a film on glass (FOG) electrode [89 “ITO anode”, Col. 6, Lines 64-66, Fig. 3a-3c] provided on an upper side of the upper insulating layer [88, Col. 6, Lines 61-64, Fig. 3a-3c].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kasai into the teachings of Ki et al., Quan et al., Gamota et al., and Jang et al. to include wherein the LED module further comprises a film on glass (FOG) electrode provided on an upper side of the upper insulating layer, for the purpose of providing a low resistance electrical contact, reducing cost, and improving performance without blocking light.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Gamota et al. (US 5682066 A), Jang et al. (KR 101892213 B1), Kasai (US 6864863 B2), Jeong et al. (US 20180188579 A1), Chen (US 20190280151 A1), Quan et al. (CN 110676290 A), and Yokoyama et al. (CN 110741428 A).
Regarding claim 5, Ki et al. teaches
A light emitting diode (LED) module [118, paragraph [0045-0050], Fig. 3-6] comprising:
a substrate layer [120, paragraph [0058-0061], Fig. 3-6] comprising a cutting surface [TA “Test Area”, paragraph [0010], [0079], Fig. 3-6] and an active area [DA “Display Area”, paragraph [0049], [0059], Fig. 3-6];
at least one wiring layer [GL “gate wiring”, DL “data wiring”, PL “power wiring”, paragraph [0050], Fig. 3] provided on the substrate layer [120, Fig. 3-6];
an LED [De, paragraph [0050-0051], Fig. 3-6] provided on an upper side of the substrate layer [120].
an upper insulating layer [146, paragraph [0072-0074], Fig. 3-6] including upper electrodes [144, paragraph [0070-0071], Fig. 3-6] provided on an upper side of the LED [De, Fig. 3-6] and connected to the LED [De, Fig. 3-6];
the upper insulating layer [146, paragraph [0072-0074], Fig. 3-6] being provided on at least one of the upper electrodes [144, Fig. 3-6];
a protective coating structure [158, paragraph [0086-0091], Fig. 3-6] provided on the cutting surface [TA, Fig. 3-6],
wherein the cutting surface [TA “Test Area”, paragraph [0010], [0079], Fig. 3-6] is provided on a predetermined boundary [CL1/CL2, paragraph [0079-0081], [0089], Fig. 3-6] between the active area [DA, Fig. 3-6] of the substrate layer [120, Fig. 3-6] and a test pad [TP, Fig. 3-6].
wherein the cutting surface [TA, Fig. 3-6] includes a rear surface of the substrate layer [120, Fig. 3-6], a side surface of the substrate layer [120, Fig. 3-6], and a surface where at least one test line [TL, paragraph [0081], [0085], Fig. 3-6] of the test pad [TP, Fig. 3-6] is exposed,
wherein the protective coating structure [158, Fig. 3-6] is provided, and the surface where the at least one test line [TL, Fig. 3-6] of the test pad [TP, FIG. 3-6] is exposed.
Ki et al. does not teach:
an LED configured to emit light toward the substrate layer.
Gamota et al. teaches:
an LED [18, Col. 2, Lines 11-26; Col. 4, Lines 10-14, Fig. 1] configured to emit light toward the substrate layer [14, Col. 2, Lines 11-26; Col. 4, Lines 10-14, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Gamota et al. into the teachings of Ki et al. to include an LED configured to emit light toward the substrate layer, for the purpose of increasing luminance while using the same current, and increasing efficiency of the device.
Ki et al. and Gamota et al. do not teach:
A plurality of upper electrodes.
Jang et al. teaches:
A plurality of upper electrodes. [181-184, paragraph [0061-0062], Fig. 13-17, 20-24]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jang et al. into the teachings of Ki et al. and Gamota et al. to include a plurality of upper electrodes, for the purpose of increasing density, electrically connecting features within the device to drive the LED module, and improve performance and resilience.
Ki et al., Gamota et al. and Jang et al. do not teach:
a film on glass (FOG) electrode provided on an upper side of the upper insulating layer.
Kasai teaches:
a film on glass (FOG) electrode [89 “ITO anode”, Col. 6, Lines 64-66, Fig. 3a-3c] provided on an upper side of the upper insulating layer [88, Col. 6, Lines 61-64, Fig. 3a-3c].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kasai into the teachings of Ki et al., Gamota et al. and Jang et al. to include a film on glass (FOG) electrode provided on an upper side of the upper insulating layer, for the purpose of providing a low resistance electrical contact, reducing cost, improving performance without blocking light.
Ki et al., Gamota et al., Jang et al., and Kasai do not teach:
a rear surface of the substrate layer on which a chamfering is performed
wherein the protective coating structure is provided on the rear surface of the substrate layer on which the chamfering is performed.
Jeong et al. teaches:
a rear surface of the substrate layer [20/200, paragraph [0096], Fig. 4] on which a chamfering is performed
wherein the protective coating structure [50, paragraph [0097-0098], Fig. 4] is provided on the rear surface [200b, Fig. 4] of the substrate layer [20/200, Fig. 4] on which the chamfering is performed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jeong et al. into the teachings of Ki et al., Gamota et al., Jang et al., and Kasai to include a rear surface of the substrate layer on which a chamfering is performed wherein the protective coating structure is provided on the rear surface of the substrate layer on which the chamfering is performed, for the purpose of enhancing mechanical strength, preventing cracking and reducing thermal stress, planarization for subsequent processes, improving quality and yield, preventing damage from environmental factors, improving integrity and reliability of device, reducing reflection, and improving output.
Ki et al., Gamota et al., Jang et al., Kasai and Jeong et al. do not teach:
the protective coating structure includes a material having a refractive index corresponding to a refractive index of the substrate layer.
Chen teaches:
the protective coating structure [13, paragraph [0033], Fig. 2F] includes a material having a refractive index corresponding to a refractive index of the substrate layer [14, paragraph [0033], Fig. 2F].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen into the teachings of Ki et al., Gamota et al., Jang et al., Kasai and Jeong et al. to include the protective coating structure includes a material having a refractive index corresponding to a refractive index of the substrate layer, for the purpose of minimizing reflection, and improving light emission, performance, efficiency and durability. Due to the finite number of materials with corresponding refractive indexes, this limitation would be obvious through trial testing and routine optimization.
Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al. and Chen do not teach:
wherein the side surface of the substrate layer is provided to protrude beyond an exposed surface of the at least one test line of the test pad, and
wherein a protective coating structure is provided on the side surface of the substrate layer.
Quan et al. teaches:
wherein the side surface [106, paragraph [0062], [0131], [0138], Fig. 1C] of the substrate layer [110, paragraph [0062], Fig. 1C] is provided to protrude beyond an exposed surface of the at least one test line [150, paragraph [0048], [0057-0060], Fig. 1C] of the test pad [PAD1, paragraph [0060], Fig. 1C], and
wherein a protective coating structure [180, paragraph [0048], [0067-0069], Fig. 1C] is provided on the side surface [106, Fig. 1C] of the substrate layer [110, Fig. 1C].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Quan et al. into the teachings of Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al. and Chen to include wherein the side surface of the substrate layer is provided to protrude beyond an exposed surface of the at least one test line of the test pad, and wherein a protective coating structure is provided on the side surface of the substrate layer, for the purpose of exposing surfaces of the signal lines for subsequent processes, improve visibility and protect features within.
Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Chen and Quan et al. do not teach:
wherein a thickness of the protective coating structure provided on the side surface of the substrate layer is less than a thickness of the protective coating structure provided on the exposed surface of the at least one test line of the test pad.
Yokoyama et al. teaches:
wherein a thickness of the protective coating structure [36, paragraph [0042-0043], [0045], [0047-0049], [0065-0066], Fig. 2] provided on the side surface of the substrate layer [1, paragraph [0047], Fig. 2] is less than a thickness of the protective coating structure [36, Fig. 2] provided on the exposed surface of the at least one test line [2p, paragraph [0038], [0045], [0054], Fig. 1-2] of the test pad [37, paragraph [0054], [0058], [0065], Fig. 1-2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yokoyama et al. into the teachings of Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Chen and Quan et al. to include wherein a thickness of the protective coating structure provided on the side surface of the substrate layer is less than a thickness of the protective coating structure provided on the exposed surface of the at least one test line of the test pad, for the purpose of protecting features within, shielding light, and improving display and visibility.
Regarding claim 6, Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Chen, Quan et al., and Yokoyama et al. teach the LED module of claim 5.
Ki et al. further teaches:
wherein the cutting surface [TA “Test Area”, paragraph [0010], [0079], Fig. 3-6] is formed after cutting the test pad [TP, paragraph [0056], [0079], [0088-0089], Fig. 3-6].
Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Chen, Quan et al., and Yokoyama et al. disclose the above claimed subject matter.
However, Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Quan et al., and Yokoyama et al. do not teach:
Through grinding
Chen teaches:
Through grinding [paragraph [0030]]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen into the teachings of Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Chen, Quan et al., and Yokoyama et al. to include through grinding, for the purpose of cutting the desired features at the desired locations with higher precision and reducing damage to other features, and improving development speed.
It should be noted that applicant included the limitation “through grinding” in claim 6, when describing how the cutting surface is formed. This limitation is a Product-by-Process claim and as such, patentability is determined by the product or device itself, not how it is made. See MPEP 2113 Product-by-Process Claims.
Regarding claim 7, Ki et al., Gamota et al., Jang et al., Kasai, Jeong et al., Chen, Quan et al., and Yokoyama et al. teach the LED module of claim 5.
Ki et al. further teaches:
wherein the at least one test line [TL, Fig. 3-6] includes a line protective coating [150, paragraph [0072-0074], [0081], Fig. 3-6], and
wherein the cutting surface [TA, Fig. 3-6] and the at least one test line [TL, Fig. 5-6] include the exposed surface.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A) as applied to claim 9 above, and further in view of Itagaki et al. (US 20060125512 A1).
Regarding claim 10, Ki et al., and Quan et al. teach the LED module inspection method of claim 9.
Ki et al. and Quan et al. do not teach:
wherein the determining whether the error is generated in the LED module comprises
identifying a capacitance of the LED module based on the test current; and
determining whether the error is generated in the LED module based on the capacitance.
Itagaki et al. teaches:
wherein the determining whether the error is generated in the LED module comprises
identifying a capacitance of the LED module based on the test current; and
determining whether the error is generated in the LED module based on the capacitance. [paragraph [0007-0016], [0029-0043], Fig. 1(A)-7(D)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Itagaki et al. into the teachings of Ki et al. and Quan et al. to include wherein the determining whether the error is generated in the LED module comprises identifying a capacitance of the LED module based on the test current; and determining whether the error is generated in the LED module based on the capacitance, for the purpose of testing the device to ensure proper functionality, and drawing multiple conclusions with regard to different states and causes of failure.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A) and Itagaki et al. (US 20060125512 A1) as applied to claim 10 above, and further in view of Kodama et al. (JP 2008002858 A).
Regarding claim 11, Ki et al., Quan et al. and Itagaki et al. teach the LED module inspection method of claim 10.
Ki et al. further teaches:
wherein the determining whether the error is generated in the LED module [118, paragraph [0078], [0088], Fig. 3-6] is performed after mounting an LED [De, Fig. 3-6].
Ki et al., Quan et al. and Itagaki et al. do not teach:
wherein the determining whether the error is generated in the LED module is performed before mounting an LED.
Kodama et al. teaches:
wherein the determining whether the error is generated in the LED module is performed before mounting an LED. [Paragraph [0001], [0012-0014], [0020-0021], [0023], Fig. 1-2]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kodama et al. into the teachings of Ki et al., Quan et al. and Itagaki et al. to include wherein the determining whether the error is generated in the LED module is performed before mounting an LED, for the purpose of reducing time and man-hours required for the inspection, ensuring no errors before mounting, therefore the device can function properly. See also, MPEP 2144.04(IV)(C) Changes in Sequence of Adding Ingredients.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A) as applied to claim 9 above, and further in view of Gamota et al. (US 5682066 A), and Kodama et al. (JP 2008002858 A).
Regarding claim 12, Ki et al., and Quan et al. teach the LED module inspection method of claim 9.
Ki et al. further teaches:
wherein the LED module [118, Fig. 3-6] further comprises an LED [De, Fig. 3-6] provided on an upper side of the substrate [120, Fig. 3-6].
Ki et al. and Quan et al. do not teach:
an LED configured to emit light toward the substrate.
Gamota et al. teaches:
an LED [18, Col. 2, Lines 11-26; Col. 4, Lines 10-14, Fig. 1] configured to emit light toward the substrate layer [14, Col. 2, Lines 11-26; Col. 4, Lines 10-14, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Gamota et al. into the teachings of Ki et al. and Quan et al. to include an LED configured to emit light toward the substrate, for the purpose of increasing luminance while using the same current, and increasing efficiency of the device.
Ki et al., Quan et al. and Gamota et al. do not teach:
wherein the determining whether the error is generated in the LED module is performed based on a light emission of the LED corresponding to the test current obtained after mounting the LED.
Kodama et al. teaches:
wherein the determining whether the error is generated in the LED module is performed based on a light emission [paragraph [0001]] of the LED [2, paragraph [0023], Fig. 1-2] corresponding to the test current obtained after mounting the LED [2, Fig. 1-2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kodama et al. into the teachings of Ki et al., Quan et al. and Gamota et al. to include wherein the determining whether the error is generated in the LED module is performed based on a light emission of the LED corresponding to the test current obtained after mounting the LED, for the purpose of reducing time and man-hours required for the inspection, ensuring no errors, therefore the device can function properly.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A) as applied to claim 9 above, and further in view of Hirasawa et al. (US 10181553 B2).
Regarding claim 13, Ki et al., and Quan et al. teach the LED module inspection method of claim 9.
Ki et al. further teaches:
cutting a predetermined boundary [CL1/CL2, paragraph [0079-0081], [0089], Fig. 3-6] between the active area [DA, Fig. 3-6] and the test pad [TP, Fig. 3-6]; and
after cutting the predetermined boundary [CL1/CL2, paragraph [0079-0081], [0089], Fig. 3-6], a cutting surface [TA “Test Area”, paragraph [0010], [0079], Fig. 3-6] formed by cutting the predetermined boundary [CL1/CL2].
Ki et al. and Quan et al. do not teach:
grinding a cutting surface.
Hirasawa et al. teaches:
grinding a cutting surface [T, Col. 9, Lines 25-28, Fig. 4(e)-4(f)]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hirasawa et al. into the teachings of Ki et al. and Quan et al. to include grinding a cutting surface, for the purpose of acquiring the desired shape/structure, grinding is a known method in the art for removing portions of a surface with high precision.
It should be noted that applicant included the limitation “grinding” in claim 13, when describing how the cutting surface is formed. This limitation is a Product-by-Process claim and as such, patentability is determined by the product or device itself, not how it is made. See MPEP 2113 Product-by-Process Claims.
Regarding claim 14, Ki et al., Quan et al. and Hirasawa et al. teach the LED module inspection method of claim 13.
Ki et al. further teaches:
comprising after cutting the predetermined boundary [CL1/CL2, paragraph [0079-0081], [0089], Fig. 3-6], providing a protective coating structure [158 “resin pattern”, paragraph [0086-0088], [0090], Fig. 6] corresponding to the cutting surface [TA “Test Area”, paragraph [0010], [0079], Fig. 3-6].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (KR 20180076159 A), in view of Quan et al. (CN 110676290 A) and Hirasawa et al. (US 10181553 B2) as applied to claim 14 above, and further in view of Hong et al. (CN 106129231 B).
Regarding claim 15, Ki et al., Quan et al. and Hirasawa et al. teach the LED module inspection method of claim 14.
Ki et al. further teaches:
After cutting the predetermined boundary [CL1/CL2, paragraph [0079-0081], [0089], Fig. 3-6], removing the at least one test line [paragraph [0025], [0035], Fig. 1-2] connecting the at least one wiring layer [GL “gate wiring”, DL “data wiring”, PL “power wiring”, paragraph [0050], Fig. 3] to the test pad [TP, paragraph [0054-0055], [0078], [0088], Fig. 3-6].
Ki et al., Quan et al. and Hirasawa et al do not teach:
Before cutting the predetermined boundary.
Hong et al. teaches:
Before cutting the predetermined boundary. [Paragraph [0141], Fig. 11C]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hong et al. into the teachings of Ki et al., Quan et al. and Hirasawa et al. to include before cutting the predetermined boundary, for the purpose of exposing features beneath for subsequent processes.
Response to Arguments
Applicant’s arguments with respect to independent claims 1, 5 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues on pages 1-6, Section: Rejections Under 35 USC §§ 102 and 103, in remarks filed January 20, 2026 that the prior art of record does not teach the amendments to independent claims 1, 5 and 9. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art, the amended limitations of independent claims 1, 5 and 9 can be overcome by newly cited sources Quan et al. (CN 110676290 A), and Yokoyama et al. (CN 110741428 A). The amended limitations of independent claims 1 and 9 can be overcome by Quan et al. (CN 110676290 A). The amended limitations of independent claim 5 can be overcome by a combination of Quan et al. (CN 110676290 A), and Yokoyama et al. (CN 110741428 A).
Applicant further argues on page 6, in remarks filed January 20, 2026 that claims dependent on independent claims 1, 5 and 9 should be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
In summary, Applicant’s arguments regarding the amendments to independent claims 1, 5 and 9 are moot due to the introduction of newly cited sources Quan et al. (CN 110676290 A), and Yokoyama et al. (CN 110741428 A). All claims directly or indirectly dependent on independent claims 1, 5 and 9 are therefore rejected for at least the reasons mentioned above.
Conclusion
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/D.M.H./Examiner, Art Unit 2815 02/20/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815