Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s cancellation of claims 2 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan.
For claim 9, Ki teaches a light emitting diode (LED) module inspection method, the LED module comprising a plurality of layer (Ki, fig. 3 – 6 shows multiple layers comprising the LED module 118), the LED module inspection method comprising: laminating at least one wiring layer (fig. 3 – 6 numeral T, Ts, Td; Par. [0050 – 0051]) provide don a substrate (fig. 3 – 6 numeral 120) among the plurality of layers; the at least one wiring layer being configured to be electrically connected between an LED (fig. 3 – 6 numeral De) and a wiring that drive the LED and includes a data line (fig. 4 numeral DL), a power line (fig. 4 numeral PL), and a line for a control signal (fig. 4 numeral GL; Par. [0048]); obtaining a test current from a test pad (fig. 3 – 6 numeral TP; Par. [0054 – 0055], [0078], [0088]) connected to the at least one wiring layer (Par. [0078]; Par. [0050 – 0052]; fig. 4 numeral TP and TL) and determining whether an error is generated in the LED module based on the test current (Par. [0078 – 0088]), wherein the substrate layer comprises an active area (fig. 3 – 6 numeral DA) and a non-active area excluding the active area (fig. 3 – 6 numeral NDA), and wherein the test pad is provided in the non-active area (fig. 3 – 6 numeral TP) and includes at least one test line connected to the at least one wiring layer (fig. 3 – 6 numeral TL). Ki is silent regarding a line protective coating being provide in contact with one side of the least one test line, the line protective coating being configured to protect the at least one test line.
Quan teaches a line protective coating (Quan, fig. 1C numeral 140) in contact with one side of a signal line (fig. 1C numeral 150), and the line is configured to protect the line (Par. [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the protective layer in Quan with the testing line in Ki in order to prevent the testing line from being exposed to moisture and/or other particulates and erosive materials (Quan, Par. [0056]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan in further view of US 20060125512 A1 hereinafter Itagaki.
For claim 10, Ki and Quan teach all of claim 9. Ki and Quan are silent regarding determining whether the error is generated in the LED module comprises identifying a capacitance of the LED module based on the test current; and determining whether the error is generated in the LED module based on the capacitance.
Itagaki teaches an inspecting method including determining whether the error is generated in the LED module comprises identifying a capacitance of the LED module based on the test current; and determining whether the error is generated in the LED module based on the capacitance (Par. [0007-0016], [0029-0043], Fig. 1(A)-7(D)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the capacitance testing in Itagaki with the testing structure in Ki and Quan in order to improve the accuracy of testing the LED modules (Itagaki, Par. [0016]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan in view of US 20060125512 A1 hereinafter Itagaki, and in further view of JP 2008002858 A hereinafter Kodama.
For claim 11, Ki, Quan, and Itagaki teach all of claim 10. Ki, Quan, and Itagaki are silent regarding determining whether the error is generated in the LED module is performed before mounting the LED.
Kodama teaches an inspection method wherein the method determining whether the error is generated in the LED module is performed before mounting an LED. (Par. [0001], [0012-0014], [0020-0021], [0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kodama into the teachings of Ki, Quan, and Itagaki, to include wherein the determining whether the error is generated in the LED module is performed before mounting an LED, for the purpose of reducing time and man-hours required for the inspection, ensuring no errors before mounting, therefore the device can function properly. See also, MPEP 2144.04(IV)(C) Changes in Sequence of Adding Ingredients.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan in view of US 20060125512 A1 hereinafter Itagaki, in further view of JP 2008002858 A hereinafter Kodama, and in further view of US 5682066 A hereinafter Gamota.
For claim 12, Ki, Quan, Itagaki, and Kodama teach all of claim 12. Ki also teaches an LED being proved on an upper side of the substrate layer (Ki, fig. 3 – 6 numeral De). Kodama also teaches a testing method wherein determining whether the error is generated in the LED module is performed based on a light emission (Kodama, Par. [0001]) of the LED (Fig. 1-2 numeral 2 Par. [0023]) corresponding to the test current obtained after mounting the LED. Ki, Quan, Itagaki, and Kodama are silent regarding the LED being configured to emit light toward the substrate layer.
Gamota teaches a LED module (Gamota, fig. 1 numeral 10) comprising an LED (fig. 1 numeral 18) and the LED is mounted onto a substrate (fig. 1 numeral 14) and is configured so that the light from the LED is directed to the substrate (Abstract; Col. 2 ln 10 – 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the configuration of the LED in Gamota with the structure and wiring configuration in Ki, Quan, Itagaki, and Kodama for the purpose of increasing luminance while using the same current, and increasing efficiency of the device and to assist in creating a well-lit display and improve mechanical support (Gamota, Col. 4 ln 21 – 29).
Claim(s) 13 – 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan in view of US 10181553 B2 hereinafter Hirasawa.
For claim 13, Ki and Quan teach all of claim 9. Ki also teaches cutting a predetermined boundary (Par. [0079 – 0081]; Par. [0089]; fig. 3 – 6 numeral CL1/CL2) between the active area (fig. 3 – 6 numeral DA) and the test pad (fig. 3 – 6 numeral TP); and after cutting the predetermined boundary, a cutting surface forming a cutting surface by cutting the predetermined boundary (fig. 3 – 6 numeral TA; Par. [0010]; Par. [0079]). Ki and Quan are silent regarding grinding the cutting surface.
Hirasawa teaches a cutting surface including grinding the cutting surface (Hirasawa, Col. 9 ln 25 – 28, fig. 4e – 4f numeral T).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the grinding in Hirasawa with the cutting in Ki and Quan in order to remove blemishes or burrs left over after the cutting process (Hirasawa, Col. 3 ln 33 – 44).
For claim 14, Ki, Quan, and Hirasawa teach all of claim 13. Ki also teaches providing a protective coating structure corresponding to the cutting surface (Ki, fig. 6 numeral 158; Par. [0086 – 0090]).
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan and in further view of US 5682066 A hereinafter Gamota.
For claim 1, Ki teaches a light emitting diode (LED) module (Ki, fig. 3 – 6 numeral 118) comprising a substrate layer (fig. 3 – 6 numeral 120) comprising an active area (fig. 3 – 6 numeral DA) and a non-active area (fig. 3 – 6 numeral NDA) that excludes the active area; an LED provided on the upper side of the substrate layer (fig. 3 – 6 numeral De); a wiring configured to drive the LED and comprising a data line (fig. 4 numeral DL), a power line (fig. 4 numeral PL), and a line for a control signal (fig. 4 numeral GL; Par. [0048]); at least one wiring layer provided on the substrate layer and electrically connected between the wiring and the LED (fig. 4 numeral Ts and Td; fig. 3 – 6 numeral T; Par. [0023], Par. [0050 – 0052]); and a test (fig. 3 – 6 numeral TP) provided in the non-active area and including at least one test line connected to the least one wiring layer (fig. 3 – 6 numeral TL; Par. [0023]). Ki is silent regarding a protective coating in contact with one side of the at least one test line and configured to protect the one test line. Ki is also silent regarding the LED being configured to emit light toward the substrate layer.
Quan teaches a line protective coating (Quan, fig. 1C numeral 140) in contact with one side of a signal line (fig. 1C numeral 150), and the line is configured to protect the line (Par. [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the protective layer in Quan with the testing line in Ki in order to prevent the testing line from being exposed to moisture and/or other particulates and erosive materials (Quan, Par. [0056]). Ki and Quan are silent regarding the LED being configured to emit light toward the substrate layer.
Gamota teaches a LED module (Gamota, fig. 1 numeral 10) comprising an LED (fig. 1 numeral 18) and the LED is mounted onto a substrate (fig. 1 numeral 14) and is configured so that the light from the LED is directed to the substrate (Abstract; Col. 2 ln 10 – 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the configuration of the LED in Gamota with the structure and wiring configuration in Ki and Quan in order for the purpose of increasing luminance while using the same current, and increasing efficiency of the device and to assist in creating a well-lit display and improve mechanical support (Gamota, Col. 4 ln 21 – 29).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan and in view of US 5682066 A hereinafter Gamota, and in further view of KR 101892213 B1 hereinafter Jang.
For claim 3, Ki, Quan, and Gamota teach all of claim 1. Ki also teaches an upper insulating layer (fig. 3 – 6 numeral 146] including upper electrodes provided on an upper side of the LED and connected to the LED (fig. 3 – 6 numeral 144). Ki, Quan, and Gamota are silent regarding a plurality of upper electrodes.
Jang teaches an LED module (Jang, fig. 14) comprising a plurality of electrodes (fig. 14 – 17 numeral 181 – 184) on top of an LED (fig. 14 – 17 numeral 161 – 164).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the multiple electrodes in Jang with the LED in Ki, Quan, and Gamota in order to provide multiple contact spots connected to the LED (Jang, Par. [0072 – 0073]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20180076159 A hereinafter Ki in view of CN 110676290 A hereinafter Quan, in view of US 5682066 A hereinafter Gamota, in view of KR 101892213 B1 hereinafter Jang, and in further view of US 6864863 B2 hereinafter Kasai.
For claim 4, Ki, Quan, Gamota, and Jang teach all of claim 3. Ki also teaches an upper insulating layer provided on at least one of the upper electrodes (Ki, fig. 3 – 6 numeral 146). Ki, Quan, Gamota, and Jang are silent regarding a film on glass (FOG) electrode provided on an upper side of the upper insulating layer.
Kasai teaches an LED module including a film on glass electrode (Kasai, fig. 3a – 3c numeral 89; Col. 6 ln 64 – 66) provided on an upper side of the upper insulating layer (fig. 3a – 3c numeral 88).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the FOG electrode in Kasai with the electrodes in Ki, Quan, Gamota, and Jang in order to better control the capacitance of the device and the wiring (Kasai, Col. 6 ln 50 – Col. 7 ln 19).
Allowable Subject Matter
Claims 5 - 7 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 5’s “…the thickness being a distance parallel to an extension of the substrate layer”. The prior art of record does not appear to teach a thickness of the protective coating being less on the side surface of the substrate layer than the thickness of the protective coating on the exposed surface of the test line, wherein that thickness is measured as a distance parallel to an extension of the substrate.
Claims 6 – 7 are allowable primarily as being dependent on an allowable base claim.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Claim 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 15, Ki does teach removing the at least one test line from the at least one wiring layer. However, Ki preforms the removal step after cutting the predetermined boundary (Ki, Par. [079 – 0089]; Par. [0025 – 0035]). It would not be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to reverse the order of cutting and removal in Ki.
Response to Arguments
Applicant’s arguments, see pages 12 - 14 of applicant's remarks, filed 05/20/2026, with respect to claim 5 have been fully considered and are persuasive. The rejection of 02/24/2026 has been withdrawn.
Applicant's arguments filed 05/20/2026 directed to claims 1 and 9 have been fully considered but they are not persuasive. Applicant’s arguments directed to claims 1 and 9 focus on the amended claims including limitations not taught by the prior art and that Quan does not teach a test pad or test line. Firstly, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Quan is combined with other prior art that does teach a test pad and test line, and Quan is used primarily to teach the inclusion of a protective coating or film on an electrical line to protect it from the external environment. Other prior art is relied upon to teach a test line and a test pad. Applicant’s arguments do not appear to address the combination of the prior art and only attacks the references individually.
Second, regarding the amended claims and the new limitation that the wiring includes a power line, data line, and a line for transmitting a control signal; Ki appears to teach all the new limitations present in the amended claims (see the above rejection). The rejection of claims 1 and 9 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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