Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2025 has been entered.
Response to Amendment
The applicant has amended their application as follows:
Amended: 1 and 7
Cancelled: 6 and 9-11
Added: 14
Therefore, claims 1-5, 7-8 and 12-14 are currently pending in the instant application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2009/0135111 A1, hereinafter “Yamamoto”) in view of Choi et al. (US 2010/0141564 A1, hereinafter “Choi”).
As to claim 1, Yamamoto (Fig. 1) discloses a display device (1), comprising:
a pixel array (102) in which pixels are arranged in a matrix pattern (Para. 0087); and
driving circuitry (104, 105, 106) configure to drive the pixel array (Para. 0091),
wherein respective ones of the pixels (P_1, 1) include:
a light emitting element (Fig. 15A element 127) including an anode electrode (“anode”) and a cathode electrode (“cathode”), the cathode electrode being electrically connected to a first power supply line (Vcath),
a first capacitor (Cs),
a sampling component (125) configured to supply a data signal voltage (Vsig) supplied through a data signal line (106HS) to the first capacitor (Cs);
a driving transistor (121) configured to supply a driving current from a second power supply line (Vc1) to the light emitting element (127) according to a voltage stored in the first capacitor (Para. 0135), and
a light emission control component (122) electrically connected in series with the driving transistor (121) and the light emitting element (127) between the first and second power supply lines (Vcath, Vc1),
wherein the sampling component (125) is configured to start supplying a first voltage (Fig. 15B element Vofs) to the first capacitor at a first timing (t54) and to start supplying the data signal voltage (Vsig) to the first capacitor at a second timing (timing right after t54 and before t56 when Vsig i.e. Vofs + Vin is supplied as shown in reproduced figure below), both the first timing and the second timing being during a period when the second power supply line and the driving transistor are electrically disconnected by the light emission control component in a non-light emission period (DS is high; Para. 0385).
Yamamoto does not disclose a second capacitor configured to be electrically connected in series with the first capacitor, and
wherein the second capacitor is directly electrically connected to the light emission control component.
However, Choi (Fig. 3) teaches second capacitor (C2) configured to be electrically connected in series with the first capacitor (CC1), and
wherein the second capacitor (C2) is directly electrically connected to the light emission control component (M3).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Choi to include a coupling capacitor in the device disclosed by Yamamoto. The motivation would have been to provide the benefits of coupling effect of the capacitors (Choi; Para. 0052). In combination, the coupling capacitor C2 would be connected to the source of the light emitting transistor 122 of Yamamoto in order to control the voltage of node ND122 (Choi; Para. 0052).
Reproduced figure 15B of Yamamoto for clarity.
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As to claim 2, Yamamoto (Fig. 15A) discloses the display device according to claim 1, wherein a sampling transistor (125) of the sampling component is configured to receive an offset voltage (Vofs) in a threshold correction period (Fig. 15 element First threshold value correction period E; Para. 0385-0386) that occurs prior to a light emission period (T68, light emitting period), and the sampling transistor is configured to be in an ON state during the threshold correction period (Para. 0380, 125 would be turned on when WS is high during threshold value correction period E).
As to claim 3, Yamamoto (Fig. 15A) discloses the display device according to claim 2, wherein the sampling transistor (125) is configured to receive the data signal voltage (Vsig) during a signal writing period (Fig. 15B element t66-t67; Para. 0384).
As to claim 5, Yamamoto (Fig. 15A) discloses the display device according to claim 2, wherein the sampling transistor (125) is configured to be in an OFF state during the light emission period (Fig. 15B element t68; WS is low during light emission period).
As to claim 8, Yamamoto (Fig. 15A) discloses the display device according to claim 1, wherein a first terminal of the second capacitor (120) is electrically connected to the first capacitor (Ryu, as disclosed teaches two capacitors) and a second terminal of the second capacitor (120) is supplied with a predetermined voltage (Vs1; when 124 is turned on).
As to claim 13, Yamamoto (Fig. 15A) discloses the display device according to claim 1, wherein the second power supply line (Vc1) and the drive transistor (121) are configured to continuously maintain a state of being electrically disconnected by the light emission control component (122) between the first timing (Fig. 15B element t54) and the second timing (before t56; DS is high from t54 to t56 i.e. the light emitting transistor T22 is turned off).
Claim(s) 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto and Choi in view of Yamamoto et al. (US 2009/0219231 A1, hereinafter “Yamamoto’231”).
As to claim 4, Yamamoto does not disclose the display device according to claim 3, wherein the sampling transistor is configured to receive an intermediate voltage during the light emission period, which occurs after the signal writing period.
However, Yamamoto’231 (Fig. 50) teaches wherein the sampling transistor (T31) is configured to receive an intermediate voltage (Vofs1) during the light emission period (Fig. 52C element T15), which occurs after the signal writing period (T12-T14; Para. 0255-0256).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Yamamoto’231 to sequentially apply data voltage and offset voltage to the data line in the device disclosed by Yamamoto/Yamashita. The motivation would have been to perform the mobility corrections in the pixels in just proportion within the determined time period (Yamamoto’231; para. 0299).
As to claim 7, Yamamoto does not disclose the display device according to claim 1, wherein the driving circuitry is configured to selectively to provide, via the data signal line, the data signal voltage, the reference voltage, an offset voltage and an intermediate voltage to the sampling component, the offset voltage being between the reference voltage and the data signal voltage, and the intermediate voltage being between the reference voltage and the data signal voltage.
However, Yamamoto’231 teaches wherein the driving circuitry (Fig. 50 element 157) is configured to selectively to provide, via the data signal line (DTL), the data signal voltage (Vsig), a reference voltage (Vini), an offset voltage (Vofs1) and an intermediate voltage (Vofs2) to the sampling component (T31), the offset voltage (Fig. 52C element Vofs1) being between the reference voltage (Vini) and the data signal voltage (Vsig), and the intermediate voltage (Vofs2) being between the reference voltage (Vini) and the data signal voltage (Vsig; Para. 0250, 0256).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Yamamoto’231 to apply offset voltages to the device disclosed by Yamamoto/Yamashita. The motivation would have been to increase the “time required for the mobility correction” (Yamamoto’231; Para. 0292).
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto and Choi as applied to claim 1 above, and further in view of Kim et al. (US 2007/0118781 A1, hereinafter “Kim”).
As to claim 12, Yamamoto does not disclose the display device according to claim 1, wherein a capacitance value of the first capacitor is greater than or equal to a capacitance value of the second capacitor.
However, Kim (Fig. 4) teaches wherein a capacitance value of the first capacitor (Cst) is greater than or equal to a capacitance value of the second capacitor (Caux; Para. 0063).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kim to have the capacitance of the storage capacitor larger than the capacitance of the auxiliary capacitor in the device disclosed by Yamamoto/Yamashita. The motivation would have been to enhance the contrast ratio (Kim; Para. 0062-0063).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto and Choi as applied to claim 1 above, and further in view of Yamashita et al. (US 2008/0291182 A1, hereinafter “Yamashita”).
As to claim 14, Yamamoto in view of Choi discloses the display device according to claim 1. Furthermore, Yamamoto wherein the first capacitor (Cs) is directly electrically connected to a gate of the driving transistor (121).
Yamamoto does not disclose wherein the second capacitor is not directly electrically connected to the gate of the driving transistor.
However, Yamashita (Fig. 2) teaches wherein the second capacitor (Csub) is not directly electrically connected to the gate of the driving transistor (Tr2).
It would have been obvious to one of ordinary skill in the art to simple substitute the capacitor formation of Yamashita for the capacitor formation of Yamamoto/Choi. The result of such a substitution would have yielded predictable results of providing a coupling effect. In combination, the driving transistor of Yamamoto would be a PMOS transistor, therefore, the ND121 would be formed between the light emitting transistor 122 and the driving transistor 121.
Conclusion
The prior at made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Tanikame et al. (US 2009/0262102 A1) also discloses a second offset voltage (Fig. 11 element Vofs2).
Yamamoto et al. (US 2010/0289793 A1) also discloses sampling transistor turning on and off twice during the non-light emission period (Fig. 5).
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BIPIN GYAWALI
Examiner
Art Unit 2625
/BIPIN GYAWALI/Examiner, Art Unit 2625