Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 9, and 11 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over US20040010767A1 (Agrawal) and in view of US20050035783A1
(Wang).
In regards to claim 1 (Agrawal) shows a method for constructing an FPGA chip top-level schematic comprising:
integrating several grid devices into one tile device; Agrawal [0072] teaches each GLB tile includes a Block Output Switch Matrix and direct-connect sourcing node, demonstrating integration of multiple functional blocks into tile structures.
constructing each tile device symbol into a tile interconnection line symbol of at least one corresponding form according to a predefined interconnection requirement; Agrawal [0039] teaches there are only two types of general interconnect line segments in this embodiment with Double-Reach Length lines and Deca-Reach Length lines, demonstrating construction of interconnection symbols according to predefined architectural requirements.
each of the tile interconnection line symbols including several communication ports; Agrawal [0040] teaches the Double-Reach Length line has 3 signal tap points corresponding to the 3 nodes spanned by the line with respective left, middle and right tap points, demonstrating multiple communication ports in interconnection line symbols.
integrating several tile interconnection line symbols into a top-level schematic; Agrawal [0069] teaches the tiling arrangement may be used for arranging Generically-variable Logic Blocks relative to one another and relative to corresponding ISM blocks and switchboxes, demonstrating integration of multiple interconnected elements into a complete top-level arrangement.
Agrawal differs from the claimed invention in that it does not explicitly disclose integrating several PRIM devices into one grid device; abstracting each tile device into a corresponding tile device symbol.
Wang teaches integrating several PRIM devices into one grid device; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters working together as a unified structure, demonstrating integration of primitive electronic devices into a single logic block unit.
Wang teaches abstracting each tile device into a corresponding tile device symbol; Wang [0028] teaches the logic block can be configured to implement hundreds of logic functions such as a 1-bit full adder and 5-bit detector, demonstrating symbolic representation of configurable tile devices with different functional capabilities.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to create a comprehensive FPGA construction methodology. Agrawal provides the hierarchical interconnect architecture and tiling framework but lacks primitive device integration and symbolic abstraction. Wang contributes the essential primitive logic block integration techniques and symbolic representation capabilities that form the foundation of Agrawal's tile structures. A person of ordinary skill would combine these teachings to achieve a complete FPGA design flow from primitive components to top-level schematics.
In regards to claim 2 (Agrawal) does not show the method of claim 1, wherein the step "integrating several PRIM devices into one grid device" comprises a step of integrating several PRIM devices and special logic units for storing configuration points into a grid device schematic:
Wang teaches wherein the step "integrating several PRIM devices into one grid device"; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters working together as a unified structure, demonstrating integration of primitive electronic devices into a single logic block unit.
Wang teaches comprises a step of integrating several PRIM devices and special logic units for storing configuration points into a grid device schematic; Wang [0046] teaches programmable switches use switches and programmable nonvolatile memory, demonstrating integration of configuration storage units with logic devices.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to enhance FPGA construction with integrated configuration storage capabilities. Wang's configuration memory integration techniques would naturally be applied to Agrawal's tile-based architecture to create more efficient programmable structures with embedded configuration points, improving overall FPGA functionality and reducing external configuration requirements.
In regards to claim 3 (Agrawal) does not show the method of claim 1, wherein the PRIM device includes at least one cell electronics:
Wang teaches wherein the PRIM device includes at least one cell electronics; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters, demonstrating that primitive devices include electronic cell components.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to specify the electronic components within primitive devices for Agrawal's hierarchical architecture. Wang's detailed electronic cell specifications would naturally be incorporated into Agrawal's FPGA construction methodology to define the fundamental building blocks, ensuring proper electronic implementation of the hierarchical design.
In regards to claim 4 (Agrawal) does not show the method of claim 1, wherein different tile devices achieve different functions:
Wang teaches wherein different tile devices achieve different functions; Wang [0028] teaches the logic block can be configured to implement hundreds of logic functions such as a 1-bit full adder, 5-bit detector, 4-bit comparator, and parity generator, demonstrating different tile devices achieving different functions.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to provide functional diversity within Agrawal's tile-based architecture. Wang's configurable logic functions would be naturally integrated into Agrawal's tile devices to create a more versatile FPGA construction system capable of implementing various logic operations within the hierarchical framework.
In regards to claim 5 (Agrawal) does not show the method of claim 1, wherein the predefined interconnection requirement comprises the physical layout of the connections between the PRIM devices in different tile devices:
Wang teaches wherein the predefined interconnection requirement comprises the physical layout of the connections between the PRIM devices in different tile devices; Wang [0039] teaches through dedicated lines the outputs can connect to its most adjacent neighbors to the east, north, south, and west, demonstrating predefined physical layout requirements for connections between devices.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to define specific physical layout requirements for Agrawal's interconnection architecture. Wang's directional connection specifications would naturally be applied to Agrawal's tile interconnection requirements to create more precise and efficient physical routing implementations.
In regards to claim 6 (Agrawal) shows the method of claim 1:
wherein after integrating several tile interconnection line symbols into a top-level schematic; Agrawal [0069] teaches the tiling arrangement may be used for arranging Generically-variable Logic Blocks relative to one another and relative to corresponding ISM blocks and switchboxes, demonstrating integration of multiple interconnected elements into a complete top-level arrangement.
the method further comprises a step of verifying the architecture information of the top-level schematic according to different tile interconnection line symbols; Agrawal [0099] teaches place-and-route software that searches for cluster-like signal duplicating needs in design problems and analyzes whether signals match to the taps of interconnection lines, demonstrating a verification module that analyzes architecture information according to different tile interconnection line characteristics.
In regards to claim 7 (Agrawal) shows an apparatus for constructing an FPGA chip top-level schematic comprising:
a second integration module for integrating several grid devices into one tile device; Agrawal [0072] teaches each GLB tile includes a Block Output Switch Matrix and direct-connect sourcing node, demonstrating integration of multiple functional blocks into tile structures.
a morphological building block for constructing each tile device symbol into a tile interconnection line symbol of at least one corresponding form according to a predefined interconnection requirement; Agrawal [0039] teaches there are only two types of general interconnect line segments in this embodiment with Double-Reach Length lines and Deca-Reach Length lines, demonstrating construction of interconnection symbols according to predefined architectural requirements.
in which each of the tile interconnection line symbols includes several communication ports; Agrawal [0040] teaches the Double-Reach Length line has 3 signal tap points corresponding to the 3 nodes spanned by the line with respective left, middle and right tap points, demonstrating multiple communication ports within interconnection line symbols.
a third integration module for integrating several tile interconnection line symbols into a top-level schematic; Agrawal [0069] teaches the tiling arrangement may be used for arranging Generically-variable Logic Blocks relative to one another and relative to corresponding ISM blocks and switchboxes, demonstrating integration of multiple interconnected elements into a complete top-level arrangement.
Agrawal differs from the claimed invention in that it does not explicitly disclose a first integration module for integrating several PRIM devices into one grid device; an abstract module for abstracting each tile device into a corresponding tile device symbol.
Wang teaches a first integration module for integrating several PRIM devices into one grid device; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters working together as a unified structure, demonstrating integration of primitive electronic devices into a single logic block unit.
Wang teaches an abstract module for abstracting each tile device into a corresponding tile device symbol; Wang [0028] teaches the logic block can be configured to implement hundreds of logic functions such as a 1-bit full adder and 5-bit detector, demonstrating symbolic representation of configurable tile devices with different functional capabilities.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to create a modular apparatus for FPGA construction. Agrawal provides the architectural framework and interconnection modules, while Wang contributes the primitive integration modules and symbolic abstraction capabilities. A person of ordinary skill would combine these discrete functional components to build a comprehensive FPGA construction apparatus.
In regards to claim 8 (Agrawal) shows:
wherein the apparatus further comprises a verification module for verifying the architecture information of the top-level schematic according to different tile interconnection line symbols; Agrawal [0099] teaches place-and-route software that searches for cluster-like signal duplicating needs in design problems and analyzes whether signals match to the taps of interconnection lines, demonstrating a verification module that analyzes architecture information according to different tile interconnection line characteristics.
In regards to claim 9 (Agrawal) shows an apparatus for constructing an FPGA chip top-level schematic:
the apparatus comprising a processor and a memory storing program instructions coupled to the processor; Agrawal [0106] teaches providing computer-understandable instructions to computers for causing the computers to perform automated place-and-route operations within computer-readable media, demonstrating processor and memory apparatus with program instructions for FPGA construction.
the processor being configured to execute the program instructions of memory storage in order to implement the method for constructing an FPGA chip top-level schematic which comprises; Agrawal [0033] teaches place-and-route determining means executing place-and-route software in an instructable other machine for programmably configuring FPGA, demonstrating processor execution of stored instructions to implement FPGA construction methods.
integrating several grid devices into one tile device; Agrawal [0072] teaches each GLB tile includes a Block Output Switch Matrix and direct-connect sourcing node, demonstrating integration of multiple functional blocks into tile structures.
constructing each tile device symbol into a tile interconnection line symbol of at least one corresponding form according to a predefined interconnection requirement; Agrawal [0039] teaches there are only two types of general interconnect line segments in this embodiment with Double-Reach Length lines and Deca-Reach Length lines, demonstrating construction of interconnection symbols according to predefined architectural requirements.
each of the tile interconnection line symbols including several communication ports; Agrawal [0040] teaches the Double-Reach Length line has 3 signal tap points corresponding to the 3 nodes spanned by the line with respective left, middle and right tap points, demonstrating multiple communication ports in interconnection line symbols.
integrating several tile interconnection line symbols into a top-level schematic; Agrawal [0069] teaches the tiling arrangement may be used for arranging Generically-variable Logic Blocks relative to one another and relative to corresponding ISM blocks and switchboxes, demonstrating integration of multiple interconnected elements into a complete top-level arrangement.
Agrawal differs from the claimed invention in that it does not explicitly disclose integrating several PRIM devices into one grid device; abstracting each tile device into a corresponding tile device symbol.
Wang teaches integrating several PRIM devices into one grid device; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters working together as a unified structure, demonstrating integration of primitive electronic devices into a single logic block unit.
Wang teaches abstracting each tile device into a corresponding tile device symbol; Wang [0028] teaches the logic block can be configured to implement hundreds of logic functions such as a 1-bit full adder and 5-bit detector, demonstrating symbolic representation of configurable tile devices with different functional capabilities.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to implement the FPGA construction methodology in a processor-based system. Agrawal's place-and-route software framework provides the foundation for processor implementation, while Wang's techniques would be naturally incorporated as software modules executing on the processor to create a complete automated FPGA construction system.
In regards to claim 11 (Agrawal) does not show the apparatus of claim 9, wherein the step "integrating several PRIM devices into one grid device" comprises a step of integrating several PRIM devices and special logic units for storing configuration points into a grid device schematic:
Wang teaches wherein the step "integrating several PRIM devices into one grid device"; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters working together as a unified structure, demonstrating integration of primitive electronic devices into a single logic block unit.
Wang teaches comprises a step of integrating several PRIM devices and special logic units for storing configuration points into a grid device schematic; Wang [0046] teaches programmable switches use switches and programmable nonvolatile memory, demonstrating integration of configuration storage units with logic devices.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to enhance FPGA construction with integrated configuration storage capabilities. Wang's configuration memory integration techniques would naturally be applied to Agrawal's tile-based architecture to create more efficient programmable structures with embedded configuration points, improving overall FPGA functionality and reducing external configuration requirements.
In regards to claim 12 (Agrawal) does not show the apparatus of claim 9, wherein the PRIM device includes at least one cell electronics:
Wang teaches wherein the PRIM device includes at least one cell electronics; Wang [0029] teaches the logic blocks consist of two transmission gates, seven switches, and three inverters, demonstrating that primitive devices include electronic cell components.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to specify the electronic components within primitive devices for Agrawal's hierarchical architecture. Wang's detailed electronic cell specifications would naturally be incorporated into Agrawal's FPGA construction methodology to define the fundamental building blocks, ensuring proper electronic implementation of the hierarchical design.
In regards to claim 13 (Agrawal) does not show the apparatus of claim 9, wherein different tile devices achieve different functions:
Wang teaches wherein different tile devices achieve different functions; Wang [0028] teaches the logic block can be configured to implement hundreds of logic functions such as a 1-bit full adder, 5-bit detector, 4-bit comparator, and parity generator, demonstrating different tile devices achieving different functions.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to provide functional diversity within Agrawal's tile-based architecture. Wang's configurable logic functions would be naturally integrated into Agrawal's tile devices to create a more versatile FPGA construction system capable of implementing various logic operations within the hierarchical framework.
In regards to claim 14 (Agrawal) does not show the apparatus of claim 9, wherein the predefined interconnection requirement comprises the physical layout of the connections between the PRIM devices in different tile devices:
Wang teaches wherein the predefined interconnection requirement comprises the physical layout of the connections between the PRIM devices in different tile devices; Wang [0039] teaches through dedicated lines the outputs can connect to its most adjacent neighbors to the east, north, south, and west, demonstrating predefined physical layout requirements for connections between devices.
The motivation to combine Agrawal and Wang at the effective filing date of the invention is to define specific physical layout requirements for Agrawal's interconnection architecture. Wang's directional connection specifications would naturally be applied to Agrawal's tile interconnection requirements to create more precise and efficient physical routing implementations.
In regards to claim 15 (Agrawal) shows the apparatus of claim 9:
wherein after integrating several tile interconnection line symbols into a top-level schematic; Agrawal [0069] teaches the tiling arrangement may be used for arranging Generically-variable Logic Blocks relative to one another and relative to corresponding ISM blocks and switchboxes, demonstrating integration of multiple interconnected elements into a complete top-level arrangement.
the method further comprises a step of verifying the architecture information of the top-level schematic according to different tile interconnection line symbols; Agrawal [0099] teaches place-and-route software that searches for cluster-like signal duplicating needs in design problems and analyzes whether signals match to the taps of interconnection lines, demonstrating a verification module that analyzes architecture information according to different tile interconnection line characteristics.
Response to Argument
Applicant's arguments filed on August 28, 2025 have been fully considered but they are not persuasive.
The applicant argues that the combination of Agrawal and Wang fails to teach "abstracting each tile device into a corresponding tile device symbol" and "constructing each tile device symbol into a tile interconnection line symbol." However, the examiner respectfully disagrees.
Agrawal [0069] teaches "tiling arrangement for arranging Generically-variable Logic Blocks (GLB's) such as the illustrated blocks 410-460 relative to one another and relative to corresponding ISM blocks and switchboxes," demonstrating symbolic representation of tile structures in a design methodology. Agrawal [0033] teaches that "operations of the placer-and-router are controlled in part by routing navigation rules associated with the interconnect structure," showing that the physical FPGA elements are represented abstractly for design tool manipulation. This constitutes the claimed abstraction of tile devices into symbols.
Wang [0028] teaches that "the logic block can be configured to implement hundreds of logic functions such as a 1-bit full adder, 5-bit all-one or all-zero detector, 4-bit equality or inequality comparator," demonstrating functional abstraction where physical logic blocks are represented by their configurable capabilities. This teaches symbolic representation of configurable devices with different functional capabilities, which corresponds to the claimed tile device symbols.
The applicant's argument that Wang merely discloses "configurable functions" rather than "symbolic representation" is based on an overly narrow interpretation. The configurable logic functions (1-bit adder, 5-bit detector) inherently represent symbolic abstractions of the underlying physical logic blocks. A person of ordinary skill would understand that representing a complex logic block by its functional capability (e.g., "1-bit adder") constitutes symbolic abstraction for design purposes.
Agrawal [0040] teaches interconnection lines with "3 signal tap points corresponding to the 3 nodes spanned by the line with respective left, middle and right tap points," demonstrating interconnection line symbols with multiple communication ports as claimed. The tap points function as communication ports within the symbolic representation of the interconnection structure.
The applicant argues that Agrawal's place-and-route software only performs "routing optimization and signal matching" rather than "verifying architecture information according to different tile interconnection line symbols." However, the examiner respectfully disagrees.
Agrawal [0099] teaches place-and-route software that "searches for cluster-like, signal duplicating needs in design problems and analyzes whether signals match to the taps of interconnection lines," demonstrating verification of architectural compatibility between design requirements and available interconnection resources. This analysis necessarily involves verifying the architecture information of the interconnection structure according to the characteristics of different interconnection line types (e.g., 2×RL vs. 10×RL lines with different tap configurations).
Agrawal [0033] teaches that "operations of the placer-and-router are controlled in part by routing navigation rules associated with the interconnect structure," showing that the software verifies compliance between design requirements and architectural constraints. This constitutes verification of architecture information according to different interconnection line characteristics.
The applicant's distinction between "routing optimization" and "architectural verification" is artificial. The claimed verification step necessarily involves analyzing whether the top-level schematic architecture is compatible with the available tile interconnection resources, which is exactly what Agrawal's place-and-route software performs when matching signals to interconnection line taps.
These claims depend from independent claims 1 and 9 respectively and are unpatentable for the same reasons. The examiner's original analysis showing that Wang [0046] teaches configuration storage units and Wang [0029] teaches electronic cell components in primitive devices remains applicable and unrefuted by applicant's arguments.
Applicant's arguments regarding the remaining claims have been fully considered but are not persuasive for the reasons stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on (571)-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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