DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Independent claim 21 states that "the first input of the output logic circuit is connected to the data output of the circuit state element through a first signal path that bypasses the first delay circuit". Technically, a signal path bypasses a circuit when said signal path is connected between an input and an output of said circuit. Nevertheless, the application does not disclose any embodiment in which a signal path bypasses the first delay circuit as claimed (see Figures 4A, 4C, 4D and 6). This rejection applies to Independent Claims 32 and 37, mutatis mutandis. Dependent claims 22-31, 33-36 and 38-40 fail to remedy these issues.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 states that "the first input of the output logic circuit is connected to the data output of the circuit state element through a first signal path that bypasses the first delay circuit" – thus is not clearly defined. The claim attempts to define the subject-matter in terms of the result to be achieved, in particular the result of generating an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal which merely amounts to a statement of the underlying problem, without providing the specific structural limitations characterizing the function of the claimed output logic circuit necessary for achieving this result. This rejection applies to Independent Claims 32 and 37, mutatis mutandis. Dependent claims 22-31, 33-36 and 38-40 fail to remedy these issues.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 32-34, and 36 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by de Gruijl (US 2011/0018585).
Regarding Claim 32, de Gruijl discloses a method of edge combining in an electronic timing system [Fig 1: 0019], the method controlling a first input of a circuit state element based on a first timing signal [#102 of Fig 1; 0019]; resetting the circuit state element by controlling a second input of the circuit state element with a pulse generator that receives a second timing signal [#102, #106 of Fig 1; 0020]; delaying a data output signal from a data output of the circuit state element to generate a delayed data output signal using a first delay circuit [#102 #104 of Fig 1; 0019-20; 0031-32]; and generating an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal using an output logic circuit that receives the data output signal and the delayed data output signal [#104, #106 of Fig 1; Fig 4; 0031-33].
Regarding Claim 33, de Gruijl also discloses delaying the first timing signal to the first input of the circuit state element using a second delay circuit [#102 of Fig 1; 0019-20].
Regarding Claim 34, de Gruijl also discloses processing the data output signal and the delayed data output signal using a two-input logic gate [#104 of Fig 1; 0019-20].
Regarding Claim 36, de Gruijl also discloses controlling a pulse width of the pulse generator based on a time delay from the edge of the second timing signal [#108 of Fig 1; 0019-20].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-23, 25, 27-30, 37, and 39-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over de Gruijl (US 2011/0018585) in view of Flores (US 2021/0211132).
Regarding Claim 21, de Gruijl teaches an edge combiner with symmetrical operation range, the edge combiner [#100 of Fig 1, Fig 4; 0019] comprising: a circuit state element including a first input controlled by a first timing signal, a second input, and a data output [#102, R, Q of Fig 1; 0019-20]; a first pulse generator configured to reset the circuit state element based on a second timing signal [#102, #106, #108 of Fig 1; Fig 4; 0019-20; 0032]; a first delay circuit [#104 of Fig 1; 0019-20]; and an output logic circuit [#106 of Fig 1; 0019-20] …a second input connected to the data output of the circuit state element through a second signal path that includes the first delay circuit [#102, #104, S, Q of Fig 1; 0019-20], and an output configured to generate an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal [Fig 4; 0031-33]. de Gruijl does not explicitly teach – but Flores does teach including a first input connected to the data output of the circuit state element through a first signal path that bypasses the first delay circuit [0006; 0015]. It would have been obvious to modify the device of de Gruijl to include a circuit bypass of the first delay circuit to provide a bypass control signal at the first reset output responsive to the reset signal and provide a reset control signal at the second reset output responsive to the reset signal and delayed relative to the bypass control signal.
Regarding Claim 37, de Gruijl teaches an time of flight system comprising: an edge combiner [#100 of Fig 1, Fig 4; 0019] comprising: a circuit state element including a first input controlled by a first timing signal, a second input, and a data output [#102, R, Q of Fig 1; 0019-20]; a pulse generator configured to reset the circuit state element based on a second timing signal [#102, #106, #108 of Fig 1; Fig 4; 0019-20; 0032]; a first delay circuit [#104 of Fig 1; 0019-20]; and an output logic circuit [#106 of Fig 1; 0019-20] … a second input connected to the data output of the circuit state element through a second signal path that includes the first delay circuit [#102, #104, S, Q of Fig 1; 0019-20], and an output configured to generate an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal [Fig 4; 0031-33]; and a driver circuit configured to control an emission of light from a light emitting element based on the output signal. de Gruijl does not explicitly teach – but Flores does teach including a first input connected to the data output of the circuit state element through a first signal path that bypasses the first delay circuit [0006; 0015]. It would have been obvious to modify the device of de Gruijl to include a circuit bypass of the first delay circuit to provide a bypass control signal at the first reset output responsive to the reset signal and provide a reset control signal at the second reset output responsive to the reset signal and delayed relative to the bypass control signal.
Regarding Claims 22 and 39, de Gruijl also teaches a second delay circuit including an input that receives the first timing signal and an output that provides a delayed version of the first timing signal to the first input of the circuit state element [#102 of Fig 1; 0019-20].
Regarding Claim 23, de Gruijl also teaches wherein the output logic circuit is a two input logic gate [#104 of Fig 1; 0019-20].
Regarding Claim 25, de Gruijl also teaches wherein a pulse width of the first pulse generator is based on a time delay from the edge of the second timing signal [#108 of Fig 1; 0019-20].
Regarding Claim 27, de Gruijl also teaches wherein the circuit state element includes a d-type flip-flop [0019-21; 0028].
Regarding Claim 28, de Gruijl also teaches wherein the d-type flip-flop includes a data input connected to a fixed voltage, wherein the first input of the d-type flip-flop corresponds to a clock input and the second input of the d-type flip-flop corresponds to a reset input [0019-21; 0028].
Regarding Claim 29, de Gruijl also teaches wherein the circuit state element includes a set-reset latch [0005; Claim 7].
Regarding Claim 30, de Gruijl also teaches, wherein the first input of the set-reset latch corresponds to a set input, and the second input of the set-reset latch corresponds to a reset input [0005; Claim 7].
Regarding Claim 40, de Gruijl also teaches wherein the circuit state element corresponds to one of a flip-flop or a latch [0019-21; 0028].
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gruijl (US 2011/0018585), as applied to claim 21 above, and further in view of Shi (US 2014/0197814).
Regarding Claim 24, de Gruijl does not explicitly teach – but Shi does teach a feedback path configured to control a pulse width of the first pulse generator based on timing of the output signal [0024; 0045]. It would have been obvious to modify the device of de Griujl to include a pulse control as feedback mechanisms may be applied to control the difference between output voltage and a desired target output voltage by adjusting the pulse width.
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gruijl (US 2011/0018585) in view of Flores (US 2021/0211132), as applied to claim 32 above, and further in view of Shi (US 2014/0197814).
Regarding Claim 35, de Gruijl does not explicitly teach – but Shi does teach controlling a pulse width of the pulse generator based on timing of the output signal [0024; 0045]. It would have been obvious to modify the device of de Griujl to include a pulse control as feedback mechanisms may be applied to control the difference between output voltage and a desired target output voltage by adjusting the pulse width.
Claim(s) 26, 31, and 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gruijl (US 2011/0018585) in view of Flores (US 2021/0211132), as applied to claims 21, 29, and 37 above, and further in view of Jung (US 2015/0263740).
Regarding Claim 26, de Griujl does not explicitly teach – but Jung does teach wherein the edge of the first timing signal and the edge of the second timing signal are each one of a rising edge or a falling edge [0032; 0037-38; 0042-44]. It would have been obvious to modify the system of de Griujl to use rising or falling edges for a timing signal as when tracking operation has completed, a pulse width of the timing signal is the same as a delay amount of the variable delay line circuit.
Regarding Claim 31, de Griujl does not explicitly teach – but Jung does teach a second pulse generator configured to control the first input based on the first timing signal [0008; 0042; 0048]. It would have been obvious to modify the system of de Griujl to include a second pulse generation pulse as the selection circuit selects the second feedback signal as the pulse signal, the variable delay line circuit receives the pulse signal generated using the pulse retainer circuit and generates the output signal.
Regarding Claim 38, de Griujl does not explicitly teach – but Jung does teach a first delay locked loop (DLL) configured to generate the first timing signal and a second DLL configured to generate the second timing signal [0008; 0026-29]. It would have been obvious to modify the system of de Griujl to include multiple timing signals and delays to determine the delay amount of the variable delay line circuit, adjusting the delay amount so that a phase difference between the input signal and the first feedback signal becomes zero.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES R HULKA whose telephone number is (571)270-7553. The examiner can normally be reached M-R: 9am-6pm, F: 10am-2pm.
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JAMES R. HULKA
Primary Examiner
Art Unit 3645
/JAMES R HULKA/Primary Examiner, Art Unit 3645