Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the response to amendment filed 3/20/2026 in which Claims 1-9, 20, 21 are pending.
Response to Arguments
Applicant's arguments filed 3/20/2026 have been fully considered but they are not persuasive. Applicant argues that Zhu fails to disclose “wherein a respective stage of the scan circuit comprises a first scan unit and a second scan unit configured to provide control signals to different rows of subpixels, output from the first scan unit being input to the second scan unit through at least one of M rows of subpixels, M being an integer ≥ 2”. Examiner contends that each of first and second scan units are provided in the same group to provide control signals to different rows of subpixels output from the first scan unit and input to the second scan unit through at least two rows of subpixels as shown in the annotated illustration below.
Applicant further argues that a first group of cascaded shift registers and a second group of cascaded shift registers are equated to the first scan unit and second scan unit respectively. Examiner has modified the annotations of the illustration below to reflect that each of first and second scan units are provided in the same cascaded group to provide control signals to different rows of subpixels output from the first scan unit and input to the second scan unit through at least two rows of subpixels.
Applicant further argues that Zhu fails to teach or suggest that “a first scan unit and a second scan unit configured to provide control signals to different rows of subpixels”. Examiner has modified the annotations of the illustration below to reflect that each of first and second scan units are provided in the same cascaded group to provide control signals to different rows of subpixels output from the first scan unit and input to the second scan unit through at least two rows of subpixels.
Applicant further argues that Zhu fails to teach or suggest that “output from the first scan unit being input to the second scan unit through at least one of M rows of subpixels, M being an integer ≥ 2”. Examiner has modified the annotations of the illustration below to reflect that each of first and second scan units are provided in the same cascaded group to provide control signals to different rows of subpixels output from the first scan unit and input to the second scan unit through at least two rows of subpixels. Specifically, in Figure 10, signal “F/F1” is a first row of subpixels output from the first scan unit and input to the second scan unit as signal “E”. Signal “F/F2” is a second row of subpixels output from second scan unit.
Applicant further argues that Zhu fails to teach or suggest that “output from the first scan unit being input to the second scan unit”. Examiner has modified the annotations of the illustration below to reflect that each of first and second scan units are provided in the same cascaded group to provide control signals to different rows of subpixels output from the first scan unit and input to the second scan unit through at least two rows of subpixels. Specifically, in Figure 10, signal “F/F1” is a first row of subpixels output from the first scan unit and input to the second scan unit as signal “E”. Signal “F/F2” is a second row of subpixels output from second scan unit.
Applicant further argues that Zhu fails to teach or suggest that “output from the first scan unit being input to the second scan unit”. Examiner has modified the annotations of the illustration below to reflect that each of first and second scan units are provided in the same cascaded group to provide control signals to different rows of subpixels output from the first scan unit and input to the second scan unit through at least two rows of subpixels. Specifically, in Figure 10, signal “F/F1” is a first row of subpixels output from the first scan unit and input to the second scan unit as signal “E”. Signal “F/F2” is a second row of subpixels output from second scan unit.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 20, 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication 2019/0333433 to Zhu et al (“Zhu”).
As to Claim 1, Zhu teaches a scan circuit, comprising a plurality of stages, wherein a respective stage of the scan circuit comprises a first scan unit and a second scan unit configured to provide control signals to different rows of subpixels (shift registers 4 include a first group of cascaded shift registers 401 and a second group of cascaded shift registers 402. The first group of cascaded shift registers 401 and the second group of cascaded shift registers 402 are disposed in two respective peripheral circuit areas NAA, which are disposed on two opposite sides of a display area AA. The shift registers 4 at the same stage in the first group of cascaded shift registers 401 and the second group of cascaded shift registers 402 are electrically connected to a same scanning line 1 for synchronously outputting scan driving signals to the same scanning line 1 through drive signal output ends F, see ¶ 0052), output from the first scan unit being input to the second scan unit through at least one of M rows of subpixels, M being an integer > 2 (the shift registers 4 at the first stage in the first group of cascaded shift registers 401 and the second group of cascaded shift registers 402 are electrically connected the same trigger signal line 9. The trigger signal line 9 is used for transferring a trigger signal to trigger signal input ends E of the shift registers 4 at the first stage in the first group of cascaded shift registers 401 and the second group of cascaded shift registers 402, see ¶ 0054; Specifically, in Figure 10, signal “F/F1” is a first row of subpixels output from the first scan unit and input to the second scan unit as signal “E”. Signal “F/F2” is a second row of subpixels output from second scan unit).
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As to Claim 2, Zhu depending on Claim 1, Zhu teaches wherein the first scan unit and the second scan unit are configured to provide control signals to the M rows of subpixels in a display panel, the first scan unit and the second scan unit being on two opposite sides of the M rows of subpixels, respectively (shift registers 4 include a first group of cascaded shift registers 401 and a second group of cascaded shift registers 402. The first group of cascaded shift registers 401 and the second group of cascaded shift registers 402 are disposed in two respective peripheral circuit areas NAA, which are disposed on two opposite sides of a display area AA. The shift registers 4 at the same stage in the first group of cascaded shift registers 401 and the second group of cascaded shift registers 402 are electrically connected to a same scanning line 1 for synchronously outputting scan driving signals to the same scanning line 1 through drive signal output ends F, see ¶ 0052).
As to Claim 3, Zhu depending on Claim 1, Zhu teaches wherein a length of each of the first scan unit and the second scan unit along a column direction spans over the M rows of subpixels (Figure 10, annotated above, illustrates a first group of cascaded shift registers 401 and a second group of cascaded shift registers 402 in a column direction spanning along the four rows of subpixels).
As to Claim 4, Zhu depending on Claim 1, Zhu teaches wherein a ratio of a total number of scan units of the scan circuit to a total number of rows of subpixels is (2/M), wherein M≥4 (Figure 10, annotated above, illustrates two groups of shift registers 401 and 402 to 4 rows of subpixels a ratio of 2/4).
As to Claim 5, Zhu depending on Claim 1, Zhu teaches wherein M = 4 (Figure 10, annotated above, illustrates 4 rows of subpixels a ratio of 2/4).
As to Claim 6, Zhu depending on Claim 1, Zhu teaches wherein an n-th stage of the scan circuit comprises a first n-th stage scan unit and a second n-th stage scan unit, n is an integer >1 (Figure 10 illustrates a second shift register in the first group of cascaded shift registers [first n-th stage scan unit] and a second shift register in the second group of shift registers [second n-th stage scan unit]);
wherein the first n-th stage scan unit is configured to receive an output signal from a (n-1)-th stage of the scan circuit as an input signal (Figure 10 illustrates a second shift register in the first group of cascaded shift registers [first n-th stage scan unit] receiving an output signal (E) from a first shift register in the first group of cascaded shift registers [(n-1)th stage of the scan circuit] as an input signal);
an output signal from the first n-th stage scan unit is provided to m1 number of rows of the M rows of subpixels as control signals therein, and subsequently input to the second n-th stage scan unit as an input signal thereof, m1 is an integer < M (Figure 10 illustrates an output signal from the second shift register of the first group of cascaded shift registers is provided to 2 rows of subpixels and input to the second shift register of the second group of cascaded shift registers as an input signal); and
an output signal from the second n-th stage scan unit is provided to m2 number of rows of the M rows of subpixels as control signals therein, and subsequently input to a (n+1)-th stage of the scan circuit as an input signal thereof, m2 is an integer < M, (m1 + m2) = M (Figure 10 illustrates an output signal from a second shift register in the second group of cascaded shift registers [second n-th stage scan unit] provided to 2 rows of subpixels and input to a third shift register in the second group of cascaded shift registers [(n+1)th stage of the scan circuit] as an input signal).
As to Claim 20, Zhu depending on Claim 1, Zhu teaches a display apparatus, comprising the scan circuit, and a display panel comprising a plurality of light emitting elements (The shift registers 4 at respective stages successively outputs the scan driving signals to the respective scanning lines 1 of the display panel. The pixel units 2 [light emitting elements] of the display panel receive corresponding scan driving signals row by row and are turned on accordingly. Each data signal line 8 inputs a data signal to a corresponding pixel unit 2, so that the display panel implements a display function, see ¶ 0060).
As to Claim 21, Zhu depending on Claim 1, Zhu teaches inputting an output signal from the (n-1)-th stage of the scan circuit into the first n-th stage scan unit as an input signal thereof (Figure 10 illustrates a second shift register in the first group of cascaded shift registers [first n-th stage scan unit] receiving an output signal (E) from a first shift register in the first group of cascaded shift registers [(n-1)th stage of the scan circuit] as an input signal);
outputting a first control signal from the first n-th stage scan unit to the m1 number of rows of the M rows of subpixels (Figure 10 illustrates an output signal from the second shift register of the first group of cascaded shift registers is provided to 2 rows of subpixels);
subsequent to outputting the first control signal through subpixels in the m1 number of rows of the M rows of subpixels, inputting the first control signal to the second n-th stage scan unit as an input signal thereof (The trigger signal line 9 is used for transferring a trigger signal to trigger signal input ends E of the shift registers 4 at the first stage in the first group of cascaded shift registers 401 and the second group of cascaded shift registers 402. Exemplarily, the trigger signal may be input synchronously at opposite ends of the trigger signal line 9, see ¶ 0054; Figure 10 illustrates input to a second shift register in the second group of cascaded shift registers [(n)th stage of the scan circuit] as an input signal); and
outputting a second control signal from the second n-th stage scan unit to the m2 number of rows of the M rows of subpixels (The trigger signal line 9 is used for transferring a trigger signal to trigger signal input ends E of the shift registers 4 at the first stage in the first group of cascaded shift registers 401 and the second group of cascaded shift registers 402. Exemplarily, the trigger signal may be input synchronously at opposite ends of the trigger signal line 9, see ¶ 0054; Figure 10 illustrates the signal F/F2 is output from the second shift register of the second group of cascaded shift registers to 2 rows of sub-pixels).
Allowable Subject Matter
Claims 7-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EBONI N GILES whose telephone number is (571)270-7453. The examiner can normally be reached Monday - Friday 9 am - 6 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PATRICK EDOUARD can be reached at (571)272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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