Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the response to after-final amendment filed 6/25/2026 in which Claims 1-9, 20, 21 are pending.
Response to Amendment
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
Response to Arguments
Applicant’s arguments, see page 10, filed 6/25/2026, with respect to the rejection(s) of claim(s) 1-2 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Du.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by U.S. Patent 10,223,992 to Du et al (“Du”).
As to Claim 1, Du teaches a scan circuit, comprising a plurality of stages, wherein a respective stage of the scan circuit comprises a first scan unit and a second scan unit configured to provide control signals to different rows of subpixels (The driving circuit is used to input a scanning signal to a display panel. The display panel includes n rows of pixels. A scanning line set is correspondingly arranged on each of the n rows of pixels. The scanning line set includes a primary scanning line and a secondary scanning line, see Col. 4, lines 13-18; the third stage GOA unit 303 corresponds to the primary scanning line 43 on the third row of pixel and the secondary scanning line 33 on the first row of pixel. The similar condition occurs to the remaining GOA units at other stages. It is understood that 31-37 indicates the secondary scanning lines and 41-47 indicates the primary scanning lines, see Col. 4, lines 29-35; an output terminal of a third stage GOA unit at the left side 303 [first scan unit] is connected to a secondary scanning line 33 of a first row of pixel (that is, a first row of secondary scanning line). An output terminal of a third stage GOA unit at the right side 310 [second scan unit] is also connected to the secondary scanning line 33 of the first row of pixel, see Col. 4, lines 54-59; Figure 5A illustrates secondary scanning line 33 of a first row of pixel connects the left third stage GOA 303 and right third stage GOA 310; primary scanning line 43 of a third row of pixel connects the left third stage GOA 303 and right third stage GOA 310), output from the first scan unit being input to the second scan unit through at least one of M rows of subpixels, M being an integer > 2 (the third stage GOA unit 303 corresponds to the primary scanning line 43 on the third row of pixel and the secondary scanning line 33 on the first row of pixel. The similar condition occurs to the remaining GOA units at other stages. It is understood that 31-37 indicates the secondary scanning lines and 41-47 indicates the primary scanning lines, see Col. 4, lines 29-35; an output terminal of a third stage GOA unit at the left side 303 is connected to a secondary scanning line 33 of a first row of pixel (that is, a first row of secondary scanning line). An output terminal of a third stage GOA unit at the right side 310 is also connected to the secondary scanning line 33 of the first row of pixel, see Col. 4, lines 54-59).
As to Claim 2, Du depending on Claim 1, Du teaches wherein the first scan unit and the second scan unit are configured to provide control signals to the M rows of subpixels in a display panel, the first scan unit and the second scan unit being on two opposite sides of the M rows of subpixels, respectively (The driving circuit is used to input a scanning signal to a display panel. The display panel includes n rows of pixels. A scanning line set is correspondingly arranged on each of the n rows of pixels. The scanning line set includes a primary scanning line and a secondary scanning line, see Col. 4, lines 13-18; the third stage GOA unit 303 corresponds to the primary scanning line 43 on the third row of pixel and the secondary scanning line 33 on the first row of pixel. The similar condition occurs to the remaining GOA units at other stages. It is understood that 31-37 indicates the secondary scanning lines and 41-47 indicates the primary scanning lines, see Col. 4, lines 29-35; an output terminal of a third stage GOA unit at the left side 303 [first scan unit] is connected to a secondary scanning line 33 of a first row of pixel (that is, a first row of secondary scanning line). An output terminal of a third stage GOA unit at the right side 310 [second scan unit] is also connected to the secondary scanning line 33 of the first row of pixel, see Col. 4, lines 54-59; Figure 5A illustrates secondary scanning line 33 of a first row of pixel connects the left third stage GOA 303 and right third stage GOA 310; primary scanning line 43 of a third row of pixel connects the left third stage GOA 303 and right third stage GOA 310).
As to Claim 20, Du depending on Claim 1, Du teaches a display apparatus, comprising the scan circuit, and a display panel comprising a plurality of light emitting elements (The driving circuit is used to input a scanning signal to a display panel. The display panel includes n rows of pixels. A scanning line set is correspondingly arranged on each of the n rows of pixels, see Col. 4, lines 12-17).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
11. Claim(s) 3-5, 21 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 10,223,992 to Du et al (“Du”) in view of U.S. Patent Publication 2019/0333433 to Zhu et al (“Zhu”).
As to Claim 3, Du depending on Claim 1, Du does not expressly disclose wherein a length of each of the first scan unit and the second scan unit along a column direction spans over the M rows of subpixels. Zhu teaches wherein a length of each of the first scan unit and the second scan unit along a column direction spans over the M rows of subpixels (Figure 10, annotated above, illustrates a first group of cascaded shift registers 401 and a second group of cascaded shift registers 402 in a column direction spanning along the four rows of subpixels).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Du with Zhu to teach wherein a length of each of the first scan unit and the second scan unit along a column direction spans over the M rows of subpixels. The suggestion/motivation would have been in order for the number of pixel units in each row to be substantially the same (see ¶ 0031).
As to Claim 4, Du depending on Claim 1, Du does not expressly disclose wherein a ratio of a total number of scan units of the scan circuit to a total number of rows of subpixels is (2/M), wherein M≥4. Zhu teaches wherein a ratio of a total number of scan units of the scan circuit to a total number of rows of subpixels is (2/M), wherein M≥4 (Figure 10, annotated above, illustrates two groups of shift registers 401 and 402 to 4 rows of subpixels a ratio of 2/4).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Du with Zhu to teach wherein a ratio of a total number of scan units of the scan circuit to a total number of rows of subpixels is (2/M), wherein M≥4. The suggestion/motivation would have been in order for the number of pixel units in each row to be substantially the same (see ¶ 0031).
As to Claim 5, Du depending on Claim 1, Du does not expressly disclose wherein M=4. Zhu teaches wherein M = 4 (Figure 10, annotated above, illustrates 4 rows of subpixels a ratio of 2/4).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Du with Zhu to teach wherein M=4. The suggestion/motivation would have been in order for the number of pixel units in each row to be substantially the same (see ¶ 0031).
Allowable Subject Matter
Claims 7-9, 21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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