DETAILED ACTION
This action is responsive to U.S. Patent Application No. 17/908,652 filed on 1 September 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
The application’s status as a 371 of PCT/CN2021/126089, claiming priority to CN202110276322.9 is confirmed.
Election/Restrictions
Applicant’s election without traverse of the Group I invention and Species VI embodiment thereof in the reply filed on 24 February 2025 is acknowledged.
Claims 6-9 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 24 February 2025.
Response to Arguments
Applicant's arguments filed 25 November 2025 have been fully considered but they are not persuasive.
Claim 5 (which Applicant incorporated into currently amended independent claim 1, along with intervening claims 3 and 4) was rejected under 35 U.S.C. § 103 over Chinese Patent Publication No. CN111725242A (published Sept. 2, 2020) (hereinafter “Liang”) in view of U.S. Patent Publication No. 2018/0197887 (published July 12, 2018) (hereinafter “Liu”) and U.S. Patent Publication No. 2017/0263734 (published Sept. 14, 2017) (hereinafter “Xie”). Applicant’s arguments are entirely directed to the teachings of Xie. Nowhere in Applicant’s response does Applicant address the combination of Xie with either Liang or Liu. “One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references.” MPEP § 2145(V) (citing In re Keller, 642 F.2d 413 (CCPA 1981) and In re Merck & Co., Inc., 800 F.2d 1091 (Fed. Cir. 1986)). “Where a rejection of a claim is based on two or more references, a reply that is limited to what a subset of the applied references teaches or fails to teach, or that fails to address the combined teaching of the applied references may be considered to be an argument that attacks the reference(s) individually.” MPEP § 2145(V). “The test for obviousness is what the combined teachings of the references would have suggested to a PHOSITA.” Id. (quoting In re Mouttet, 686 F.3d 1322, 1333 (Fed. Cir. 2012)). In the instant case, Applicant provides three arguments, each regarding the teachings of Xie, but does not address the combined teachings of Xie and Liu, or the combined teachings of Xie, Liang, and Liu. Accordingly, Applicant’s arguments are unpersuasive.
Regarding Applicant’s first point, Applicant argues:
Firstly, Xie's technical solution is applied to a bottom-gate, top-gate or dual-gate TFT Xie's technical solution does not involve "oxygen supplementation layer" at all. The technical purpose of Xie is to prevent metal ions (such as Cu) from the source/drain electrodes from diffusing into the active layer. It is clear that the technical solutions of amended claim 1 and Xie are fundamentally different. Xie addresses the problem of metal contamination, while the technical solution of amended claim 1 addresses the defects (oxygen vacancies) in the active layer.
Applicant Arguments/Remarks Made in an Amendment (filed 25 November 2025) at 7.
The Examiner respectfully notes that Xie is not cited as providing the “oxygen supplementation layer” limitations. Liang is cited as providing the “oxygen supplementation layer” limitation.
Regarding Applicant’s second point, Applicant argues:
Secondly, regarding the first buffer layer, in Xie, the layer corresponds to the first buffer layer is the gate cover layer (126, 326, 426, 496), which is located above the (first or second) gate electrode, and its function (see paragraph [0039]) is to act as a metal diffusion barrier to prevent copper in the gate electrode layer from diffusing into the active layer. It is clear that the first buffer layer in the technical solution of amended claim 1 and the gate cover layer in Xie are located similarly but have different functions. The "gate cover layer" in Xie is used to prevent the gate metal from diffusing upwards, while the first buffer layer in the technical solution of amended claim 1 is used to protect the first gate from being corroded by other film layers. Xie does not disclose any relationship between the gate cover layer and the "oxygen supplementation layer".
Id. at 7.
The Examiner respectfully notes that Applicant appears to cite several functional limitations, such as that the buffer layer is “used to protect the first gate from being corroded by other film layers,” which are not claimed. “Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims.” MPEP § 2145(VI).
Regarding Applicant’s third point, Applicant argues:
Thirdly, regarding the second buffer layer, in amended claim 1, the second buffer layer is located between the second gate and the oxygen supplementation layer, and its function is to act as a spacer layer between the two. In Xie's technical solution, the layer equivalent to the second buffer layer is the gate buffer layer (122, 322, 422, 492), which is located below the (first or second) gate electrode and is between the gate electrode and the layer below (such as the substrate or the active layer), and its function (see paragraph [0039]) is: "to enhance the adhesion between the gate electrode layer and the substrate." It is clear that the second buffer layer in the technical solution of amended claim 1 and the gate buffer layer in Xie are located at completely different positions and have completely different functions. Xie does not disclose setting a buffer layer between a gate and an oxygen supplementation layer at all.
Applicant Arguments/Remarks Made in an Amendment (filed 25 November 2025) at 7-8.
The Examiner respectfully notes that Applicant appears to cite several functional limitations, such as that the second buffer layer’s “function is to act as a spacer layer between the two,” which are not claimed. “Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims.” MPEP § 2145(VI).
Accordingly, Applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 21: claim 21 recites, in relevant part: “wherein a sheet resistance of the oxygen supplementation layer is greater than a sheet resistance of the first buffer layer and a sheet resistance of the second buffer layer, and both the sheet resistance of the first buffer layer and the sheet resistance of the second buffer layer are greater than a sheet resistance of the second gate electrode.” Applicant claims a relationship between the sheet resistances of various layers and structures, but then fails to provide basic parameters for determining the relative sheet resistances of the relevant layers and structures, including thicknesses and material identities (and thus resistivities). Notably, nowhere in the specification does Applicant disclose or reference the materials from which the first and second buffer layers are formed, and nowhere in the specification does Applicant disclose or reference a thickness of the oxygen supplementation layer so as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Thus, claim 21 is directed to subject matter the specification fails to describe.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Claim Rejections - 35 USC § 103
Claims 1, 2, 10, and 21 are rejected under 35 U.S.C. § 103 as being unpatentable over Chinese Patent Publication No. CN111725242A (published Sept. 2, 2020) (hereinafter “Liang”) in view of U.S. Patent Publication No. 2018/0197887 (published July 12, 2018) (hereinafter “Liu”) and U.S. Patent Publication No. 2017/0263734 (published Sept. 14, 2017) (hereinafter “Xie”).
Regarding independent claim 1, Liang discloses: A thin film transistor (FIG. 5, array substrate 100, “The array substrate 100 includes a plurality of sub-pixels, each sub-pixel Pixel includes a pixel driving circuit 101, and the pixel driving circuit 101 includes At least one thin film transistor M.” Translation of CN111725242A at 4.), comprising:
an active layer (FIG. 5, active layer 4, Translation of CN111725242A at 4) disposed on a side of a base substrate (FIG. 5, substrate 1, Translation of CN111725242A at 4);
source (FIG. 5, source electrode 5, Translation of CN111725242A at 4) and drain (FIG. 5, drain electrode 6, Translation of CN111725242A at 4) electrodes disposed on a side, distal from the base substrate, of the active layer (FIG. 5, depicting wherein source and drain electrodes 5 and 6 are disposed on a side of the active layer 4 distal from the substrate 1); and
an oxygen supplementation (FIG. 5, protective pattern 8, “By adopting the above process, oxygen gas is introduced during the sputtering process, and the active layer 4 can be supplemented with oxygen while bombarding the target material to prevent the active layer 4 from becoming conductive.” Translation of CN111725242A at 9.) layer disposed on the side, distal from the base substrate, of the active layer (FIG. 5, depicting wherein the protective pattern 8 is disposed on a side of the active layer 4 distal from the substrate 1) and containing a metal oxide (FIG. 5, “The protective pattern 8 is made of a metal oxide conductive material, which can further improve the ability of the protective pattern 8 to block hydrogen atoms and prevent hydrogen atoms from intruding into the active layer 4 from the spacer region B.” Translation of CN111725242A at 6),
wherein an orthogonal projection of the oxygen supplementation layer (FIG. 5, protective pattern 8) on the base substrate (FIG. 5, substrate 1) is at least partially overlapped with an orthogonal projection of a target portion of the active layer (FIG. 5, depicting wherein active layer 4 has space B, see Translation of CN111725242A at 9) on the base substrate (FIG. 5, depicting wherein orthogonal projections of the protective pattern 8 and space B of the active layer 4 overlap), and
the orthogonal projection of the target portion (FIG. 5, active layer 4 having space B) on the base substrate (FIG. 5, substrate 1) is not overlapped with orthogonal projections of the source (FIG. 5, source electrode 5) and drain electrodes (FIG. 5, drain electrode 5) on the base substrate (FIG. 5, depicting wherein orthogonal projections of the space B of the active layer 4 and source and drain electrodes 5 and 6 do not overlap),
the thin film transistor (FIG. 5, array substrate 100, “The array substrate 100 includes a plurality of sub-pixels, each sub-pixel Pixel includes a pixel driving circuit 101, and the pixel driving circuit 101 includes At least one thin film transistor M.” Translation of CN111725242A at 4.) further coomprising:
a first gate electrode (FIG. 5, gate electrode 2, Translation of CN111725242A at 6),
a first insulation layer (FIG. 5, gate insulating layer 3, Translation of CN111725242A at 6), and
a second insulation layer (FIG. 5, first passivation layer 7, Translation of CN111725242A at 5);
wherein the first gate electrode, the first insulation layer, the active layer, the source and drain electrodes, the second insulation layer, and the oxygen supplementation layer are sequentially laminated in a direction away from the base substrate (FIG. 5, depicting wherein the gate electrode 2, gate insulating layer 3, active layer 4, source electrode 5 and drain electrode 6, first passivation layer 7, and protective pattern 8 are laminated in that particular sequential order in a direction away from the substrate 1).
Liang does not specifically disclose wherein the thin film transistor further comprises a second gate electrode; wherein the second gate electrode is disposed on a side, distal from the base substrate, of the oxygen supplementation layer, and an orthogonal projection of the second gate electrode on the base substrate is at least partially overlapped with the orthogonal projection of the target portion on the base substrate.
In the same field of endeavor, however, Liu discloses a thin film transistor (FIG. 4, thin film transistor 200, [0051]) having a dual-gate configuration and including a first gate electrode (FIG. 4, bottom gate electrode 202, [0052]) and a second gate electrode (FIG. 4, second floating gate electrode 2092, [0053]) disposed on another conductive layer (FIG. 4, first floating gate electrode 2091, [0053]), wherein the second gate electrode is disposed on a side of the conductive layer distal from a base substrate (FIG. 4, depicting wherein the second floating gate electrode is disposed on a side of the first floating gate electrode 2091 distal from the substrate 201, [0052]), and an orthogonal projection of the second gate electrode (FIG. 4, second floating gate electrode 2092) on a substrate is at least partially overlapped with an orthogonal projection of a portion of an active layer on the base substrate (FIG. 4, depicting wherein an orthogonal the second floating gate electrode 2092 on the substrate 201 overlaps with an orthogonal projection of a portion of a semiconductor layer 204 disposed between but not overlapping with a source electrode 205 and a drain electrode 206). Regarding the dual-gate configuration, in [0041], Liu states: “the thin film transistor 100 of such structure can be adjusted through the same or the different dual gate voltage, achieving the variation of the threshold voltage, improving the stability of the thin film transistor 100, meanwhile, the mobility of the thin film transistor 100 can be improved to a certain extent.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed thin film transistor of Liang by adding the second floating gate electrode 2092 of Liu in order to provide the capacity for adjustment of the thin film transistor by different dual-gate voltage, to enable variation of threshold voltage, and to improve the stability of the thin film transistor. See Liu [0041].
Moreover, the addition of the second gate electrode as disclosed in Liu in the thin film transistor of Liang would result in the claimed configuration wherein the second gate electrode (Liu FIG. 4, second floating gate electrode 2092) is disposed on a side, distal from the base substrate, of the oxygen supplementation layer (Liang FIG. 5/Liu FIG. 4, the second floating gate electrode 2092 of Liu may be disposed on the protective pattern 8 of Liang in the same manner in which the second floating gate electrode 2092 of Liu is disposed over the first floating gate electrode 2091 of Liu, such that the floating gate electrode 2092 is disposed on side of the protective pattern 8 distal from the substrate 1), and an orthogonal projection of the second gate electrode on the base substrate is at least partially overlapped with the orthogonal projection of the target portion on the base substrate (Liang FIG. 5/Liu FIG. 4, an orthogonal projection of the second floating gate electrode 2092 of Liu may overlap with an orthogonal projection of space B of the active layer 4 of Liang in the same manner in which the second floating gate electrode 2092 of Liu overlaps with the portion of the semiconductor layer 204 of Liu disposed between but not overlapping with a source electrode 205 and a drain electrode 206, such that the orthogonal projections of the second floating gate electrode 2092 and the space B of the active layer 4 overlap).
Liang in view of Liu does not specifically disclose wherein the thin film transistor further comprises: at least one of a first buffer layer and a second buffer layer; wherein the first buffer layer is disposed on a side, distal from the oxygen supplementation layer, of the second gate electrode; and the second buffer layer is disposed between the second gate electrode and the oxygen supplementation layer.
In the same field of endeavor, Xie discloses a thin film transistor (FIG. 4, array substrate 400 including a double gate type TFT, [0077]) including a first buffer layer (FIG. 4, gate capping layer 496, [0080]) and a second buffer layer (FIG. 4, gate buffer layer 492, [0080]), wherein the first buffer layer (FIG. 4, gate capping layer 496) is disposed on a side of a second gate electrode distal from a substrate (FIG. 4, depicting wherein the gate capping layer 496 is disposed on a side of the second gate electrode layer 494 away from the substrate 410), and the second buffer layer (FIG. 4, gate buffer layer 492) is disposed on a side of the gate electrode between the gate electrode and the substrate (FIG. 4, depicting wherein the gate buffer layer 492 is disposed on a side of the second gate electrode layer 494 between the second gate electrode layer 494 and the base substrate 410). Regarding the buffer layers, in [0038], Xie states: “The gate capping layer 126 may be used as a diffusion barrier layer to prevent diffusion of copper ions from the gate electrode layer 124.” Further, in [0038], Xie further states that the gate buffer layer 492 “may facilitate/provide adhesion between the gate electrode layer . . . and the underlying layer . . . .”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed thin film transistor of Liang having the second floating gate electrode 2092 of Liu by adding the gate capping layer 496 of Xie to the second floating gate electrode 2092 of Liu and by adding the gate buffer layer 492 of Xie, in order to prevent the diffusion of metal ions and facilitate adhesion between the gate electrode and underlying layers. See Xie [0038].
Moreover, the addition of the first and second buffer layers as disclosed in Xie in the thin film transistor of Liang and second gate electrode of Liu would result in the claimed configuration wherein the first buffer layer (FIG. 4, gate capping layer 496) is disposed on a side, distal from the oxygen supplementation layer, of the second gate electrode (Liang FIG. 5/Liu FIG. 4/Xie FIG. 4, the gate capping layer 496 of Xie may be disposed on the second floating gate electrode 2092 of Liu in the thin film transistor of Liang in the same manner in which the gate capping layer 496 of Xie is disposed on a side of the second gate electrode layer 494 of Xie, such that the gate capping layer 496 is disposed on a side of the second floating gate electrode 2092 distal from the protection pattern 8), and the second buffer layer (FIG. 4, gate buffer layer 492) is disposed between the second gate electrode and the oxygen supplementation layer (Liang FIG. 5/Liu FIG. 4/Xie FIG. 4, the gate buffer layer 492 may be disposed on the second floating gate electrode 2092 of Liu in the thin film transistor of Liang in the same manner in which the gate buffer layer 492 is disposed on a side of the second gate electrode 494, such that the gate buffer layer 492 is disposed on a side of the second floating electrode 2092 proximal to the protection pattern 8, and thus between the second floating electrode 2092 and the protective pattern 8).
Regarding claim 2, Liang in view of Liu and Xie further discloses wherein the orthogonal projection of the oxygen supplementation layer (FIG. 5, protective pattern 8) on the base substrate (FIG. 5, substrate 1) covers the orthogonal projection of the target portion (FIG. 5, active layer having space B) on the base substrate (FIG. 5, depicting wherein orthogonal projections of the protective pattern 8 and space B of the active layer 4 overlap, and the orthogonal projection of the pattern portion 8 covers the orthogonal projection of space B of the active layer 4).
Regarding claim 10, Liang in view of Liu and Xie further discloses wherein
a material of the active layer (FIG. 5, active layer 4) comprises at least one of: an indium-gallium-zinc oxide, an indium-gallium-zinc-tin oxide, an indium-tin oxide, an indium-zinc oxide, and an indium-tin-zinc oxide (FIG. 5, “In some embodiments, the material of the active layer 4 may include metal oxides, such as indium gallium zinc oxide.” Translation of CN111725242A at 5.); and
a material of the oxygen supplementation layer (FIG. 5, protective pattern 8) comprises at least one of: an indium- gallium-zinc oxide, an indium-gallium-zinc-tin oxide, an indium-tin oxide, an indium-zinc oxide, an indium-tin-zinc oxide, a molybdenum oxide, an aluminum oxide, a copper oxide, an indium oxide, a tin oxide, a zinc oxide, and a nickel oxide (FIG. 5, “Exemplarily, the material of the protection pattern 8 and the pixel electrode 9 may be a metal oxide conductive material, for example, Indium Tin Oxide (ITO for short).” Translation of CN111725242A at 6.).
Regarding claim 21, Liang in view of Liu and Xie further discloses wherein a sheet resistance of the oxygen supplementation layer (Liang FIG. 5, protective pattern 8, Translation of CN111725242A at 6: “Exemplarily, the material of the protection pattern 8 . . . may be a metal oxide conductive material, for example, Indium Tim Oxide (ITO for short).”) is greater than a sheet resistance of the first buffer layer and a sheet resistance of the second buffer layer (Xie FIG. 4, gate buffer layer 492, gate capping layer 496, [0037]: “Each of the gate buffer layer 122, the gate electrode layer 124, and the gate capping layer 126 may be made of same or different electrically conductive materials. Non-limiting examples of the electrically conductive materials may include: metal material and/or transparent conductive material. The metal material may include aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), palladium (Pd), platinum (Pt), chromium (Cr), neodymium (Nd), zinc (Zn), cobalt (Co), manganese (Mn), and any mixtures or alloys thereof. The transparent conductive material may include, for example, an indium tin oxide (ITO), an indium zinc oxide (IZO), and an aluminum doped zinc oxide (AZO).”), and both the sheet resistance of the first buffer layer and the sheet resistance of the second buffer layer are greater than a sheet resistance of the second gate electrode (Liu FIG. 4, second floating gate electrode 2092, [0055]: “And then covering a metal layer (not shown) on the metal oxide semiconductor, the material of the metal layer comprises but is not limited to aluminum, molybdenum, copper, silver and so on, through a mask process, optionally using a half-tone mask to carry on the pattern process to the metal oxide semiconductor layer and the metal layer, forming a first floating gate electrode 2091, a second floating gate electrode 2092 and a pixel electrode 210, the first floating gate electrode 2091 and the pixel electrode 210 are formed by the metal oxide semiconductor layer, both materials of which are the same, the second floating gate electrode 2092 is formed by the metal layer, between the first floating gate 2091 and the second floating gate electrode 2092 has an electrical effect, so that electrons can move between the two layers.”).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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