Prosecution Insights
Last updated: April 19, 2026
Application No. 17/909,146

DIE BONDING METHOD FOR MICRO-LED

Non-Final OA §103
Filed
Sep 02, 2022
Examiner
KIM, PAUL D
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Ledman Optoelectronic Co. Ltd.
OA Round
3 (Non-Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
3y 0m
To Grant
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
1346 granted / 1537 resolved
+17.6% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
52 currently pending
Career history
1589
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
35.2%
-4.8% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
30.9%
-9.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1537 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 4, 5, 7, 11, 13, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US PAT. 11,417,795) in view of Bucker (USPAT. 4,387,116), and further in view of Cheung et al. (US PAT. 10,186,549) and Wang et al. (TW 200708631 A). Yang teaches a process of die bonding for a micro-LED, comprising steps of: plating a tin (14, Fig. 2) at a die bonding position of a printed circuit board (PCB, 11) to obtain a tin-plated layer (col. 4, lines 27-28); adding a flux on the tin-plated layer (col. 4, lines 35-37) and a protective layer (16, col. 4, lines 39-40) on the tin-plated layer in sequence to obtain a pretreated PCB; and transferring a flip-chip micro-LED (17) to the pretreated PCB, reflowing and die bonding to complete die bonding of the micro-LED (col. 5, lines 25-27). However, Yang teaches to form the protective layer after the flux is formed, not prior to. Even though Yang teaches to form the protective layer after the flux is formed, at the time of the effective filing date of the claimed invention was made, it would have been an obvious matter of design choice to a person of ordinary skill in the art to modify the processes as recited in the claimed invention because the protective layer and the flux layer would have expected Applicant’s invention to perform equally well to enhance the bonding property between the PCB and the LED chip. Also, Applicant has not disclosed that the forming process of the protective layer and the flux layer in sequence to obtain a pretreated PCB as recited in the claimed invention provides an advantage, is used for a particular purpose, or solves a stated problem. Therefore, it would have been an obvious matter of design choice to modify the forming processes of the protective layer and the flux layer of Yang to obtain the invention as specified in claim 1. Alternately, Bucker teaches a process to form a protective layer (18, col. 2, lines 58-65) on a tin layer (12, col. 2, lines 9-10, Fig. 1) follow by applying a flux layer to form a layer (20, Fig. 3, col. 3, lines 7-15). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating the protective layer and the flux layer of Yang by forming the protective layer and the flux layer in sequence as taught by Bucker in order to provide enhancing the bonding property between the PCB and the LED chip. Further, Yang, modified by Bucker, silent a flip-chip micro-LED with tin. Cheung et al. teach a process of fabricating an electrical device including a process of providing a flip-chip micro-LED (36, 38, 40, Fig. 5) with tin (46, solder flux) in order to provide for enhancing a thermal bonding between the flip-chip micro-LED and a PCB (10, Fig. 6E). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify the flip-chip micro-LED of Yang, modified by Bucker, by providing a flip-chip micro-LED with tin as taught by Cheung et al. in order to provide for enhancing a thermal bonding between the flip-chip micro-LED and the PCB. In addition, Yang, modified by Bucker and Cheung et al., fails to teach to form the tin by an electroless tin plating. Wang et al. teach a process of forming an oxidation resistant layer on a surface including electroless plating for tin on a circuit board in order to provide a composite oxidation resistance layer on the surface of the circuit board (see abstract). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify the tin plating process of Yang, modified by Bucker and Cheung et al., by forming a tin plating layer by an electroless plating process as taught by Wang et al. in order to provide a composite oxidation resistance layer on the surface of the circuit board. Re. claims 2, 5, 13 and 15: Yang, modified by Bucker and Cheung et al., silent a thickness of the tin-plated layer and the flux layer. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). The applicant has not disclosed any criticality for the claimed limitations. Therefore, since such a modification would have been an obvious design consideration that is within the purview of one having ordinary skill in the art to provide the well-known benefit of obtaining a desirable electrical device. Re. claims 4 and 11: : Yang, modified by Bucker and Cheung et al. and Wang et al., silent a material of the flux. Since the flux material is provided for enhancing the bonding property between the micro-LED and the PCB, one of ordinary skill in the art could easily select materials from the recited lists to result in the required bonding property. Therefore, it would have been an obvious matter of design choice to modify the flux material of Yang, modified by Bucker and Cheung et al. and Wang et al., to obtain the invention as specified in claims 4 and 11. Re. claim 7 and 20: Bucker teaches that “layer thickness is controlled by regulating the amount of liquid applied to the surface and the spinning speed which controls the centrifugal liquid spreading force” (col. 2, lines 22-25) and Yang teaches that “…a die-bonding position of the wafer does not change significantly and the reflow process for the solder is completed in the case” (col. 5, lines 25-37). Since the reflowing process has been held that where the general conditions of a claim are disclosed in Yang, modified by Bucker and Cheung et al. and Wang et al., adjusting a reflow profile before the reflowing and the die bonding is within the purview of one having ordinary skill in the art to provide the well-known benefit of controlling the reflow process during the die bonding process. Claims 3, 9, 10, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Bucker and Cheung et al. and Wang et al., as applied to claim 1 above, and further in view of Ishida et al. (PGPub 2018/0158794 A1). Yang, modified by Bucker and Cheung et al. and Wang et al., teaches all limitations as set forth above, but silent an organic solderability preservative (OSP) process to form the protective layer. Ishida et al. teach a process of fabricating an electrical device including a process of forming a protecting layer (an organic corrosion inhibitor) to protect a layer (paragraph [0042]). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating the protective layer of Yang, modified by Bucker and Cheung et al. and Wang et al., by providing an organic solderability preservative (OSP) process as taught by Ishida et al. in order to provide a protection from the corrosion to a desired layer. Re. claim 12: Yang, modified by Bucker and Cheung et al. and Wang et al., silent a material of the flux. Since the flux material is provided for enhancing the bonding property between the micro-LED and the PCB, one of ordinary skill in the art could easily select materials from the recited lists to result in the required bonding property. Therefore, it would have been an obvious matter of design choice to modify the flux material of Yang, modified by Bucker and Cheung et al. and Wang et al., to obtain the invention as specified in claim 12. Re. claim 14: Yang, modified by Bucker and Cheung et al. and Wang et al., silent a thickness of the tin-plated layer and the flux layer. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). The applicant has not disclosed any criticality for the claimed limitations. Therefore, since such a modification would have been an obvious design consideration that is within the purview of one having ordinary skill in the art to provide the well-known benefit of obtaining a desirable electrical device. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Bucker and Cheung et al. and Wang et al., as applied to claim 1, and further in view of Ishibashi (PGPub 2015/0040419 A1). Yang, modified by Bucker and Cheung et al. and Wang et al., teaches all limitations including a thickness of tin-plated layer and the flux layer as set forth above (see also claims 2 and 5), but silent a nitrogen to correct a negative pressure. Ishibashi teaches an apparatus including “a gas ejector (26, Fig. 13) can easily adjust a negative pressure by regulating the flow rate of the gas (for example, nitrogen gas or dry air) flowing into the gas ejector 26, a fine adjustment of the negative pressure can be performed” (paragraph [0081]). Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify the die bonding process of Yang, modified by Bucker and Cheung et al. and Wang et al., by adjusting a negative pressure by a nitrogen gas as taught by Ishibashi in order to provide a fine adjustment of the negative pressure. Response to Arguments Applicant’s arguments with respect to claims 1-5, 7-15 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aneeta Yodichkas can be reached on 571-272-9773. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL D KIM/Primary Examiner, Art Unit 3729
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Prosecution Timeline

Sep 02, 2022
Application Filed
Mar 20, 2025
Non-Final Rejection — §103
Jun 20, 2025
Response Filed
Aug 27, 2025
Final Rejection — §103
Nov 25, 2025
Request for Continued Examination
Nov 26, 2025
Response after Non-Final Action
Jan 05, 2026
Non-Final Rejection — §103
Apr 07, 2026
Response Filed

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+6.6%)
3y 0m
Median Time to Grant
High
PTA Risk
Based on 1537 resolved cases by this examiner. Grant probability derived from career allow rate.

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