DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on October 14, 2025 in response to the previous Office Action (07/14/2025) is acknowledged and has been entered.
Claims 1 – 19 are currently pending.
Claims 12 – 15 are withdrawn.
Applicant’s amendment overcomes the following objections/rejections in the last Office Action:
Rejection under 112(b)
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 – 11, 16 – 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 17 recites the limitation "the third connection transistor", “the fourth connection transistor”, “the first connection transistor”, “the second transistor”, and “the first wire” in lines the last two limitations. There is insufficient antecedent basis for these limitations in the claim.
Claims 2 – 11, 16 and 18 – 19 rejected as being dependent on claims 1 and 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 2, 4, 6, 11, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma et al. (US 2022/0102403).
Regarding claim 1, Ma discloses a solid-state image capturing element comprising: a first pair of floating diffusion layers comprising: a first floating diffusion layer (subpixel w/ FD1) and a second floating diffusion layer (subpixel w/ FD3) arranged in a direction perpendicular to a predetermined direction (fig. 1); a second pair of floating diffusion layers comprising: a third floating diffusion layer (subpixel w/ FD2) and a fourth floating diffusion layer (subpixel w/ FD4) arranged in the perpendicular direction and adjacent to the first floating diffusion layer and the second floating diffusion layer pair of first floating diffusion layers in the predetermined direction (fig. 1); and an output circuit configured to output a signal according to an amount of charge of at least one of the first to fourth floating diffusion layers (out1/2/3/4) (fig. 1; ¶24-25): wherein the second floating diffusion layer and the fourth floating diffusion layer are flipped in the perpendicular direction relative to the first floating diffusion layer and the third floating diffusion layer (fig. 1), wherein the third floating diffusion layer and the fourth floating diffusion layer are flipped in the predetermined direction relative to the first floating diffusion layer and the second floating diffusion layer (fig. 1), wherein the third connection transistor (bin2) and the fourth connection transistor (bin4) are disposed adjacently to the first connection transistor (bin1) and the second connection transistor (bin3), and wherein the first wire (120) is disposed completely between a first column containing the first floating diffusion layer and the second floating diffusion layer and a second column containing the third floating diffusion layer and the fourth floating diffusion layer (fig. 1; ¶24).
Regarding claim 2, Ma et al. disclose the limitations of claim 1. Ma also teaches wherein the first connection transistor is configured to connect one of the first pair of floating diffusion layers to a first wire (120) according to a first control signal; and the second connection transistor is configured to connect another one of the first pair of floating diffusion layers to the first wire (120) according to a second control signal, and the third connection transistor is configured to connect one of the second pair of floating diffusion layers to the first wire according to a third control signal; and the fourth connection transistor is configured to connect another one of the second pair of floating diffusion layers to the first wire according to a fourth control signal (fig. 1; ¶24).
Regarding claim 4, Ma et al. disclose the limitations of claim 2. Ma also teaches wherein the first connection transistor and the third connection transistor are disposed adjacent to each other in the predetermined direction (fig. 1), and a selection transistor (RS) is disposed between the first connection transistor and the second connection transistor in the perpendicular direction (fig. 1).
Regarding claim 6, Ma et al. disclose the limitations of claim 2. Ma also teaches wherein the first connection transistor and the third connection transistor are disposed adjacent to each other in the predetermined direction, and the first connection transistor and the second connection transistor are disposed adjacent to each other in the perpendicular direction (fig. 8).
Regarding claim 11, Ma et al. disclose the limitations of claim 2. Ma also teaches further comprising: a pair of third floating diffusion layers arranged in the perpendicular direction; a pair of fourth floating diffusion layers arranged in the perpendicular direction and adjacent to the pair of third floating diffusion layers in the predetermined direction; a first connection circuit configured to select at least one of the pair of third floating diffusion layers and to connect the selected third floating diffusion layer to the first wire; and a second connection circuit configured to select at least one of the pair of fourth floating diffusion layers and to connect the selected fourth floating diffusion layer to the first wire. (fig. 1: multiples rows of shared FDs of two adjacent columns are connected with corresponding transistors via wires).
Claim 17 is rejected for the same reasons as claim 1. Ma also teaches the added limitation of an ADC (¶27, 32).
Regarding claim 18, Ma et al. disclose the limitations of claim 17. Ma also teaches wherein the first connection transistor is configured to connect one of the first pair of floating diffusion layers to a first wire (120) according to a first control signal; and the second connection transistor is configured to connect another one of the first pair of floating diffusion layers to the first wire (120) according to a second control signal, and the third connection transistor is configured to connect one of the second pair of floating diffusion layers to the first wire according to a third control signal; and the fourth connection transistor is configured to connect another one of the second pair of floating diffusion layers to the first wire according to a fourth control signal (fig. 1; ¶24).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, 4. 6, 11, 17 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Niwa et al. in view of Ma et al.
Regarding claim 1, Niwa discloses a solid-state image capturing element ( title) comprising: a first pair of floating diffusion layers comprising: a first floating diffusion layers and a second floating diffusion layer arranged in a direction perpendicular to a predetermined direction (fig. 8: floating diffusion of pixel groups 31-121-1 and 31-122-1 or groups 31-123-1 and 31-124-1); a first pair of floating diffusion layers comprising: a third floating diffusion layers and a fourth floating diffusion layer arranged in the perpendicular direction and adjacent to the pair of first floating diffusion layers in the predetermined direction ( fig. 8: floating diffusion of pixel groups 31-121-2 and 31-122-2 or groups 31-123-2 and 31-124-2); and an output circuit configured to output a signal according to an amount of charge of at least one of the first to fourth floating diffusion layers ( fig. 1: 12). Niwa fails to explicitly disclose wherein the second floating diffusion layer and the fourth floating diffusion layer are flipped in the perpendicular direction relative to the first floating diffusion layer and the third floating diffusion layer, wherein the third floating diffusion layer and the fourth floating diffusion layer are flipped in the predetermined direction relative to the first floating diffusion layer and the second floating diffusion layer, wherein the third connection transistor and the fourth connection transistor (bin4) are disposed adjacently to the first connection transistor and the second connection transistor, and wherein the first wire is disposed completely between a first column containing the first floating diffusion layer and the second floating diffusion layer and a second column containing the third floating diffusion layer and the fourth floating diffusion layer.
In a similar field of endeavor, Ma teaches a scalable pixel size image sensor with a configuration wherein the second floating diffusion layer and the fourth floating diffusion layer are flipped in the perpendicular direction relative to the first floating diffusion layer and the third floating diffusion layer (fig. 1), wherein the third floating diffusion layer and the fourth floating diffusion layer are flipped in the predetermined direction relative to the first floating diffusion layer and the second floating diffusion layer (fig. 1), wherein the third connection transistor (bin2) and the fourth connection transistor (bin4) are disposed adjacently to the first connection transistor (bin1) and the second connection transistor (bin3), and wherein the first wire (120) is disposed completely between a first column containing the first floating diffusion layer and the second floating diffusion layer and a second column containing the third floating diffusion layer and the fourth floating diffusion layer (fig. 1; ¶24). In light of the teaching of Ma, it would have been obvious to one of ordinary skill in the art before the effective filing date to use Ma’s configuration in Niwa’s system because an artisan of ordinarily skill would recognize that this would result in reducing pixel density and the conversion efficiency can be improved.
Regarding claim 2, Niwa et al. in view of Ma disclose the limitations of claim 1. Niwa also teaches wherein the first connection transistor is configured to connect one of the pair of first floating diffusion layers to the first wire according to a first control signal; and the second connection transistor is configured to connect another one of the pair of first floating diffusion layers to the first wire according to a second control signal, and the third connection transistor is configured to connect one of the pair of second floating diffusion layers to the first wire according to a third control signal; and the fourth connection transistor is configured to connect another one of the pair of second floating diffusion layers to the first wire according to a fourth control signal (fig. 8: 121-1-1, 121-2-1, 121-1-2, 121-2-2 all connect to wire 151-1).
Regarding claim 4, Niwa et al. in view of Ma et al. disclose the limitations of claim 2. Ma also teaches wherein the first connection transistor and the third connection transistor are disposed adjacent to each other in the predetermined direction (fig. 1), and a selection transistor (RS) is disposed between the first connection transistor and the second connection transistor in the perpendicular direction (fig. 1).
Regarding claim 6, Niwa et al. in view of Ma disclose the limitations of claim 2. Niwa also teaches wherein the first connection transistor and the third connection transistor are disposed adjacent to each other in the predetermined direction, and the first connection transistor and the second connection transistor are disposed adjacent to each other in the perpendicular direction (fig. 8).
Regarding claim 11, Niwa et al. in view of Ma disclose the limitations of claim 1. Niwa also teaches further comprising: a pair of third floating diffusion layers arranged in the perpendicular direction; a pair of fourth floating diffusion layers arranged in the perpendicular direction and adjacent to the pair of third floating diffusion layers in the predetermined direction; a first connection circuit configured to select at least one of the pair of third floating diffusion layers and to connect the selected third floating diffusion layer to the first wire; and a second connection circuit configured to select at least one of the pair of fourth floating diffusion layers and to connect the selected fourth floating diffusion layer to the first wire. (fig. 8: 3 rows of shared FDs of two adjacent columns are connected with corresponding transistors via wires 101-2-1, 101-2-2, 151-3, 151-5 to common wire 151-4).
Claim 17 is rejected for the same reasons as claim 1. Niwa also teaches the added limitation of an ADC (fig. 1; element 12).
Regarding claim 18, Niwa in view of Ma et al. disclose the limitations of claim 17. The combination also teaches wherein the first connection transistor is configured to connect one of the first pair of floating diffusion layers to a first wire (120) according to a first control signal; and the second connection transistor is configured to connect another one of the first pair of floating diffusion layers to the first wire (120) according to a second control signal, and the third connection transistor is configured to connect one of the second pair of floating diffusion layers to the first wire according to a third control signal; and the fourth connection transistor is configured to connect another one of the second pair of floating diffusion layers to the first wire according to a fourth control signal (Niwa fig. 8: transistor 121-1-1 connects FD of first group of pixels to wire 151-1 or transistor 121-4-1 connects FD of first group of pixels to wire 151-4…Ma fig. 1; ¶24).
Claim(s) 3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Niwa et al. in view of Ma in view of Japanese Patent Publication JP2013-197989A (Canon).
Regarding claim 3, Niwa et al. in view of Ma disclose the limitations of claim 2. Niwa fails to explicitly disclose wherein a reset transistor is disposed between the first connection transistor and the third connection transistor in the predetermined direction, and a selection transistor is disposed between the first connection transistor and the second connection transistor in the perpendicular direction.
In a similar field of endeavor, Canon teaches a solid-state imaging device including a plurality of photoelectric conversion elements that convert incident light into electrical signals wherein a reset transistor is between two transistors for binning to common wire (fig. 9; 204 between 206p and 206). In light of the teaching of Canon, it would have been obvious to one of ordinary skill in the art to use Canon’s teaching in Niwa’s system because an artisan of ordinarily skill would recognize that this would have yielded predictable results and resulted in an improved system capable of resetting the PD and allowing for effective image capture.
Regarding claim 5, Niwa et al. in view of Ma disclose the limitations of claim 2. Niwa also teaches the first connection transistor and the second connection transistor are disposed adjacent to each other in the perpendicular direction (fig. 8). Niwa fails to explicitly disclose wherein a reset transistor is disposed between the first connection transistor and the third connection transistor in the predetermined direction.
In a similar field of endeavor, Canon teaches a solid-state imaging device including a plurality of photoelectric conversion elements that convert incident light into electrical signals wherein a reset transistor is between two transistors for binning to common wire (fig. 9; 204 between 206p and 206). In light of the teaching of Canon, it would have been obvious to one of ordinary skill in the art to use Canon’s teaching in Niwa’s system because an artisan of ordinarily skill would recognize that this would have yielded predictable results and resulted in an improved system capable of resetting the PD and allowing for effective image capture.
Claim(s) 7 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Niwa et al. in view Ma in view of Korean Patent Publication KR 100790582B1 (PixelPlus).
Regarding claim 7, Niwa et al.in view of Ma disclose the limitations of claim 2. The combination fails to explicitly disclose further comprising: the second connection circuit further includes: a fifth connection transistor configured to connect one of the pair of second floating diffusion layers to a predetermined second wire according to a fifth control signal; and a sixth connection transistor configured to connect another one of the pair of second floating diffusion layers to a predetermined third wire according to a sixth control signal.
In a similar field of endeavor, PixelPlus teaches CMOS image sensor pixel is provided to improve low illumination characteristics wherein two transistors connect to two floating diffusions to two other wires (fig. 8: the center 4x4 pixel blocks sharing a common FD are all connected with four switches and wires to all adjacent blocks in all four directions). In light of the teaching of PixelPlus, it would have been obvious to one of ordinary skill in the art to use Canon’s teaching in Niwa’s system because an artisan of ordinarily skill would recognize that this would have yielded predictable results and resulted in an improved system allowing for effective image capture with improved low illumination characteristics.
Regarding claim 8, Niwa et al.in view of Ma in view of PixelPlus disclose the limitations of claim 7. The combination also teaches wherein a reset transistor is disposed adjacent to the fifth connection transistor in the predetermined direction (Niwa fig. 8).
Regarding claim 9, Niwa et al.in view of Ma in view of PixelPlus disclose the limitations of claim 7. The combination also teaches wherein a predetermined number of the fifth connection transistors are arranged adjacent to each other in the predetermined direction (Niwa fig. 8).
Allowable Subject Matter
Claims 10, 16 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTOINETTE T. SPINKS whose telephone number is (571)270-3749. The examiner can normally be reached M-Th 7am - 5pm EST.
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/ANTOINETTE T SPINKS/Primary Examiner, Art Unit 2639