DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Examiner notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The entire reference is considered to provide disclosure relating to the claimed invention. The claims & only the claims form the metes & bounds of the invention. Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. Unclaimed limitations appearing in the specification are not read into the claim. Prior art was referenced using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning. Examiner's Notes are provided with the cited references to assist the applicant to better understand how the examiner interprets the applied prior art. Such comments are entirely consistent with the intent & spirit of compact prosecution.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 10, 13-18, 20, and 33 are rejected under 35 U.S.C. 102 as being anticipated by Petunin et al., US 2005/0114821A1 (Petunin).
Claim 1
Petunin teaches An analogue circuit design apparatus, the apparatus comprising: a primary design unit and a plurality of secondary design units; (Petunin 0027) “The server also assigns a new pin pair to the client which found the newly-applied route. If the edit request fails the DRC, the server does not update the PCB master design. Instead, the server instructs the client sending the request to retry routing the previously-assigned pin pair, or to route another pin pair. Further aspects and additional embodiments of the invention are described below.” (0035) “Server 22 places the update message in the update queue for each client.” {Examiners note: Server corresponds to primary design unit, the multiple clients correspond to the plurality of secondary design units.}
wherein the primary design unit is configured to: obtain information representing technical requirements for the analogue circuit; ( Petunin 0045) “At block 201, the server receives the electrical design for the circuit to be placed onto a printed circuit board. This electrical design includes a netlist indicating all pin pairs which are to be connected, as well as the placement of components on the PCB.” {Examiners note: “Technical criteria” is being view as routing constraints/design rules.}
identify, based on the received information, a plurality of circuit portions for forming the analogue circuit; (Petunin 0045) “At block 201, the server receives the electrical design for the circuit to be placed onto a printed circuit board. This electrical design includes a netlist indicating all pin pairs which are to be connected, as well as the placement of components on the PCB.”
determine for each circuit portion of the plurality of circuit portions respective technical criteria for that circuit portion; (Petunin 0045) “At block 207, the server begins pass 0. During this pass, the server will require clients to route connections between pins without using vias. Initially, the server selects a pin pair by simply taking the first pin pair on the netlist. After the first pin pair is assigned, the server selects subsequent pin pairs based on distance and overlap with previously-assigned pin pairs.” {Examiners note: Per portion criteria include allowable vias; the servers pass based constraints define technical criteria applied to each portion.}
and provide the respective technical criteria for each circuit portion to at least one of a plurality of secondary design units; (Petunin 0045) “After the first pin pair is assigned, overlap with previously-assigned pin pairs as well as based upon whether a pin pair can be connected using the current via constraint the server selects subsequent pin pairs based on distance. At block 211, the server assigns the selected pin pair to the client, and the assigned pin pair with any updates in that client's update queue.” {Examiners note: “Circuit portion” is being treated as a connectivity portion (pin-pair connection/conductive path) within a circuit design.}
and wherein each of the plurality of secondary design units of the analogue circuit design apparatus is configured to: design a respective circuit portion of the plurality of circuit portions based on the technical criteria for that respective circuit portion provided by the primary design unit; and output a resulting initial design of the respective circuit portion; (Petunin 0045) “At block 215, the server waits for a client to either submit an edit request containing a proposed route for that client's assigned pin pair ("edit"), or to indicated that the assigned pin pair cannot be connected ("error").” {Examiners note: The clients proposed route is an “initial design” of the portion (connection) that the client outputs to its server.}
wherein, after at least an initial design of a given circuit portion has been completed by at least another one of the secondary design units, at least one of the secondary design units is configured to adapt its output initial design based on a context of its corresponding circuit portion, the context comprising technical criteria generated based on the completed design of the given circuit portion completed by the at least another one of the secondary design units; (Petunin 0035) “When server 2 forwards a new pin pair assignment to client 7, server 2 also forwards an update instructing client 7 to now include the proposed 23"-23 route in the client 7 copy of design In this manner, client 7 is able to take that newly-included route into consideration during its new routing task. If server 2 had rejected the proposed 23a-23b route, and if updates had been generated between the time of the initial assignment of pin pair 23a-23b to client 7 and the time of reporting the rejection, server 2 would send those interim updates to client 7 with a message advising that the proposed 23a-23b route was rejected, and instructing client 7 to try again. For example, client 5 or client 6 may have completed its routing task before client 7, and generated a route conflicting with the route proposed by client 7.” {Examiners note: The “context” is the updated design state incorporating the other clients completed routes; the secondary adapts (reroutes) when its initial proposal conflicts with that context. Context is ”generated based on” the completed routes of another client (e.g. the incorporated 25a-25b route causes a violation)}
the primary design unit is further configured to: receive a respective design for each circuit portion from at least one of a plurality of secondary design units; (Petunin 0037) “client 7 has forwarded an update request for a proposed 24a-24b connection route.” {Examiners note: The server receives each portion design proposal (edit request) from clients and accepts/ incorporates it or rejects it.}
and generate at least an initial design for the analogue circuit, based on the received designs. (Petunin 0036) “At this point, server 2 has incorporated into design 3 routes for pin pairs” {Examiners note: The servers assembled design (design 3 with incorporated routes) is the overall circuits initial design (for interconnect).}
Claim 2
Petunin teaches The analogue circuit design apparatus of claim 1 wherein each secondary design unit is configured to repeat the step of adapting the design of its corresponding circuit portion in the event that the modification of the design of another circuit portion of the plurality of circuit portions causes a change of context for the secondary design unit's corresponding circuit portion. (Petunin 0008) “The routes are incorporated into a master PCB design, and the steps of the method are repeated.” (0036) “client 7 has routed pin pair 24a-24b without knowledge of the routes for pin pairs 25a-25b and 26a-26b that have been incorporated into design 3.” (0036) “When server 2 performs a DRC for the proposed route connecting pin pair 24a-24b, server 2 finds a rule violation. . . Accordingly, server 2 rejects the proposed route for connecting pins 24a-24b . Server 2 then sends a rejection message to client 7, together with the updates in the update queue of client 7 (FIG. 11). Subsequently, client 7 finds a new route” {Examiners note: The context changes when other clients routes are incorporated (modified/added) into the master design, this is a direct analog to “modification of another circuit portion . . causes a change of context.” The routing/design steps are repeated, when context changes the client adapts its design by generating a new route (repeat the adaptation step).}
Claim 3.
Petunin teaches The analogue circuit design apparatus of claim 2 wherein each secondary design unit is configured to repeat the step of adapting the design of its corresponding circuit portion only in the event that the change in context is greater than a selected threshold level of change in context. (Petunin 0037) “the proposed 24 -24 route is too close to the route for pins 25a -25b . In FIG. 10, the traces are shown as solid or dashed lines. The minimum clearance between traces is represented as a shaded region around each trace. If the shaded regions of two traces on the same side of the board overlap ( or on the same level for boards with more than two levels), the traces are too close.” {Examiners note: The selected threshold (minimum clearance) triggers rework when it causes overlap/too close condition.}
Claim 4.
Petunin teaches The analogue circuit design apparatus of claim 1 wherein each secondary design unit is configured to adapt the design of its corresponding circuit portion only after at least an initial design of their corresponding circuit portion has been completed by all of the secondary design units. (Petunin 0036) “Client 7 has routed pin pair 24"-246 without knowledge of the routes for pin pairs 25"-256 and 26"-266 that have been incorporated into design 3.” (0036) “When server 2 performs a DRC for the proposed route connecting pin pair 24a-24b, server 2 finds a rule violation. . . Accordingly, server 2 rejects the proposed route for connecting pins 24"-246 . Server 2 then sends a rejection message to client 7, together with the updates in the update queue of client 7 (FIG. 11). Subsequently, client 7 finds a new route” {Examiners note: While all completed designs don’t explicitly have to be completed by the secondary design unit (servers) first, there is a design sequence out of the possible design sequences here where all secondary design units have completed their design first.}
Claim 10.
The analogue circuit design apparatus of claim 1, wherein each secondary and/or tertiary design unit is configured to: verify whether or not its corresponding designed circuit portion meets its corresponding technical criteria, and when the designed respective circuit portion meets the technical criteria, output the generated design; and when the respective circuit portion does not meet the technical criteria, adapt the design of the respective circuit portion. ( Petunin 0004) “As edits to that design are made at the clients, those edits are transmitted to the server as requests to edit the design. After the server performs a design rule check (DRC) to confirm a requested edit will not conflict with another edit or otherwise violate a restriction imposed on the PCB design (e.g., minimum separation between traces, etc.), the server applies the requested edit to the design. The applied edit is then broadcast to the clients for update of the PCB design copies at those clients.” (0027) “If the route passes the DRC, the server applies the edit request to the master design to include the route. The server forwards an update to all clients to modify their PCB design copies to reflect the new route. If the edit request fails the DRC, the server does not update the PCB master design” {Examiners note: Contains a verification step against constraints (technical criteria) and if it passes verification outputs generated design. Failing verification generates an alternative route.}
Claim 13.
Petunin teaches The analogue circuit design apparatus of claim 1 wherein the primary and/or secondary design unit is configured to adjust the technical criteria for the corresponding circuit portion of the at least one of the secondary design units based on the context of the corresponding circuit portion of the at least one of the secondary design units; (Petunin 0035) “When server 2 forwards a new pin pair assignment to client 7, server 2 also forwards an update instructing client 7 to now include the proposed 23"-23 route in the client 7 copy of design In this manner, client 7 is able to take that newly-included route into consideration during its new routing task. (0036) “client 5 sent an edit request to server 2 proposing a route for connecting pin pair 25a -25b , and server 2 accepted that route.” {Examiners note: The servers update changes the constraints the client must obey is being viewed as “adjusting technical criteria based on context”}
and wherein the at least one of the secondary design units is configured to adapt the design of its corresponding circuit portion based on adjusted technical criteria for the corresponding circuit portion received from the parent. (Petunin 0035) “server 2 would send those interim updates to client 7 with a message advising that the proposed 23a-23b route was rejected, and instructing client 7 to try again.” (Petunin 0037) “the proposed 24 -24 route is too close to the route for pins 25a -25b . In FIG. 10, the traces are shown as solid or dashed lines. . . client 7 would then forward a subsequent edit request for the second route. (0036) “Thus, at the time client 7 finds a route for pin pair 24a -24b.” {Examiners note: Parents sends updates (adjusted criteria) child is instructed to “try again” Child adapts based on adjusted criteria.}
Claim 14.
Petunin teaches A method of designing an analogue circuit, the method comprising: at a primary design unit of an analogue circuit design apparatus: (Petunin 0027) “The server also assigns a new pin pair to the client which found the newly-applied route. If the edit request fails the DRC, the server does not update the PCB master design. Instead, the server instructs the client sending the request to retry routing the previously-assigned pin pair, or to route another pin pair. Further aspects and additional embodiments of the invention are described below.” (0035) “Server 22 places the update message in the update queue for each client.” {Examiners note: Server corresponds to primary design unit, the multiple clients correspond to the plurality of secondary design units.}
obtaining information representing technical requirements for the analogue circuit; ( Petunin 0045) “At block 201, the server receives the electrical design for the circuit to be placed onto a printed circuit board. This electrical design includes a netlist indicating all pin pairs which are to be connected, as well as the placement of components on the PCB.” {Examiners note: “Technical criteria” is being view as routing constraints/design rules. }
identifying, based on the received information, a plurality of circuit portions for forming the analogue circuit; ( Petunin 0045) “At block 201, the server receives the electrical design for the circuit to be placed onto a printed circuit board. This electrical design includes a netlist indicating all pin pairs which are to be connected, as well as the placement of components on the PCB.”
determining for each circuit portion of the plurality of circuit portions respective technical criteria for that circuit portion; ( Petunin 0045) “At block 207, the server begins pass 0. During this pass, the server will require clients to route connections between pins without using vias. Initially, the server selects a pin pair by simply taking the first pin pair on the netlist. After the first pin pair is assigned, the server selects subsequent pin pairs based on distance and overlap with previously-assigned pin pairs.” {Examiners note: Per portion criteria include allowable vias; the servers pass based constraints define technical criteria applied to each portion.}
providing the respective technical criteria for each circuit portion to at least one of a plurality of secondary design units; ( Petunin 0045) “After the first pin pair is assigned, overlap with previously-assigned pin pairs as well as based upon whether a pin pair can be connected using the current via constraint the server selects subsequent pin pairs based on distance. At block 211, the server assigns the selected pin pair to the client, and the assigned pin pair with any updates in that client's update queue.” {Examiners note: “Circuit portion” is being treated as a connectivity portion (pin-pair connection/conductive path) within a circuit design. }
at each of the plurality of secondary design units of the analogue circuit design apparatus: designing a respective circuit portion of the plurality of circuit portions based on the technical criteria for that respective circuit portion provided by the primary design unit; and output a resulting initial design of the respective circuit portion; (Petunin 0045) “At block 215, the server waits for a client to either submit an edit request containing a proposed route for that client's assigned pin pair ("edit"), or to indicated that the assigned pin pair cannot be connected ("error").” {Examiners note: The clients proposed route is an “initial design” of the portion (connection) that the client outputs to its server.}
wherein, after at least an initial design of a given circuit portion has been completed by at least another one of the secondary design units, the design of a further circuit portion, by a further secondary design unit, is adapted based on a context of that further circuit portion, the context comprising technical criteria generated based on the completed design of the given circuit portion; and Petunin 0035) “When server 2 forwards a new pin pair assignment to client 7, server 2 also forwards an update instructing client 7 to now include the proposed 23"-23 route in the client 7 copy of design In this manner, client 7 is able to take that newly-included route into consideration during its new routing task. If server 2 had rejected the proposed 23a-23b route, and if updates had been generated between the time of the initial assignment of pin pair 23a-23b to client 7 and the time of reporting the rejection, server 2 would send those interim updates to client 7 with a message advising that the proposed 23a-23b route was rejected, and instructing client 7 to try again. For example, client 5 or client 6 may have completed its routing task before client 7, and generated a route conflicting with the route proposed by client 7.” {Examiners note: The “context” is the updated design state incorporating the other clients completed routes; the secondary adapts (reroutes) when its initial proposal conflicts with that context. Context is ”generated based on” the completed routes of another client (e.g. the incorporated 25a-25b route causes a violation)}
at the primary design unit is further configured to: receiving a respective design for each circuit portion from at least one of a plurality of secondary design units; (Petunin 0037) “client 7 has forwarded an update request for a proposed 24a-24b connection route.” {Examiners note: The server receives each portion design proposal (edit request) from clients and accepts/ incorporates it or rejects it.}
generating at least an initial design for the analogue circuit, based on the received designs. (Petunin 0036) “At this point, server 2 has incorporated into design 3 routes for pin pairs” {Examiners note: The servers assembled design (design 3 with incorporated routes) is the overall circuits initial design (for interconnect).}
Claim 15.
Petunin teaches The method of claim 14 further comprising: adapting the initial design of the given circuit portion based on the context of the given circuit portion, the context comprising technical criteria generated based on the adapted design of the further circuit portion. (Petunin 0037) “Accordingly, server 2 rejects the proposed route for connecting pins 24a-24b. . . Subsequently, client 7 finds a new route. . . client 7 would then forward a subsequent edit request for the second route.”
Claim 16.
Petunin teaches The method of claim 14 further comprising repeating the step of adapting the design of a further circuit portion in the event that the modification of the design of another circuit portion of the plurality of circuit portions causes a change of context for that further circuit portion, (Petunin 0008) “The routes are incorporated into a master PCB design, and the steps of the method are repeated.” (0036) “client 7 has routed pin pair 24a-24b without knowledge of the routes for pin pairs 25a-25b and 26a-26b that have been incorporated into design 3.”
wherein repeating the step of adapting the design of a further circuit portion occurs only in the event that the change in context is greater than a selected threshold level of change in context. (Petunin 0035) “server 2 would send those interim updates to client 7 with a message advising that the proposed 23a-23b route was rejected, and instructing client 7 to try again.” (Petunin 0037) “the proposed 24 -24 route is too close to the route for pins 25a -256 . In FIG. 10, the traces are shown as solid or dashed lines. The minimum clearance between traces is represented as a shaded region around each trace. If the shaded regions of two traces on the same side of the board overlap ( or on the same level for boards with more than two levels), the traces are too close.”
Claim 18.
Petunin teaches The method of claim 14 further comprising adapting the design of the circuit portions output from each of the plurality of secondary design units based on their respective contexts after at least an initial design of their corresponding circuit portion has been completed by each corresponding secondary design unit. (Petunin 0036) “Client 7 has routed pin pair 24"-246 without knowledge of the routes for pin pairs 25"-256 and 26"-266 that have been incorporated into design 3.” (0036) “When server 2 performs a DRC for the proposed route connecting pin pair 24a-24b, server 2 finds a rule violation. . . Accordingly, server 2 rejects the proposed route for connecting pins 24"-246 . Server 2 then sends a rejection message to client 7, together with the updates in the update queue of client 7 (FIG. 11). Subsequently, client 7 finds a new route” {Examiners note: While all completed designs don’t explicitly have to be completed by the secondary design unit (servers) first, there is a design sequence out of the possible design sequences here where all secondary design units have completed their design first.}
Claim 20.
Petunin teaches The method of claim 14 wherein the respective technical criteria for each circuit portion is at least one of: (i) provided to all of the secondary design units in parallel, (ii) sent from the primary design unit to the at least one of the secondary design units, and then from the at least one of the secondary design units to the further secondary design unit. (Petunin 0027) “If the route passes the DRC, the server applies the edit request to the master design to include the route. The server forwards an update to all clients.” {Examiners note: Under BRI The update is sent to all clients is distributing current design state in parallel. Under BRI, Information originating from one client is disseminated to other clients via the server as an indirect relay.}
Claim 33.
Petunin teaches A computer readable non-transitory storage medium comprising a program for a computer to cause a processor to perform the method of claim 14. (Petunin 0008) “A second embodiment includes a machine-readable medium containing instructions for performing a method of the first embodiment.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 6, 8, 9, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Petunin et al., US 2005/0114821A1 (Petunin) in view of Werblun et al., Closing the Analog Design Loop with the Berkeley Analog Generator (Werblun)
Claim 5.
Petunin does not explicitly teach, but Werblun teaches The analogue circuit design apparatus of claim 1 wherein the primary design unit is configured to obtain the context of a secondary design unit's corresponding circuit portion by simulating the performance of the given circuit portion completed by the at least another one of the secondary design units. (Werblun Pg. 38 Section 4.3) “Since we know the pole location of the TIA after simulation, we can design the CTLE to have its zero in close proximity.” (Pg. 1 Paragraph 2) “Additionally, BAG allows the automation of simulation and post-processing of simulation data as well as implementation of higher-level design scripts that encapsulate designer insights and methodology, as well as opens the doors for automated optimizer-driven circuit design” (Pg. 24 Paragraph 1) “and runs an AC simulation and noise simulation. The corresponding measurement manager sifts through the data and (regardless of the transfer function shape) computes the DC gain and overall bandwidth.” {Examiners note: Top level controller (primary design unit) simulating a circuit portion (TIA), extracting performance characteristic (pole location) using the context criterion to design a different portion (CTLE). Under BRI the extracted pole location are “technical criteria generated based on the completed design” of the other portion. While a secondary design unit is not explicitly taught, under BRI, the “generator/flow for a block” is being viewed as a secondary design unit.}
are analogous to the claimed invention because they are from the same field of endeavor of
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify the primary and secondary design units of Petunin with the simulation of a secondary design unit of Werblun to “allows the automation of simulation and post-processing of simulation data as well as implementation of higher-level design scripts as Werblun (abstract) suggests.
Claim 6.
Modified Petunin with Werblun teaches The analogue circuit design apparatus of claim 1 wherein each secondary design unit is configured to obtain the context of its corresponding circuit portion by simulating the performance of the given circuit portion completed by the at least another one of the secondary design units. (Werblun Pg. 38 Section 4.3) “Since we know the pole location of the TIA after simulation, we can design the CTLE to have its zero in close proximity.” (Pg. 37 2nd paragraph) “Plugging into equation 4.8 gives a starting point that can then be swept using BAG for better accuracy. . . This is also determined by simulating BAG generated instances.” (Pg. 1 Paragraph 2) “Additionally, BAG allows the automation of simulation and post-processing of simulation data as well as implementation of higher-level design scripts that encapsulate designer insights and methodology, as well as opens the doors for automated optimizer-driven circuit design” {Examiners note: Actively generated circuit instances and uses results to set/adjust design choices. (Obtaining context. . . by simulating performance.” While a secondary design unit is not explicitly taught, under BRI, the “generator/flow for a block” is being viewed as a secondary design unit.}
Claim 8.
Modified Petunin with Werblun teaches The analogue circuit design apparatus of claim 1 wherein the analogue circuit design apparatus further comprises a plurality of tertiary design units; (Werblun Abstract) “Designers who have decided on a certain topology can write a layout and schematic generator script in a high level programming language with class based hierarchy once, and then any changes in the circuit simply require changing the corresponding parameters file containing the circuit specifications. {Examiners note: “Class based hierarchy” is explicit evidence of multi-level generator decomposition (i.e. higher level generator classes utilizing lower level classes. This as being view as tertiary design units.}
and wherein at least one of the plurality of primary and/or secondary design units is further configured to design a respective circuit sub-portion of at least one of the plurality of circuit portions based on the technical criteria for that respective circuit portion provided by the primary design unit by: identifying, based on the received technical criteria, a plurality of circuit sub- portions for forming the analogue circuit; (Werblun Pg. 20 Section 2.3) “Schematic generators control the process of copying the template schematic mentioned previously and assigning values to the components based on the inputted spec file [3]. These generators have the capability of arraying and deleting instances, removing, adding or re- naming pins and other simple operations.” (Pg. 20 Listing 2.8) “# Copy the unit cell many times with many names.” {Examiners note: Under BRI, Generators operating on template schematics and instance (sub elements) correspond to “circuit sub portions” The generator generates repeated sub circuits or sub block instances (copied unit cell).}
determining for each circuit sub-portion of the plurality of circuit sub-portions respective technical sub-criteria for that circuit sub-portion; and providing the respective technical sub-criteria for each circuit sub-portion to at least one of a plurality of tertiary design units; and each of the plurality of tertiary design units of the analogue circuit design apparatus is configured to: design a respective circuit sub-portion based on the technical sub-criteria for that respective circuit sub-portion provided by the secondary design unit; (Werblun Pg. 20 Listing 2.8) “#Loop through all instances and use the design method to input the params from the spec file into the schematic.” {Examiners note: Per instance parameter sets coming from “spec file” and then applied to each instance. Per subportion (per instance) criteria existing as a parameter sets.}
and output a resulting design of the respective circuit sub-portion. (Werblun Pg. 20 Section 2.3) “Schematic generators control the process of copying the template schematic mentioned previously and assigning values to the components based on the inputted spec file [3]. {Examiners note: Generating schematic/layout artifacts (resulting design).}
Claim 9.
Modified Petunin with Werblun teaches The analogue circuit design apparatus of claim 8 wherein, after at least an initial design of a given circuit sub-portion has been completed by at least another one of the tertiary design units, at least one of the tertiary design units is configured to adapt its initial output design based on a context of its circuit sub-portion, the context comprising technical sub- criteria generated based on the completed design of the given circuit sub-portion completed by the at least another one of the tertiary design units. (Werblun Pg. 38 Section 4.3) “Since we know the pole location of the TIA after simulation, we can design the CTLE to have its zero in close proximity.” {Examiners note: “After simulating shows the TIA design exists (has been generated) and is functionally complete enough to be evaluated. Under BRI TIA the “given circuit sub portion” completed by another (tertiary) block generator flow. The CTLE design is being set/adjusted which is being viewed as “adapt its initial output design” TIA pole location is being viewed as “technical criterion”}
Claim 11.
Modified Petunin with Werblun teaches The analogue circuit design apparatus of claim 1 wherein each secondary design unit is configured to: simulate an analogue circuit based on the corresponding designed respective circuit portion design to produce at least one simulation output; (Werblun Pg. 5 paragraph 2) “The test bench script maps the pins of the instance to the pins of the test harness and runs predetermined SPICE simulations (i.e. AC, transient, S-parameters) before exporting the results to Python.” {Examiners note: Simulation of (portion level) design using SPICE producing simulation results. }
verify whether or not the circuit portion meets its corresponding technical criteria, and when the simulated performance of the respective circuit portion meets the technical criteria, output the generated design; (Werblun Pg. 22 2nd paragraph) “These outputs are sent to the measurement manager where the user can, for example, compute 3dB frequencies, DC gain, etc. and save the results if desired. Multiple test benches can be run in one instance.” {Examiners note: Computing metrics (gain/bandwidth) from simulation outputs is the verification step used to assess against criteria specs (criteria stored in spec file).}
and when the simulated performance of the respective circuit portion does not meet the technical criteria, adapt the design of the respective circuit portion based on a difference between the simulated performance and the technical criteria. (Werblun Pg. 37 3rd paragraph) “Plugging into equation 4.8 gives a starting point that can then be swept using BAG for better accuracy. . . This is also determined by simulating BAG generated instances.” {Examiners note: Simulate instances, observe performance then adjust design variables to better match the desired targets (reduce gap between performance and criteria.}
Claim 12.
Modified Petunin with Werblun teaches The analogue circuit design apparatus of claim 1 wherein the primary design unit is configured to: simulate an analogue circuit based on the generated initial design to produce at least one simulation output; (Werblun Pg. 5 paragraph 2) “The test bench script maps the pins of the instance to the pins of the test harness and runs predetermined SPICE simulations (i.e. AC, transient, S-parameters) before exporting the results to Python.” {Examiners note: Simulation of (portion level) design using SPICE producing simulation results. }
verify whether or not the analogue circuit meets the technical requirements for the analogue circuit, and when the analogue circuit meets the technical requirements, output the generated design; (Werblun Pg. 5 2nd paragraph) “Design manager is a class responsible for using the top level generator mentioned previously and overseeing the process of running tests and post-processing on test results.” {Examiners note: Verification is taught as running tests and analyzing results (post processing). It is implicit that when the requirements are met the result is passed along.}
and when the analogue circuit does not meet the technical requirements: determine, for at least one affected circuit portion of the plurality circuit portions, revised technical criteria for that affected circuit portion based on the simulation output and the technical requirements; (Werblun Pg. 2 1st paragraph) “If the circuit fails at any of these steps, the design must be modified and the steps repeated.”
provide, to at least one corresponding secondary design unit, the revised technical criteria for each affected circuit portion; (Petunin col 6 0045) “At block 211, the server assigns the selected pin pair to the client, and forwards the assigned pin pair with any updates in that client's update queue” (0035) “Server 22 places the update message in the update queue for each client.”
receive a respective updated design of each affected circuit portion from the at least one corresponding secondary design unit; (Petunin 0045) “the server waits for a client to either submit an edit request containing a proposed route for that client's assigned pin pair ("edit"), or to indicated that the assigned pin pair cannot be connected ("error").”
update the set of designs with the respective updated design of each affected circuit portion; (Petunin 0036) “server 2 has incorporated into design 3 routes for pin pairs”
and repeat the steps of simulating, verifying, and outputting for the updated set of designs. (Petunin 0008) “The routes are incorporated into a master PCB design, and the steps of the method are repeated.”
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Petunin et al., US 2005/0114821A1 (Petunin) in view of Chang et al., US 6,567,957 B1 (Chang).
Claim 7.
Petunin does not explicitly teach, but Chang teaches The analogue circuit design apparatus of claim 1 wherein at least one of the plurality of design units is configured to design a respective circuit portion of the plurality of circuit portions based on the technical criteria for that respective circuit portion provided by the primary design unit by performing a lookup in a database of designed circuits and/or circuit portions for circuit portions that fulfil the technical criteria. (Chang Abstract) “A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system” (Col 1 Lines 60-67) “as Block 60 Based Design ("BED"), in which a system is designed by integrating a plurality of existing component design blocks These pre-designed blocks may be obtained from internal design teams or licensed from other design companies.” (col 5 Lines 56-58) “upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA);” {Examiners note: “Selecting” pre-designed circuit blocks necessarily implies retrieving/choosing blocks from an available collection(database) The selected block (IP block) corresponds to “circuit portion”. }
are analogous to the claimed invention because they are from the same field of endeavor of
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify the primary and secondary design units of Petunin with the database lookup method of Chang to minimize delays and risk brought about uncertainty in determining system design feasibility as Chang suggests. (Col 1 Lines 66-67)
Claim 19.
Modified Petunin with Chang teaches The method of claim 14 wherein the design of a further circuit portion is adapted only once all the other portions of the circuit have been designed by the plurality of secondary design units based on their corresponding technical criteria. (Chang col 9 Lines 38-41) “Chip assembly design stage 108 does not begin until all circuit blocks are designed, modified, and integrated into the chip plan” {Examiners note: Under BRI, circuit blocks are “circuit potions” adaptation is not made “only after all blocks are designed”.}
Conclusion
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/JOHN DAVID HAGLER/ Examiner, Art Unit 2189
/REHANA PERVEEN/ Supervisory Patent Examiner, Art Unit 2189