Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “design unit configured to” in claim 1, “primary design unit and a plurality of secondary design units” in claim 2, “analogue circuit design unit is configured to” in claim 3, “secondary design units” and “primary design unit” in claim 12, and “primary design unit … secondary design units” in claim 14.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 and 25 are rejected under 35 U.S.C 101 because the claimed invention is directed to a judicial exception without significantly more.
Claim 1.
STEP 1: Yes. The claim recites a “apparatus” which is a manufacture.
STEP 2A PRONG ONE:
This claim recites mental processes.
identify, based on the received information, a plurality of circuit portions for forming the analogue circuit;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case a judgement of the circuit portions.
determine, for each circuit portion of the plurality circuit portions, respective technical criteria for that circuit portion;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case an observation of the respective technical criteria.
produce a set of designs comprising a respective design for each circuit portion;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case an evaluation to create a set of designs.
adapt the design of at least one circuit portion based on the obtained information relating to parasitics; and
This is a mental process of judgement to adapt the design.
STEP 2A PRONG TWO: The claim does not integrate the exception into a practical application.
STEP 2B: The claim does not recite an inventive concept or significantly more than the exception itself.
receive information representing technical requirements for the analogue circuit;
MPEP 2106.05(g) – This is pre solution data gathering.
for at least one circuit portion of the plurality of circuit portions obtain information relating to parasitics that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion;
MPEP 2106.05(g) – This is pre solution data gathering.
output a complete circuit design including at least one circuit portion adapted based on obtained information relating to parasitics.
MPEP 2106.05(g) – This is post-solution data output.
Conclusion: Claim 1 is directed to mental processes, not integrated into a practical application and lacks an inventive concept. Therefore, it is ineligible under 35 U.S.C 101.
Regarding Claims 2, 3, 5, 6, 7, 10, and 11:
These claims merely add additional limitations which recite mental abstractions of judgment, decomposition, threshold evaluation, and design decisions. They also provided more detail of the data gathering. MPEP 2106.05(g). This does not integrate the judicial exception into a practical application. The claims do not resolve the issues from the claims they depend upon.
Regarding Claims 4 and 8:
These claims merely add additional limitations which recite mathematical abstractions of simulation or machine learning which fall under the math grouping. This does not integrate the judicial exception into a practical application. The claims do not resolve the issues from the claims they depend upon.
Regarding Claim 9:
This claim merely adds additional detail to included parameters. This does not integrate the judicial exception into a practical application. The claim does not resolve the issues from the claims they depend upon.
Claim 12.
STEP 1: Yes. The claim recites a “method” which is a process.
STEP 2A PRONG ONE:
This claim recites mental processes and mathematical concepts.
a) designing a respective circuit portion of the plurality of circuit portions based on technical criteria provided by the primary design unit; and
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case an observation of the respective technical criteria.
d) generating at least an initial design for the analogue circuit based on the set of designs;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case a judgment to create a design for the analogue circuit.
generated design by mathematically simulating the performance of the generated design using a virtual test bench
This is a mathematical calculation of simulation.
repeating the steps a) to e) a plurality of times, wherein each time the steps a) to e) are repeated, new technical criteria are provided by the primary design unit.
Repeating would correspond to the stated analysis for each step a) to e).
STEP 2A PRONG TWO: The claim does not integrate the exception into a practical application.
STEP 2B: The claim does not recite an inventive concept or significantly more than the exception itself.
b) outputting a resulting design of the respective circuit portion; and at a primary design unit of an analogue circuit design apparatus:
MPEP 2106.05(g) – This is post-solution data output.
c) obtaining a set of designs comprising a respective design for each circuit portion from at least one of the plurality of secondary design units;
MPEP 2106.05(g) – This is pre-solution data gathering.
e) obtaining information relating to parasitics experienced by at least one of the circuit portions and that generated design by mathematically simulating the performance of the generated design using a virtual test bench; and
MPEP 2106.05(g) – This is pre-solution data gathering.
Conclusion: Claim 12 is directed to mental processes and mathematical abstractions, not integrated into a practical application and lacks an inventive concept. Therefore, it is ineligible under 35 U.S.C 101.
Claim 13.
STEP 1: Yes. The claim recites a “method” which is a process.
STEP 2A PRONG ONE:
This claim recites mental processes.
identifying, based on the received information, a plurality of circuit portions for forming the analogue circuit;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case a judgement of the circuit portions.
determining, for each circuit portion of the plurality circuit portions, respective technical criteria for that circuit portion;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case an observation of the respective technical criteria.
producing a set of designs comprising a respective design for each circuit portion;
This describes an observation, evaluation, judgement, or opinion that could be done in the mind or with the aid of pen and paper. In this case an evaluation to create a set of designs.
adapting the design of at least one circuit portion based on the obtained information relating to parasitics; and
This is a mental process of judgement to adapt the design.
STEP 2A PRONG TWO: The claim does not integrate the exception into a practical application.
STEP 2B: The claim does not recite an inventive concept or significantly more than the exception itself.
receiving information representing technical requirements for the analogue circuit;
MPEP 2106.05(g) – This is pre solution data gathering.
for at least one circuit portion of the plurality of circuit portions obtain information relating to parasitics that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion;
MPEP 2106.05(g) – This is pre solution data gathering.
outputting a complete circuit design including at least one circuit portion adapted based on obtained information relating to parasitics.
MPEP 2106.05(g) – This is post-solution data output.
Conclusion: Claim 13 is directed to mental processes, not integrated into a practical application and lacks an inventive concept. Therefore, it is ineligible under 35 U.S.C 101.
Regarding Claims 14, 15, 17, 18, and 19:
These claims merely add additional limitations which recite mental abstractions of judgment, decomposition, threshold evaluation, and design decisions. They also provided more detail of the data gathering. MPEP 2106.05(g). This does not integrate the judicial exception into a practical application. The claims do not resolve the issues from the claims they depend upon.
Regarding Claim 16:
This claim merely adds additional limitations which recite mathematical abstractions of simulation or machine learning which fall under the math grouping. This does not integrate the judicial exception into a practical application. The claims do not resolve the issues from the claims they depend upon.
Regarding Claim 25:
This claim merely adds “A computer readable non-transitory storage medium” and “processor” to claim 13. These are generic computer components. This does not integrate the judicial exception into a practical application. The claims do not resolve the issues from the claims they depend upon. Therefore, this claim is rejected for the stated reasons and the same reasons as claim 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 10, 13, 16, and 25 are rejected under 35 U.S.C 102 as being unpatentable over LOURENCO et al. “AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation” (2016) [herein “LOURENCO”].
Regarding Claim 1, LOURENCO teaches
An analogue circuit design apparatus, the apparatus comprising at least one design unit configured to:
“This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology.”. (Abstract).
“In this section, the results obtained using the proposed methodology, which was implemented in Java™, and executed on an Intel I7-2640M CPU with 8GB RAM, are shown.”. (Pg. 326).
AIDA is a circuit design apparatus made of design units for optimization ran on CPU with memory.
receive information representing technical requirements for the analogue circuit;
“AIDA inputs circuit-level standard Spice-like netlists for both circuit and testbench(es) descriptions, which are easily exported from most commercial IC design suites.”. (Section 3.3 Pg. 320).
This shows taking in netlist inputs among other descriptions to represent the circuit.
identify, based on the received information, a plurality of circuit portions for forming the analogue circuit;
“4.1.3. Layout guidelines The layout guidelines, which are also described in XML, provide an abstract floorplan view and are parameterized to include the design variables. This high level floorplan is defined using simple rectangular constructs that capture the proximity and topological relations that the designer wishes to impose. The information used for placement is the type and relative placement of the cells, and also, the symmetry, matching and combine requirements.”. (Pg. 321-322 and Fig. 9).
This shows based on received rules forming a circuit based on the layout portions.
determine, for each circuit portion of the plurality circuit portions, respective technical criteria for that circuit portion;
“Fig. 9. Single ended two-stage amplifier: graphical representation of the template, showing the relative location of the devices; and part of the XML description of the layout guidelines (floorplan.xml file), showing the constructs and illustrating the hierarchy, with part of the sub-floorplan file for partition P1A shown inline. (For interpretation of the references to color in this figure, the reader is referred to the web version of this article.)”. (Pg. 320).
“4.1.3. Layout guidelines The layout guidelines, which are also described in XML, provide an abstract floorplan view and are parameterized to include the design variables. This high level floorplan is defined using simple rectangular constructs that capture the proximity and topological relations that the designer wishes to impose. The information used for placement is the type and relative placement of the cells, and also, the symmetry, matching and combine requirements. Particularly, the high level floorplan of each cell is described by a box shape…”. (Pg. 321).
This shows technical criteria descriptions for respective portions of the circuit.
produce a set of designs comprising a respective design for each circuit portion;
“The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout.”. (Abstract).
This shows a module generator produces a respective module level design for each placed “cell” of the circuit.
for at least one circuit portion of the plurality of circuit portions obtain information relating to parasitics that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion;
“By using a lightweight built-in extractor it is possible to accurately compute the impact of layout parasitics for both floorplan and early-stages of routing, without requiring the detailed final layout (i.e., all design-rules and layout-versus schematic errors solved) [27]. Traditionally, the last step required in the automatic layout generation flow is the detailed routing, which is by far the most computational intensive and time consuming step.”. (Pg. 317).
This shows an extractor obtaining parasitic information for the designed cells directly from in the in loop generated floor plan.
adapt the design of at least one circuit portion based on the obtained information relating to parasitics; and
“Furthermore, when using the layout-aware aspect of the tool, a built-in extractor is used to accurately compute the impact of parasitic from both floor plan and early-stages of routing, and use that information to perform a floorplan- and parasitic-aware optimization [27]. The above characteristics together with a powerful multi-objective multi-constraint optimization engines guarantee the solution robustness against environment and process variations.”. (Pg. 320).
This shows AIDA feed the extracted parasitics back into its multi objective optimization kernel to perform “parasitic aware optimization” iteratively adapting the per portion design variables.
output a complete circuit design including at least one circuit portion adapted based on obtained information relating to parasitics.
“AIDA's output is a family of Pareto optimal sized circuits that fulfill all the constraints and represent the feasible tradeoffs between the different optimization objectives, where each sizing solution is aware of the impact of layout parasitic and worst case corner conditions.”. (Pg. 325).
This shows AIDA outputs a complete sized circuit design via parameter files and layout files in which each portion has been adapted under the parasitic aware optimization loop.
Regarding Claim 4, LOURENCO teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the design apparatus is configured to obtain information relating to parasitics, that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion, by mathematically simulating the performance of at least one of (i) the designed circuit portion and (ii) a complete analogue circuit comprising the designed circuit portion, in a virtual test bench.“AIDA inputs circuit-level standard Spice-like netlists for both circuit and testbench(es) descriptions, which are easily exported from most commercial IC design suites. The integration in the traditional analog design flow is further enforced by interfacing directly with the industry standard electrical simulators: Synopsys' HSPICEs [2], Mentor Graphics' ELDOs [3] and Cadence's SPECTREs [1], for the circuit's performance evaluation.”. (Pg. 320).
“In addition to the circuit netlist, testbench(es) with the statements to measure the circuit's performance must be added. AIDA C parses the measures files obtained using the simulator's .measure/.extract commands [31,32] to read the simulation results.”. (Pg. 321).
“Both circuits’ performances, simulated using the netlist extracted both from AIDA-PEx [27] and from CALIBREs, are presented in Table 3… In the layout-aware sizing optimization, the circuit is wittingly over estimated so that when the parasitic components are added the specifications are all fulfilled.”. (Pg. 327).
This shows defining a testbench for circuit performance measurements that include parasitic extracted netlists in its bench environment to obtain parasitic aware performance.
Regarding Claim 10, LOURENCO teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the analogue circuit design apparatus is configured to adapt the design of its respective circuit portion in the event that the information relating to parasitics experienced by the generated design indicates that the parasitics are greater than a selected threshold level of parasitics.
“This paper presents AIDA, an enhanced version of AIDA [7], an analog integrated circuit design automation environment. The new version addresses robust simulation-based circuit-level sizing with worst case process, voltage and temperature (PVT) corners accounted in the performance evaluation, automatic layout generation and parasitic extraction capabilities.”. (Pg. 316).
“Performance/Functional Constraints The upper and lower bounds to any of the available measures can be set. The functional constraints are more general to the circuit and usually specified when adding it to the library, whereas the performance constraints would be more target dependent, being defined only for a specific circuit target.”. (Pg. 323).
“This did not happened with the inclusion of the layout effects alone, where the evolutionary kernel was able to adjust the sizes of the devices to compensate for the layout parasitics without sacrificing the spread of the solutions.”. (Pg. 328).
This shows having upper and lower bounds for a threshold to trigger the optimization of parasitic aware adaptation for the circuit portions.
Claim 13 recites sustainably the same limitations as claim 1 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claim 16 recites sustainably the same limitations as claim 4 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claim 25 recites sustainably the same limitations as claim 1 except this claim is directed to a “method” with “computer readable non-transitory storage medium”. Therefore this, claim is rejected for the same rationale as addressed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 2 and 14 are rejected under 35 U.S.C 103 as being unpatentable over LOURENCO et al. “AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation” (2016) [herein “LOURENCO”] and HARJANI et al “A Prototype Framework for Knowledge-Based Analog Circuit Synthesis” (1987) [herein “HARJANI”].
Regarding Claim 2, LOURENCO teaches
e) obtain information relating to parasitics that will be experienced in the circuit portion, and/or in the analogue circuit if the analogue circuit were to include that circuit portion; and
“…when using the layout-aware aspect of the tool, a built-in extractor is used to accurately compute the impact of parasitic from both floor plan and early-stages of routing, and use that information to perform a floorplan- and parasitic-aware optimization…”. (Pg. 320).
This shows determining the parasitic impact of the circuit based on the portions.
wherein at least one of the secondary design units is configured to adapt the design of its respective circuit portion based on the information relating to parasitics; and
“…where the evolutionary kernel was able to adjust the sizes of the devices to compensate for the layout parasitics without sacrificing the spread of the solutions.”. (Pg. 328).
This shows the kernel being able to adjust the sizes of the devices to compensate for the layout parasitics for each circuit portion.
wherein the primary design unit is configured to output the complete circuit design including the at least one adapted circuit portion.
“AIDA's output is a family of Pareto optimal sized circuits that fulfill all the constraints and represent the feasible tradeoffs between the different optimization objectives, where each sizing solution is aware of the impact of layout parasitic and worst case corner conditions.”. (Pg. 325).
This shows the system outputting a complete circuit design in which the portions have already been adapted under the parasitic aware optimization loop.
LOURENCO does not explicitly teach but HARJANI teaches
The analogue circuit design apparatus of claim 1, wherein the apparatus comprises:
a primary design unit and a plurality of secondary design units;
“A topology for a high-level module (e.g., an A/D converter) is specified as an inter- connection of sub-blocks, not as an interconnection of transistors. That the topology is fixed implies only that this arrangement of sub-blocks is fixed; the detailed design of the individual sub-blocks is not specified here. Because of this explicit hierarchy, one high-level topology of blocks can specify many device- level topologies.”. (Pg. 44).
OASYS has a higher-level module with a plurality of sub blocks disclosing the primary and secondary architecture.
wherein the primary design unit is configured to:
identify, based on the received information, the plurality of circuit portions for forming the analogue circuit;
“A particular topology is chosen because it is the one best able to be configured to match the specified block-level behavior; the translation step then decides how the sub-blocks must behave to meet the block-level specification.”. (Pg. 45).
This shows a primary block selecting subblocks i.e. portions that will form the circuit on the basis of the inputted information.
determine, for each circuit portion of the plurality circuit portions, the respective technical criteria for that circuit portion and
provide the respective technical criteria for each circuit portion to at least one of the plurality of secondary design units;
“After selecting a topology to accommodate a set of performance specifications given at one level of the hierarchy, we translate these higher-level specifications into specifications for the performance of each sub-block of the topology. Informally, we are given the behavior of the interconnected sub-blocks taken as a whole, and we must deduce the specifications for each sub-block re- quired to achieve this overall behavior.”. (Pg. 44).
This shows the primary block translating the high-level specification into sub blocks i.e. for circuit portions.
wherein each of the plurality of secondary design units of the analogue circuit design apparatus is configured to:
a) design a respective circuit portion of the plurality of circuit portions based on technical criteria provided by the primary design unit; and
“The OASYS hierarchy was selected to explore two levels of design style selection and specification translation: (relatively first select op amp design style easy since we currently implement only two styles) and translate op amp specifications into specifications for sub- blocks (current mirrors, differential pairs, etc.); and second, select design styles for each sub-block and then translate each sub-block specification into device interconnections and sizes.”. (Pg. 46).
At the second hierarchical level each sub block (a secondary design unit) takes the sub block specification provided by the primary and uses it to select a design style and translate the specification to meet the criteria provided.
b) output a resulting design of the respective circuit portion; and wherein the primary design unit is further configured to:
“The two-step selection/translation lustrated designers. in the implementation of one of the simple subblock There are two possible topologies (simple and cascade) for a current mirror. Selection is based primarily on area, as evaluated from circuit equations; the style with the smaller area is selected. However, the detailed design of one topology requires some simple heuristics, because many possible combinations of device sizes can achieve the same overall mirror performance. For example, in a four-transistor cascade topology, we choose to fix the length of two devices at their minimum size, and require the width of all four devices to be equal. This produces a workable, unique solution.”. (Pg. 47).
The sub block designer produces a sub block design for its respective portion.
c) obtain a set of designs comprising a respective design for each circuit portion from each of the plurality of secondary design units;
“Figure 4 illustrates has just an example (two-stage) op amp topology template used in OASYS. Because this version of OASYS two design styles, there is minimal high-level design style selection. We currently attempt to design each style, and if both can meet the specification, select the one with the best match to the specifications, biasing the choice in favor of the design with the smallest estimated area. Area estimates include both active device area and compensation capacitor area. This version of OASYS mainly does translation, from the op amp specifications to dividual sub-blocks. the specifications Sub-blocks include differential rent mirrors, level shifters, and transconductance amplifiers. However, for each sub-block, both style selection and translation are required.”. (Pg. 47).
The topology template aggregates a sized design from each separately designed sub block.
d) generate at least an initial design for the analogue circuit based on the set of designs;
“From these inputs, OASYS produces a sized transistor-level circuit schematic.”. (Pg. 46).
This shows assembling an analogue circuit design based on the set of sub block designs.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teachings of HARJANI’s hierarchical analogue circuit design comprising design units with LOURENCO’s layout aware circuit system. The motivation for doing so would have been to create a more informed circuit designer system as stated by HARJANI “…a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower.”. (Abstract).
Claim 14 recites sustainably the same limitations as claim 2 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claims 3, 5, 6, 7, 15, 17, 18, and 19 are rejected under 35 U.S.C 103 as being unpatentable over LOURENCO et al. “AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation” (2016) [herein “LOURENCO”], HARJANI et al “A Prototype Framework for Knowledge-Based Analog Circuit Synthesis” (1987) [herein “HARJANI”], and KUKAL et al US 8316342 B1 (2012) [herein “KUKAL”].
Regarding Claim 3, neither LOURENCO nor Harjani et al teach but KUKAL teaches
The analogue circuit design apparatus of claim 2 wherein the analogue circuit design unit is configured to populate a database of parasitics and circuit designs by repeating the steps a) to e) a plurality of times, wherein each time the steps a) to e) are repeated new technical criteria are provided by the primary design unit.
“… layout synchronization stage 82 to perform a layout-versus-schematic synch up of the first and second partitions”. (0068).
“The updating of any of the first and second partitions at design stages 84 and 86 may include entering new electronic components into any of the first and second partitions. Thus, the design flow may proceed thereafter with repeating the design stages 40 and 60 in the first design entry tool or design stages 50 and 70 in the second design entry tool to exchange interfaces and export the corresponding partition.”. (0069).
“The workstations 410, 420, and 440 may also communicate with each other to exchange data by accessing a shared memory component on the database server 430, for example by reading from and/or writing to a database within the shared memory component in the database server 440.”. (0075).
This shows portioned netlists with layout parasitics stored on the shared database server and the design flow repeats each iteration for the changing electrical components.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teachings of KUKAL’s analogue circuit design comprising database writings and lookups with modified LOURENCO-HARJANI’s layout aware circuit system. The motivation for doing so would have been to create a connected circuit designer system to test more efficiently as stated by KUKAL “To allow simulation using reuse modules, netlists must be exchanged in advance across design entry tools, and components of the reuse module… “. (0007) and “…to create or update the design of components of a partition by accessing a shared file representing the common layout 350 or updating a database.”. (0108).
Regarding Claim 5, neither LOURENCO not HARJANI explicitly teach but KUKAL teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the design apparatus is configured to obtain information relating to parasitics, that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion, by performing a lookup in a database of circuit designs and parasitics.
“FIG. 13 shows an exemplary block diagram of a system for concurrently designing an electronic circuit across different design entry tools according to an embodiment of the invention. Referring to FIG. 13, the system 400 includes a schematic design workstation 410, a spreadsheet design workstation 420, a database server 430, and a placement and routing workstation 440. The workstations 410, 420, and 440 may communicate with each other to exchange data via an interconnecting network (not shown), for example, a local area network or a wide area network, or a combination of a local area network and a wide area network. The workstations 410, 420, and 440 may also communicate with each other to exchange data by accessing a shared memory component on the database server 430, for example by reading from and/or writing to a database within the shared memory component in the database server.“. (0075).“…the design of the electronic circuit includes a layout synchronization stage 82 to perform a layout-versus-schematic synch up of the first and second partitions with the common layout.”. (0068).
This shows obtaining parasitic information for a partition by reading the parasitic back annotated partition netlist from the database server i.e. by performing a lookup in a database of circuit designs and parasitics.
Regarding Claim 6, neither LOURENCO NOR HARJANI explicitly teach but KUKAL teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the design apparatus is configured to obtain information relating to parasitics experienced by that generated design by performing a lookup, in a database of circuit designs and parasitics, for similar generated designs.
“FIG. 13 shows an exemplary block diagram of a system for concurrently designing an electronic circuit across different design entry tools according to an embodiment of the invention. Referring to FIG. 13, the system 400 includes a schematic design workstation 410, a spreadsheet design workstation 420, a database server 430, and a placement and routing workstation 440. The workstations 410, 420, and 440 may communicate with each other to exchange data via an interconnecting network (not shown), for example, a local area network or a wide area network, or a combination of a local area network and a wide area network. The workstations 410, 420, and 440 may also communicate with each other to exchange data by accessing a shared memory component on the database server 430, for example by reading from and/or writing to a database within the shared memory component in the database server.“. (0075).“…the design of the electronic circuit includes a layout synchronization stage 82 to perform a layout-versus-schematic synch up of the first and second partitions with the common layout.”. (0068).
This shows the tool retrieving a parasitic back annotated partition from the database by reading the corresponding partition i.e. it performs a look up in a database of circuit designs and parasitics corresponding to the generated design.
Regarding Claim 7, NEITHER LOURENCO NOR HARJANI explicitly teach but KUKAL teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the design apparatus is configured to perform a lookup, in a database of circuit designs and parasitics, for at least one of the respective circuit portions for similar respective circuit portions, and wherein the design apparatus is configured to obtain information relating to parasitics experienced by the generated design based on the values of parasitics obtained via the lookup for the at least one of the respective circuit portions.
“The schematic design workstation 410 and the spreadsheet design workstation can cooperate to concurrently design an electronic circuit, for example a mixed SiP circuit after the design of the mixed signal SiP circuit has been logically partitioned, as shown in FIG. 2 above, into a first partition that includes an analog partition 100 of the mixed SiP circuit, and a second partition that includes a digital partition 200 of the mixed SiP circuit.”. (0075).
“…the electronic circuit includes a layout synchronization stage 82 to perform a layout-versus-schematic synch up of the first and second partitions with the common layout. At this stage 82, each of the first and second design entry tools checks whether the placement and routing processes have changed instances of any of the first and second electronic components, or changed connectivity between any of the first and second electronic components in the common layout. If any change is detected at design stage 82, the first design entry tool updates the first partition at a first update stage 84 to reflect instances and connectivity changes in the first partition from the common layout. Similarly, the second design entry tool updates the second partition…”. (0068).
“…exchange data by accessing a shared memory component on the database server 430, for example by reading from and/or writing to a database within the shared memory component…”. (0075).
This shows a look up of a parasitic back annotated per partition netlists from the shared database each partition being one circuit portion and combining them in the common layout to obtain parasitic picture of the whole circuit.
Claim 15 recites sustainably the same limitations as claim 3 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claim 17 recites sustainably the same limitations as claim 5 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claim 18 recites sustainably the same limitations as claim 6 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claim 19 recites sustainably the same limitations as claim 7 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
Claims 8 and 9 are rejected under 35 U.S.C 103 as being unpatentable over LOURENCO et al. “AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation” (2016) [herein “LOURENCO”] and WU et al CN 109710960 A (2019) [herein “WU”].
Regarding Claim 8, LOURENCO does not explicitly teach but WU teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the design apparatus is configured to obtain information relating to parasitics experienced by that generated design by using a machine learning model to predict the parasitics.
“AI 605 can predict a unit delay variation caused by change of process x and the known process of Δ TCDx, and a prediction device planning effect and changes of other RC factor Δ R0x, Δ R1x, Δ Rnx, Δ C0x, Δ C1x, ..., Δ CILL). relative to a known technique, the AI training 605 can almost instantly predict the new device parameter.”. (Pg. 18 and 19).
This shows a trained AI machine learning system to predict the parasitics for the resulting device. (Δ R0x, Δ R1x, Δ Rnx, Δ C0x, Δ C1x, ..., Δ CILL).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teachings of WU’s analogue circuit design comprising machine learning with LOURENCO’s layout aware circuit system. The motivation for doing so would have been to create a predictive circuit designer system as stated by WU “…manufacturing technology involves training the artificial intelligence to obtain the forecasting artificial intelligent training data as input, training data includes extracting the semiconductor device unit parameter and the first process parameters or materials.”. (Abstract).
Regarding Claim 9, LOURENCO does not explicitly teach but WU teaches
The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the parasitics include at least one of parasitic capacitances, parasitic resistances, and parasitic inductances.
“AI 605 can predict a unit delay variation caused by change of process x and the known process of Δ TCDx, and a prediction device planning effect and changes of other RC factor Δ R0x, Δ R1x, Δ Rnx, Δ C0x, Δ C1x, ..., Δ CILL). relative to a known technique, the AI training 605 can almost instantly predict the new device parameter.”. (Pg. 18 and 19).
This shows a parasitic including at least one of parasitic capacitances, parasitic resistances, and parasitic inductances.
Claim 11 is rejected under 35 U.S.C 103 as being unpatentable over LOURENCO et al. “AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation” (2016) [herein “LOURENCO”] and GAO et al CN 108399299 A (2018) [herein “GAO”].
Regarding Claim 11, LOURENCO teaches The analogue circuit design apparatus of any of the previous claim[[s]] 1 wherein the apparatus is configured to adapt the design of the respective portion based on the information relating to parasitics, as stated above in the rejection of claim 1.
However, LOURENCO does not explicitly teach but GAO teaches
adapt the design … by adapting the corresponding technical criteria of the respective circuit portion.
“The embodiment of the invention claims an integrated circuit physical layout generating method, comprising the following steps: the circuit schematic diagram of the integrated circuit system according to the function is divided into a plurality of cells, by using physical layout cell library to generate the physical layout unit corresponding to each unit, each physical layout classifying unit. the physical layout units of different types using different constraint conditions for placing and routing, parasitic extraction precision of parameter according to physical layout unit of the importance and the circuit connecting the circuit performance influence degree adjusting said physical layout unit and circuit connection and physical layout simulation verification”. (Abstract).
“The layout wiring optimization of positioning result control increment, until the final layout and wiring result satisfies the design requirement.”. (Pg. 9).
“… the signal circuit unit layout and wiring by extracting parasitic parameter estimated parasitic effects on line, optimizing signal circuit unit according to the estimated parasitic effects of the layout and/or wiring, and/or wire mesh to be loaded current value, and maximum allowed parasitic capacitance and the parasitic resistance determines the width of the connection.”. (Pg. 12).
This shows an analogue circuit adapting to the portion based on information relating to the parasitics corresponding to the technical criteria.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teachings of GAO’s parasitcs informed analogue circuit design system with LOURENCO’s layout aware circuit system. The motivation for doing so would have been to create a parasitic informed circuit designer system as stated by GAO “…for placing and routing, parasitic extraction precision of parameter according to physical layout unit of the importance and the circuit connecting the circuit performance influence degree adjusting said physical layout unit...”. (Abstract).
Claim 12 is rejected under 35 U.S.C 103 as being unpatentable over LOURENCO et al. “AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation” (2016) [herein “LOURENCO”], KUKAL et al US 8316342 B1 (2012) [herein “KUKAL”], and WU et al CN 109710960 A (2019) [herein “WU”].
Claim 12 recites sustainably the same limitations as claims 2, 3, and 8 except this claim is directed to a “method”. Therefore this, claim is rejected for the same rationale as addressed above.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teachings of KUKAL’s analogue circuit design comprising database writings and lookups with LOURENCO’s layout aware circuit system. The motivation for doing so would have been to create a connected circuit designer system to test more efficiently as stated by KUKAL “To allow simulation using reuse modules, netlists must be exchanged in advance across design entry tools, and components of the reuse module… “. (0007) and “…to create or update the design of components of a partition by accessing a shared file representing the common layout 350 or updating a database.”. (0108).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teachings of WU’s analogue circuit design comprising machine learning with LOURENCO-KUKAL’s reusable layout aware circuit system. The motivation for doing so would have been to create a predictive circuit designer system as stated by WU “…manufacturing technology involves training the artificial intelligence to obtain the forecasting artificial intelligent training data as input, training data includes extracting the semiconductor device unit parameter and the first process parameters or materials.”. (Abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US-20080016483-A1 CHAN et al teaches a method of synthesizing a layout of an integrated circuit chip including analog circuitry.
US 8656328 B1 SARWARY et al teaches a method for abstraction of portions of a circuit for functional verification of properties in an integrated circuit.
US 7793243 B1 BECER et al teaches a system for circuit timing analysis that includes a database for holding results of execution of portions of a timing analysis computation.
“OASYS: A Framework for Analog Circuit Synthesis” by HARJANI teaches circuit synthesis.
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/N.E.M./Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189
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