DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/10/2025 have been fully considered but they are not persuasive. Applicant’s first argument is as follows:
“This rejection is improper because the Applicant's invention achieves a technical goal, and, as a result, the claimed inventions, structurally operate in a way that is fundamentally different from the teachings of Nishimoto…The Applicant's specification defines a problem and provides a specific solution: employing redesigned electrodes (Metamaterials) concepts to deliberately design a new drain electrode that achieves an "almost identical" phase velocity match to the gate electrode. This process is a compensation for the phase-velocity mismatch induced by the transistor's intrinsic properties. The objective is to use a structured electrode (a patterned metamaterial) to introduce specific wave-shifting effects (inductance and capacitance) to precisely match the phase velocities of the input and output lines. Nishimoto's objective is to mitigate the phase velocity mismatch vector by primarily reducing the parasitic gate-to-drain capacitance and/or modifying the device width. The proposed solution must achieve the desired high gain for a specific, fixed device width; therefore, simply modifying the width is contrary to the invention's purpose…
The Office Action's interpretation overlooks the core technical problem the claimed inventions solve. Nishimoto fails to discuss wave propagation effects, which are the primary phenomena that limit device gain in this high-frequency regime. Nishimoto's Figure 3 illustrates a method focused narrowly on shifting the location of the secondary gain region (labeled 56). In contrast, the Applicant's invention provides a fundamental method to redesign the electrodes and the transmission line section. This technique is capable of compensating for the severe gain degradation across a wide frequency band, effectively eliminating the drastic drop in gain shown between approximately 10 GHz and 75 GHz in Nishimoto's curve (54), ensuring the device provides a considerable and continuous gain across the entire high-frequency band...
Moreover, there are substantial structural and operational differences between the inventions of claim 6 and the Nishimoto's devices. Applicant's inventions utilize a redesigned metamaterial arrangement (Fig. 6) that is described as imposing extra capacitance to reduce the signal velocity on the drain line. This is fundamentally different from Nishimoto's consistent goal of reducing parasitic capacitance and altering the width. The non- obviousness lies in recognizing that phase-match requires intentionally altering the phase velocity, and then using a patterned metamaterial structure to introduce precise and deliberate electromagnetic wave manipulation to achieve that goal…
Moreover, there are substantial structural and operational differences between the inventions of claim 11 and the Nishimoto's devices. Applicant's inventions utilize a redesigned metamaterial arrangement (Fig. 6) that is described as imposing extra capacitance to reduce the signal velocity on the drain line. This is fundamentally different from Nishimoto's consistent goal of reducing parasitic capacitance and altering the width. The non-obviousness lies in recognizing that phase-match requires intentionally altering the phase velocity, and then using a patterned metamaterial structure to introduce precise and deliberate electromagnetic wave manipulation to achieve that goal.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., redesigned electrodes that achieve substantially identical phase velocity match to the gate electrode via patterned metamaterials, discussion of wave propagation effects, gain across high-frequency band) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Note that “matched” as claimed does not require a 1:1 ratio of the phase velocity of the input port to the output port. Matched can also be defined as “complimentary/corresponding to one another”, e.g., a color scheme between multiple clothing items or the interlocking of jigsaw puzzle pieces. Since Nishimoto teaches the selection of transistor size based on a desired operating frequency range, output power and acceptable phase velocity mismatch (Figure 10), the phase velocity on the input and output ports are matched to the user’s preference.
Furthermore, when the phase velocity at the input of Nishimoto’s transistor is zero, the phase velocity at the output is zero. Thus, they are matched.
Applicant’s second argument is as follows:
“… the claim elements found in claim 6 do not include ranges. They include specific claim elements that require: 1) a first wave shifting electrode to increase the input phase velocity to a device phase velocity and; 2) a second wave shifting electrode to decrease the device phase velocity to the desired output phase velocity…This stands in contrast to In re Aller…Nowhere in claim 6 is a numeric range found. Instead, claim 6 recites specific requirements. Further, the Office Action fails to articulate with any specificity or detail how a claim requirement with exact requirements equates to a range.
… the claim elements found in claim 11 do not include ranges. They include specific claim elements that require: 1) an input multiple finger connection, the input multiple finger connection using input wave shifting electrodes to increase the input phase velocity on the input line to the device phase velocity; and 2) an output multiple finger connection, the output finger connection using output wave shifting electrodes to decrease the device phase velocity to the desired output phase velocity…This stands in contrast to In re Aller…Nowhere in claim 11 is a numeric range found. Instead, claim 11 recites specific requirements. Further, the Office Action fails to articulate with any specificity or detail how a claim requirement with exact requirements equates to a range.”
The 5/8/2025 Non-Final Rejection discusses in ¶19-21 how Nishimoto teaches that input phase velocity and output phase velocity can be tuned (i.e., increased or decreased) by modifying transistor dimensions. A specific phase velocity mismatch achieved by a selection of values within a tuning range would merely require simple experimentation as the phase velocity mismatch can be set to any value desired. Thus, creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation).
Furthermore, Applicant has failed to provide evidence of an unexpected result or criticality as to why Nishimoto cannot be tuned to provide the limitations regarding phase velocity of claims 6 and 11. Note MPEP 2144.05 which states:
Applicants can rebut a prima facie case of obviousness by showing the criticality of the range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims…In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)…
… In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946) (“Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies.”)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimoto et al (US 2007/0252643).
For claim 1, Nishimoto teaches a transistor (Figure 4, transistor at step 260 of Figure 10) with an input port (SIGNAL_IN) and an output port (SIGNAL_OUT), the transistor having matched phase velocity on the input and output ports ([0034], [0043], Figure 10).
For claim 3, Nishimoto teaches a transistor electrode (gate or drain, Figure 4) compensating for a phase-velocity mismatch induced by the transistor's intrinsic properties ([0034], [0043], Figures 4 and 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 5-6 and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishimoto.
For claim 2, Nishimoto teaches the limitations of claim 1 but fails to explicitly teach the finger width.
However, it is noted that Nishimoto teaches a transistor width of ¼ of an operating frequency within the desired operating frequency range ([0037] and claim 13).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the finger width of Nishimoto’s transistor to be greater than 1/10 of the wavelength since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 5, Nishimoto teaches an electronic device (Figure 4) with modified electrodes (gate and drain) that have modified electromagnetic-wave phase velocity ([0034], [0043], Figure 10).
Nishimoto fails to distinctly disclose equal electromagnetic-wave phase velocity.
However, [0044] teaches that “tuning can be achieved by modifying transistor dimensions to effect capacitances associated with the base, emitter, collector and width of the respective BJT or HBT…such that phase velocity mismatch can be modified…”
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to modify the dimensions of Nishimoto’s gate and drain electrodes such that they have equal electromagnetic-wave phase velocity since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 6, Nishimoto teaches an electronic device (Figure 4) for receiving an input electromagnetic wave on an input line (SIGNAL_IN) including an input phase velocity (Abstract), comprising:
a first wave shifting electrode (gate) to modify the input phase velocity ([0034], [0043], Figure 10);
a second wave shifting electrode (drain) to modify the device phase velocity.
Nishimoto fails to distinctly disclose:
a first wave shifting electrode to increase the input phase velocity to a device phase velocity.
a second wave shifting electrode to decrease the device phase velocity to the desired output phase velocity.
However, [0044] teaches that “tuning can be achieved by modifying transistor dimensions to effect capacitances associated with the base, emitter, collector and width of the respective BJT or HBT…such that phase velocity mismatch can be modified…”
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to modify the dimensions of Nishimoto’s gate electrode such that the input phase velocity is increased to a device phase velocity and modify the dimensions of Nishimoto’s drain electrode such that the device phase velocity is decreased to the desired output phase velocity since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 8, Nishimoto teaches an electronic device with a device phase velocity (Figure 4) connected to an output line (SIGNAL_OUT) with a desired output phase velocity (Abstract), the electronic device comprising:
a wave shifting electrode to modify the device phase velocity ([0034], [0043], Figure 10).
Nishimoto fails to distinctly disclose:
a wave shifting electrode to decrease the device phase velocity to the desired output phase velocity.
However, [0044] teaches that “tuning can be achieved by modifying transistor dimensions to effect capacitances associated with the base, emitter, collector and width of the respective BJT or HBT…such that phase velocity mismatch can be modified…”
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to modify the dimensions of Nishimoto’s gate and/or drain electrode such that the device phase velocity is decreased to a desired output phase velocity since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 9, Nishimoto teaches an electronic device (Figure 4) with a device phase velocity (Abstract) for receiving an input electromagnetic wave with an input phase velocity on an input line (SIGNAL_IN), the electronic device comprising:
at least one multiple finger connection (gate, [0032] and Figure 4), the at least one finger connection using wave shifting electrodes (gate and drain) to modify the input phase velocity on the input line ([0034], [0043], Figure 10).
Nishimoto fails to distinctly disclose:
the at least one finger connection using wave shifting electrodes to increase the input phase velocity on the input line to the device phase velocity.
However, [0044] teaches that “tuning can be achieved by modifying transistor dimensions to effect capacitances associated with the base, emitter, collector and width of the respective BJT or HBT…such that phase velocity mismatch can be modified…”
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to modify the dimensions of Nishimoto’s gate and/or drain electrodes such that the input phase velocity is increased to the device phase velocity since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 10, Nishimoto teaches an electronic device (Figure 4) with a device phase velocity (Abstract) for sending an output electromagnetic wave with a desired output phase velocity on an output line (SIGNAL_OUT), the electronic device comprising:
an output multiple finger connection (drain, [0032] and Figure 4), the at least one finger connection using wave shifting electrodes (gate and drain) to modify the device phase velocity
Nishimoto fails to distinctly disclose:
the at least one finger connection using wave shifting electrodes to decrease the device phase velocity to the desired output phase velocity.
However, [0044] teaches that “tuning can be achieved by modifying transistor dimensions to effect capacitances associated with the base, emitter, collector and width of the respective BJT or HBT…such that phase velocity mismatch can be modified…”
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to modify the dimensions of Nishimoto’s gate and/or drain electrode such that the device phase velocity is decreased to a desired output phase velocity since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 11, Nishimoto teaches an electronic device (Figure 4) with a device phase velocity (Abstract) for receiving an input electromagnetic wave with an input phase velocity on an input line (SIGNAL_IN), the electronic device comprising:
an input multiple finger connection (gate, [0032] and Figure 4), the input multiple finger connection using input wave shifting electrodes to increase the input phase velocity on the input line to the device phase velocity; and
an output multiple finger connection, the output finger connection using output wave shifting electrodes to decrease the device phase velocity to the desired output phase velocity.
Nishimioto fails to distinctly disclose:
the input multiple finger connection using input wave shifting electrodes to increase the input phase velocity on the input line to the device phase velocity; and
the output finger connection using output wave shifting electrodes to decrease the device phase velocity to the desired output phase velocity.
However, [0044] teaches that “tuning can be achieved by modifying transistor dimensions to effect capacitances associated with the base, emitter, collector and width of the respective BJT or HBT…such that phase velocity mismatch can be modified…”
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to modify the dimensions of Nishimoto’s gate and drain electrodes such that the input phase velocity is increase to the device phase velocity and the device phase velocity is decreased to the desired output phase velocity since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849