DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The Rejection of Claims 13 and 14 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for the limitation “wherein each of the plurality of functional modules and one of the plurality of power supply modules disposed directly adjacent to the each of the plurality of functional modules are positioned on different sides of the insulating substrate” is withdrawn in light of the amendment to at least Claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 – 7, and 15 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (U.S. PG Pub 2016/0035308) in view of Ura et al. (U.S. PG Pub 2015/0124006).
Regarding Claim 1, Ota teaches a semiconductor device (Figure 1. Paragraph 38), comprising:
an insulating substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.); and
a driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) positioned on the insulating substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.), wherein the driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) comprises a plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78) and a plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) , and the plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) are disposed adjacent to and electrically connected to the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78), respectively;
wherein at least one of the power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) comprises:
a power supply assembly (Figure 4, Element 500. Paragraph 71); and
a voltage regulation module (Figure 4, Elements 241 - 261. Paragraphs 70 - 73) electrically connected between (Seen in Figure 4) the power supply assembly (Figure 4, Element 500. Paragraph 71) and one of the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78);
wherein the voltage regulation module (Figure 4, Elements 241 - 261. Paragraphs 70 - 73) comprises a switch assembly (Figure 4, Element Switch. Paragraph 107) and a share assembly (Figure 4, Element 241. Paragraph 71) electrically connected to each other (Paragraph 107), and wherein the share assembly (Figure 4, Element 241. Paragraph 71) is configured to reduce a current (Paragraph 87) of the switch assembly (Figure 4, Element Switch. Paragraph 107) while ensuring that a total current flowing through the switch assembly (Figure 4, Element Switch. Paragraph 107) and the share assembly (Figure 4, Element 241. Paragraph 71) has a constant magnitude (Paragraph 87); and
wherein each of the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78) and one of the power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) disposed adjacent to the each of the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78) are positioned on a same side (Seen in Figure 4) or on different sides of the insulating substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.).
Ota is silent with regards to wherein the insulating substrate and the driving circuit are integrated into a single chip.
Ura et al. teach wherein the insulating substrate (Figure 1, Element not labeled, but is the substrate. Paragraph 32) and the driving circuit (Figure 1, Element 10. Paragraph 32) are integrated into a single chip (Paragraph 32).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota with the single chip of Ura et al. The motivation to modify the teachings of Ota with the teachings of Ura et al. is to suppress the worsening of the capability of converging gradation lines in the display driver, as taught by Ura et al. (Paragraph 33).
Regarding Claim 6, Ota teaches a semiconductor device (Figure 1. Paragraph 38), comprising:
an insulating substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.); and
a driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) positioned on the insulating substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.), wherein the driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) comprises a plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78) and a plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74);
wherein the plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) are disposed adjacent to and electrically connected to the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78), respectively.
Ota is silent with regards to wherein the insulating substrate and the driving circuit are integrated into a single chip.
Ura et al. teach wherein the insulating substrate (Figure 1, Element not labeled, but is the substrate. Paragraph 32) and the driving circuit (Figure 1, Element 10. Paragraph 32) are integrated into a single chip (Paragraph 32).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota with the single chip of Ura et al. The motivation to modify the teachings of Ota with the teachings of Ura et al. is to suppress the worsening of the capability of converging gradation lines in the display driver, as taught by Ura et al. (Paragraph 33).
Regarding Claim 7, Ota in view of Ura et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 6 (See Above). Ota teaches wherein at least one of the power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) comprises:
a power supply assembly (Figure 4, Element 500. Paragraph 71); and
a voltage regulation module (Figure 4, Elements 241 - 261. Paragraphs 70 - 73) electrically connected between (Seen in Figure 4) the power supply assembly (Figure 4, Element 500. Paragraph 71) and one of the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78);
wherein the voltage regulation module (Figure 4, Elements 241 - 261. Paragraphs 70 - 73) comprises a switch assembly (Figure 4, Element Switch. Paragraph 107) and a share assembly (Figure 4, Element 241. Paragraph 71) electrically connected to each other, and wherein the share assembly (Figure 4, Element 241. Paragraph 71) is configured to reduce a current (Paragraph 87) of the switch assembly (Figure 4, Element Switch. Paragraph 107) while ensuring that a total current flowing through the switch assembly (Figure 4, Element Switch. Paragraph 107) and the share assembly (Figure 4, Element 241. Paragraph 71) has a constant magnitude (Paragraph 87).
Regarding Claim 15, Ota in view of Ura et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 6 (See Above). Ota teaches wherein the plurality of the functional modules (Figure 4, Elements 201 - 230. Paragraphs 65 - 69) comprise a control module (Figure 4, Element 213. Paragraph 68), a memory module (Figure 4, Element 201. Paragraph 65), and an analog module (Figure 4, Element 203. Paragraph 66).
Regarding Claim 16, Ota in view of Ura et al. teach an electronic terminal comprising the semiconductor device (Ota. Figure 1. Paragraph 38) according to claim 6 (See Above).
Regarding Claim 17, Ota in view of Ura et al. teach the electronic terminal according to claim 16 (See Above). Ota teaches further comprising a panel main body (Figure 2, Element SUB1. Paragraph 47. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.), wherein the panel main body (Figure 2, Element SUB1. Paragraph 47. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.) has a display region (Figure 2, Element DA. Paragraph 48) and a non-display region (Figure 2, Element not DA. Paragraph 48), and wherein the panel main body (Figure 2, Element SUB1. Paragraph 47. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.) comprises:
a circuit layer comprising a display circuit portion (Figure 2, Element PX. Paragraph 51) positioned in the display region (Figure 2, Element DA. Paragraph 48) and a driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) portion positioned in the non-display region (Figure 2, Element not DA. Paragraph 48), wherein the driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) portion is electrically connected to (Seen in Figure 2) the display circuit portion (Figure 2, Element PX. Paragraph 51).
Regarding Claim 18, Ota in view of Ura et al. teach the electronic terminal according to claim 17 (See Above). Ota teaches wherein the driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) portion comprises a plurality of functional portions (Figure 4, Elements 201 – 230 and 301 - 330. Paragraphs 65 - 69) and a plurality of power supply portions (Figure 4, Elements 241 – 261, 341 – 361, and 500. Paragraphs 70 - 73); and
wherein each of the power supply portions (Figure 4, Elements 241 – 261, 341 – 361, and 500. Paragraphs 70 - 73) is disposed close to (Seen in Figure 4) and electrically connected to (Seen in Figure 4) one of the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78).
Claims 2 – 5 and 8 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (U.S. PG Pub 2016/0035308) in view of Ura et al. (U.S. PG Pub 2015/0124006) in view of Bertolini et al. (U.S. PG Patent No. 10,680,521).
Regarding Claim 2, Ota in view of Ura et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 1 (See Above). Ota is silent with regards to wherein the share assembly is arranged in parallel with the switch assembly, and wherein the switch assembly is electrically connected to a positive electrode of the power supply assembly through a first node and is electrically connected to a negative electrode of the power supply assembly through a second node.
Bertolini et al. teach wherein the share assembly (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) is arranged in parallel (Seen in Figure 4) with the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50), and wherein the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50) is electrically connected to a positive electrode (Figure 4, Element Vin. Column 3, Lines 48 - 65) of the power supply assembly through a first node (Figure 4, Element 12. Column 3, Lines 48 - 65) and is electrically connected to (Seen in Figure 4) a negative electrode (Figure 4, Element ground. Column 3, Line 65 - Column 4, Line 16) of the power supply assembly through a second node (Figure 4, Element 18. Column 3, Line 48 - Column 4, Line 16).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 3, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 2 (See Above). Ota is silent with regards to wherein the share assembly comprises a plurality of shunt sub-assemblies arranged in parallel, and wherein at least one of the shunt sub-assemblies comprises any one of a resistance component and a switch component.
Bertolini et al. teach wherein the share assembly (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises a plurality of shunt sub-assemblies (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) arranged in parallel (Seen in Figure 4), and wherein at least one of the shunt sub-assemblies (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises any one of a resistance component and a switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 4, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 3 (See Above). Ota is silent with regards to wherein at least one of the shunt sub-assemblies comprises the switch component, and wherein the switch component and the switch assembly are closed simultaneously or alternately.
Bertolini et al. teach wherein at least one of the shunt sub-assemblies (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises the switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50), and wherein the switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) and the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50) are closed simultaneously or alternately (Column 7, Lines 9 - 25).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 5, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 4 (See Above). Ota is silent with regards to wherein the switch assembly comprises a first transistor, wherein the switch component comprises a second transistor, and wherein a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor.
Bertolini et al. teach wherein the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50) comprises a first transistor (Figure 4, Element 15-1. Column 6, Lines 30 - 50), wherein the switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises a second transistor (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50), and wherein a gate electrode of the first transistor (Figure 4, Element 15-1. Column 6, Lines 30 - 50) is electrically connected to (Seen in Figure 4, through digital controller (Element 33’).) a gate electrode of the second transistor (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 8, Ota in view of Ura et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 7 (See Above). Ota is silent with regards to wherein the share assembly is arranged in parallel with the switch assembly, and wherein the switch assembly is electrically connected to a positive electrode of the power supply assembly through a first node and is electrically connected to a negative electrode of the power supply assembly through a second node.
Bertolini et al. teach wherein the share assembly (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) is arranged in parallel (Seen in Figure 4) with the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50), and wherein the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50) is electrically connected to a positive electrode (Figure 4, Element Vin. Column 3, Lines 48 - 65) of the power supply assembly through a first node (Figure 4, Element 12. Column 3, Lines 48 - 65) and is electrically connected to (Seen in Figure 4) a negative electrode (Figure 4, Element ground. Column 3, Line 65 - Column 4, Line 16) of the power supply assembly through a second node (Figure 4, Element 18. Column 3, Line 48 - Column 4, Line 16).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 9, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 8 (See Above). Ota is silent with regards to wherein the share assembly comprises a plurality of shunt sub-assemblies arranged in parallel, and wherein at least one of the shunt sub-assemblies comprises any one of a resistance component and a switch component.
Bertolini et al. teach wherein the share assembly (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises a plurality of shunt sub-assemblies (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) arranged in parallel (Seen in Figure 4), and wherein at least one of the shunt sub-assemblies (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises any one of a resistance component and a switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 10, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 9 (See Above). Ota is silent with regards to wherein at least one of the shunt sub-assemblies comprises the switch component, and wherein the switch component and the switch assembly are closed simultaneously or alternately.
Bertolini et al. teach wherein at least one of the shunt sub-assemblies (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises the switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50), and wherein the switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) and the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50) are closed simultaneously or alternately (Column 7, Lines 9 - 25).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 11, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 10 (See Above). Ota is silent with regards to wherein the switch assembly comprises a first transistor, wherein the switch component comprises a second transistor, and wherein a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor.
Bertolini et al. teach wherein the switch assembly (Figure 4, Element 15-1. Column 6, Lines 30 - 50) comprises a first transistor (Figure 4, Element 15-1. Column 6, Lines 30 - 50), wherein the switch component (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50) comprises a second transistor (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50), and wherein a gate electrode of the first transistor (Figure 4, Element 15-1. Column 6, Lines 30 - 50) is electrically connected to (Seen in Figure 4, through digital controller (Element 33’).) a gate electrode of the second transistor (Figure 4, Elements 15-2 - 15-n. Column 6, Lines 30 - 50).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the shunting switch of Bertolini et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Bertolini et al. is to provide an output voltage that will avoid unwanted transients, as taught by Bertolini et al. (Column 7, Lines 55 – 59).
Regarding Claim 12, Ota in view of Ura et al. in view of Bertolini et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 8 (See Above). Ota teaches wherein a plurality of the first nodes (Figure 4, Element not labeled, but is the positive terminal between Elements 500 and 251 and 351. Paragraphs 70 and 74) of the plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) are electrically connected to each other through a first grid wire (Figure 4, Element not labeled, but is the positive terminal between Elements 500 and 251 and 351. Paragraphs 70 and 74), and wherein a plurality of the second nodes (Figure 4, Element not labeled, but is the negative terminal between Elements 500 and 251 and 351. Paragraphs 70 and 74) of the plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) are electrically connected to each other through a second grid wire (Figure 4, Element not labeled, but is the negative terminal between Elements 500 and 251 and 351. Paragraphs 70 and 74).
Claims 13 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (U.S. PG Pub 2016/0035308) in view of Ura et al. (U.S. PG Pub 2015/0124006) in view of Yokoyama et al. (U.S. PG Pub 2020/0043401).
Regarding Claim 13, Ota in view of Ura et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 6 (See Above), one of the plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) disposed adjacent to and electrically connected to the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78).
Ota is silent with regards to wherein each of the plurality of functional modules and one of the power supply module are positioned on different sides of the insulating substrate.
Yokoyama et al. teaches wherein each of the plurality of functional modules (Figure 1, Elements 5 and 7. Paragraphs 37 – 39) and one of the power supply module (Figure 1, Element 6. Paragraph 37) are positioned on different sides (Paragraph 43) of the insulating substrate (Figure 1, Element 1. Paragraph 37).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the dual sided substrate of Yokoyama et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Yokoyama et al. is to provide simplification in a wiring arrangement, as taught by Yokoyama et al. (Paragraph 25).
Regarding Claim 14, Ota in view of Ura et al. teach the semiconductor device (Figure 1. Paragraph 38) according to claim 6 (See Above), wherein the insulating substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.) comprises a first substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.) and a second substrate (Element second substrate. Paragraph 39); and
one of the plurality of power supply modules (Figure 4, Elements 241 - 261 and 500 and 341 - 361 and 500. Paragraphs 70 - 74) disposed adjacent to and electrically connected to the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78);
wherein the second substrate (Element second substrate. Paragraph 39) is positioned on a side of (Paragraph 39) the each of the plurality of functional modules (Figure 4, Elements 201 - 230 and 301 - 330. Paragraphs 65 - 69 and 74 - 78) or the one of the plurality of the power supply modules away from the first substrate (Figure 2, Element SUB1. Paragraph 48. The examiner notes that Figure 2 incorrectly labels SUB instead of SUB1.).
Ota is silent with regards to wherein each of the plurality of functional modules and one of the power supply module are positioned on different sides of the first substrate.
Yokoyama et al. teaches wherein each of the plurality of functional modules (Figure 1, Elements 5 and 7. Paragraphs 37 – 39) and one of the power supply module (Figure 1, Element 6. Paragraph 37) are positioned on different sides (Paragraph 43) of the first substrate (Figure 1, Element 1. Paragraph 37).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the dual sided substrate of Yokoyama et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Yokoyama et al. is to provide simplification in a wiring arrangement, as taught by Yokoyama et al. (Paragraph 25).
Claims 19 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (U.S. PG Pub 2016/0035308) in view of Ura et al. (U.S. PG Pub 2015/0124006) in view of Kawashima et al. (U.S. PG Pub 2020/0372868).
Regarding Claim 19, Ota in view of Ura et al. teach the electronic terminal according to claim 17 (See Above). Ota teaches wherein the display circuit portion (Figure 2, Element PX. Paragraph 51) comprises a third transistor (Figure 3, Element PSW. Paragraph 61), wherein the driving circuit (Figures 1 and 2, Elements IC1 and IC2. Paragraph 42) portion comprises a fourth transistor (Figure 4, Element Switch. Paragraph 107).
Ota is silent with regards to wherein the fourth transistor and the third transistor have a same material and are set in a same layer.
Kawashima et al. teach wherein the fourth transistor (Figure 9, Element 24. Paragraph 148) and the third transistor (Figure 9, Element 21. Paragraph 148) have a same material (Paragraph 150) and are set in a same layer (Seen in Figure 9).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the transistor layers of Kawashima et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Kawashima et al. is to simplify the manufacture process, as taught by Kawashima et al. (Paragraph 145).
Regarding Claim 20, Ota in view of Ura et al. teach the electronic terminal according to claim 17 (See Above). Ota is silent with regards to wherein the display circuit portion comprises a third transistor, wherein the driving circuit portion comprises a resistance component, and wherein the resistance component and the third transistor are made of a same material and set in a same layer.
Kawashima et al. teach wherein the display circuit portion (Figure 9, Element 14. Paragraph 147) comprises a third transistor (Figure 9, Element 21. Paragraph 148), wherein the driving circuit portion (Figures 8A and 9, Elements 13 and 15. Paragraph 147) comprises a resistance component (Figure 8A, Elements 57[1] – 57[t]. Paragraph 126), and wherein the resistance component (Figure 8A, Elements 57[1] – 57[t]. Paragraph 126) and the third transistor (Figure 9, Element 21. Paragraph 148) are made of a same material (Paragraphs 148 and 150. Kawashima et al. disclose that in the circuit 15 (which is also disclosed as the source driving circuit 13), the transistor 24 and the like are provided over the substrate 111. Kawashima et al. further discloses that that the source driving circuit 13 contains the resistor string 47.) and set in a same layer (Seen in Figure 9).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the liquid crystal display device of Ota and the single chip of Ura et al. with the transistor layers of Kawashima et al. The motivation to modify the teachings of Ota and Ura et al. with the teachings of Kawashima et al. is to simplify the manufacture process, as taught by Kawashima et al. (Paragraph 145).
Response to Arguments
All other arguments are considered moot in light of the above rejection necessitated by the applicant’s amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Quan (U.S. PG Pub 2008/0088415) discloses tuning an RFID reader where the tuning circuit contains parallel shunt transistors.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW B SCHNIREL whose telephone number is (571)270-7690. The examiner can normally be reached Monday - Friday, 10 - 6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.B.S/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625