DETAILED ACTION
This office action is in response to amendment filed 7/21/2026.
Claims 1, 5-10, 14-16, and 18-21 are pending. Claims 20-21 are new. Claims 2-4, 11-13, and 17 have been canceled. Claim 5 has been withdrawn. Claims 1, 10, and 18 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6-10, 14-16, and 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “the first drain electrode and the quantum well structure are electrically insulated from the second drain electrode by an insulating layer, and the first drain electrode and the second drain electrode are connected in parallel” renders the claim indefinite. It is unclear how are the first drain electrode and second drain electrode both electrically insulated and connected in parallel, as they appeared to be contradictory. This is further evidenced by Applicant’s argument filed on 7/21/2026 (Remark, page 8) alleging electrically connected structure is not considered to be electrically insulated. Therefore, if the first drain electrode and is electrically insulated from the second drain electrode, it is unclear how are they also connected in parallel.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-10, 14-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen US 2020/0119085 A1 (Chen’085).
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In re claim 1, as best understood, Chen’085 discloses (e.g. FIGs. 12A-12B) a semiconductor structure comprising:
a substrate 10;
a heterojunction structure 120 (¶ 105) disposed on the substrate 10, wherein the heterojunction structure 120 comprises a source region (a region including source electrode 132), a drain region (a region including drain electrode 134), and a gate region (a region including gate electrode 136) disposed between the source region (region of 132) and the drain region (region of 134), and wherein the heterojunction structure 120 comprises a channel layer 124 and a potential barrier layer 126 (¶ 105);
a quantum well structure 20 disposed on the potential barrier layer 126, wherein the quantum well structure 20 (including a select portion of located in the drain region, ¶ 43, see FIG. 12A annotated above) is disposed on the drain region of the potential barrier layer 126, and the quantum well structure 20 (FIG. 12B) comprises an N-type semiconductor layer 804 (¶ 28), a first P-type semiconductor layer 1140,1150,1160 (¶ 50-51), and a quantum well layer 1110,1120,1130 disposed between the N-type semiconductor layer 804 and the first P-type semiconductor layer 1140,1150,1160, and wherein the first P-type semiconductor layer 1140,1150,1160 comprises a hole passivation layer away from the quantum well layer 1110,1120,1130 (no specific “passivation layer” is claimed that would structurally distinguish over layer 1160 that provides physical protection to underlying hole generating layers 1140,1150; “passivation layer” in understood to mean a protective coating as commonly known in the art);
a first drain electrode 30 disposed on the quantum well structure (no specific “drain electrode” claimed that would structurally distinguish over metal 30 that is connected to the drain region of the HEMT), wherein the first drain electrode 30 is in ohmic contact with the quantum well structure (30 provide ohmic contact to p-doped side (see FIG. 12B) of the quantum well structure corresponding to the portion annotated in FIG. 12A above); and
a second drain electrode 134 disposed in the drain region, wherein the second drain electrode 134 is in ohmic contact with the heterojunction structure 120 (¶ 107);
“wherein the first drain electrode 30 and the quantum well structure (select portion of 20, see annotated in FIG. 12A above) are electrically insulated from the second drain electrode 134 by an insulating layer (isolation layer 140 (¶ 108) in FIG. 12A provides vertical electrical insulation between 30 and 134; or dielectric 161,170 (¶ 116) in FIG. 12A provides lateral electrical insulation between 30 and 134; or dielectric layer 42 (¶ 58) shown in FIG. 1D provides vertical electrical insulation between 30 and 134), and the first drain electrode 30 and the second drain electrode 134 are connected in parallel (30 and 134 are structurally physically connected and are in parallel)”.
The phrase “connected in parallel” is as best understood to mean a connection between the electrodes with the electrodes being structurally parallel, wherein the electrodes are also “electrically insulated” as recited in the claim. Chen’085 teaches electrodes 30 and 134 are physically connected and they are structurally arranged as parallel layers. Electrodes 30 and 134 are also electrically insulated by interposing dielectric layers 140,161,170,42.
In re claim 6, Chen’085 discloses (e.g. FIG. 12A) wherein a material combination of the channel layer 124 and the potential barrier layer 126 comprises (¶ 105): GaN and AIN, GaN and InN, GaN and InAlGaN, GaAs and AlGaAs, GaN and InAIN, or InN and InAIN. Chen’085 teaches (¶ 105) the channel layer 124 can include GaN or InGaAs, and the barrier layer 126 can include AlGaN, InAlAs or AlGaAs. As such, Chen’085 teaches the material combination can be, e.g. GaN and AlGaN (which comprises GaN and AlN as claimed) or InGaAs and AlGaAs (which comprises GaAs and AlGaAs as claimed).
In re claim 7, Chen’085 discloses (e.g. FIGs. 12A & 12B) wherein the gate region (region of the device including gate electrode 136, see annotated in FIG. 12A above) is provided with a dielectric layer 140,170,190 (dielectric layer provided in the “gate region”, ¶ 116). Alternatively, dielectric layer may be 42 (see FIG. 1D) as part of structure 20 in the “gate region”.
In re claim 8, Chen’085 discloses (e.g. FIG. 12B) wherein the quantum well layer 1110,1120,1130 is a single quantum well layer or a multiple quantum well layer.
In re claim 9, Chen’085 discloses (e.g. FIG. 12B) wherein a material of the first P-type semiconductor layer 1140,1150,1160 (¶ 49-51) comprises at least one of GaN, AlGaN, InGaN, or AlInGaN.
In re claim 10, Chen’085 discloses (e.g. FIG. 12A, see annotated above) wherein the source region is provided with a source electrode 132 and the gate region is provided with a gate electrode 136; the source electrode 132 is in ohmic contact with the heterojunction structure 120 (¶ 107), and the gate electrode 136 is in Schottky contact with the heterojunction structure 120 (¶ 105).
In re claim 14, Chen’085 discloses (e.g. FIG. 1D and 12A) wherein a material of the dielectric layer 42 (provided in the “gate region”) comprises at least one of silicon dioxide or silicon nitride (¶ 58).
In re claim 15, Chen’085 discloses (e.g. FIG. 12B) wherein a material of the N-type semiconductor layer 804 (¶ 28) comprises at least one of GaN, AIGaN, InGaN, or AlInGaN.
In re claim 16, Chen’085 discloses (e.g. FIGs. 12A & 12B) wherein the N-type semiconductor layer 804 is close to the heterojunction structure 120 and the first P-type semiconductor layer 1140,1150,1160 is away from the heterojunction structure 120.
In re claim 18, Chen’085 discloses (e.g. FIG. 1D) wherein a material of the insulating layer 42 comprises at least one of silicon dioxide or silicon nitride (¶ 58).
In re claim 19, Chen’085 discloses (e.g. FIGs. 12A-12B) wherein the gate region is further provided with a second P-type semiconductor layer 1140,1150, and the second P-type semiconductor layer 1140,1150 is disposed on the dielectric layer 140. Alternatively, Chen’085 discloses (e.g. FIG. 1D) the second P-type semiconductor layer (lower portion of 1260) is disposed on the dielectric layer 42.
In re claim 20, Chen’085 discloses (e.g. FIG. 12A) wherein the insulating layer 161+170 (¶ 116) covers a sidewall of the quantum well structure 20 (sidewall in via 172 opening covered by 161) facing the second drain electrode 134 (134 to the right side of via 172’s left sidewall) and a part of an upper surface of the quantum well structure 20 (top of 20 covered by 170), and is in contact with the first drain electrode 30 (170 contacting 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chen’085 as applied to claim 7 above, and further in view of Huang et al. US 2016/0190384 A1 (Huang).
In re claim 21, Chen’085 discloses the claimed invention including a HEMT including the source electrode 132, second drain electrode 134, and the gate electrode 136. Chen’085 does not explicitly disclose a dielectric layer located below the gate electrode 136 and between the source electrode 132 and the second drain electrode 134.
However, Huang discloses (e.g. FIGs. 1 & 3) a HEMT comprising a source electrode 306, a drain electrode 308, and a gate electrode 305, wherein the gate electrode 305 may be an insulated gate with a gate dielectric layer 309 below the gate electrode 305 and between the source electrode 306 and the second drain electrode 308 such that the 2DEG channel can be controlled by the electric field generated by the insulated gate (¶ 22-23).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a gate dielectric layer below Chen’085’s the gate electrode 136 and between the source electrode 132 and the second drain electrode 134 to form an insulated gate for controlling the 2DEG channel as taught by Huang.
Response to Arguments
Applicant's arguments filed 7/21/2026 have been fully considered but they are not persuasive.
Regarding Chen’085, Applicant argues metal interconnect structures 171,173,192 form an electrically conductive path that connects electrode 30 and electrode 134, thus, the electrodes 30 is not electrically insulated from the drain electrode 134 (Remark, page 8).
This is not persuasive. Claim 1 recites the first drain electrode and the second drain electrode are both “electrically insulated” and “connected in parallel”. As best understood, the electrodes are “electrically insulated” by some intervening insulating material, but does not preclude additional connection made through the insulating material that connect the electrodes.
Chen’085 teaches the first drain electrode 30 is electrically insulated from the second drain electrode 134 by an insulating layer, which can be the isolation layer 140 (¶ 108) in FIG. 12A that provides vertical electrical insulation between 30 and 134, or dielectric 161,170 (¶ 116) in FIG. 12A that provides lateral electrical insulation between 30 and 134, or dielectric layer 42 (¶ 58) shown in FIG. 1D that provides vertical electrical insulation between 30 and 134). The insulating layer 140,161,170,42 either laterally or vertically interposes the electrodes 30 and 134, and provides “electrical insulation” between the electrodes 30 and 134.
The phrase “connected in parallel” is as best understood to mean a connection between the electrodes with the electrodes being structurally parallel. Chen’085 teaches electrodes 30 and 134 are physically connected and they are structurally arranged as parallel layers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
