Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 13 are amended
Claim 3 is cancelled
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda (US 20210329795 A1) in view of Kim (US 20190311830 A1) and further in view of Alberto (US 20180233967 A1).
Regarding Claim 1:
Ueda teaches that a coil device comprising at least one printed wiring board,
the at least one printed wiring board including: a base film (2, Fig. 2; para 0040-0061) that includes a first main surface (upper surface of 2 ) and a second main surface (lower surface of 2 ); and a first conductive pattern (3, Fig. 1), constituted by a first wiring section (i.e. winding part of 3 in Fig. 1) spirally wound on the first main surface, wherein
an average distance (d1, Fig. 3) between the first wiring sections adjacent to each other is greater than or equal to 3 µm and less than or equal to 15 µm, (see para 0076-0077) and
the first wiring section has a first end (not labeled; i.e. bottom end part of 3 in Fig. 1), a second end (not labeled; i.e. center end part of 3 connected to hole 7 in Fig. 1), and a length (i.e. length of coil 3 from first end to second end part) extending from the first end to the second end,
Ueda does not teach that the first wiring section includes a seed layer disposed on the first main surface, a first electrolytic plating layer disposed on the seed layer, and a second electrolytic plating layer covering the seed layer and the first electrolytic plating layer.
However, Kim teaches that the first wiring section includes a seed layer (25b. Fig. 6F; para 0056) disposed on the first main surface (20), a first electrolytic plating layer (61) disposed on the seed layer, and a second electrolytic plating layer covering (62) the seed layer and the first electrolytic plating layer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the first wiring section includes a seed layer disposed on the first main surface, a first electrolytic plating layer disposed on the seed layer, and a second electrolytic plating layer covering the seed layer and the first electrolytic plating layer to provide a coil component exhibiting low direct current (DC) resistance Rdc by increasing cross-sectional areas of coil parts (para 0005).
The modified Ueda does not teach that the first wiring section has a length greater than or equal to 150 mm and less than or equal to 1000 mm.
However, such dimensions are well-known as taught by Alberto in para 0124 that the transmitting antenna 18 was configured having an inductor coil with a length of 170 mm and a width of 100 mm and 6 turns. In this case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). MPEP 2144.05.I
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the first wiring section has a length greater than or equal to 150 mm and less than or equal to 1000 mm as claimed to meet design requirements for certain application.
Regarding Claim 2:
As applied to claim 1, the modified Ueda teaches that the at least one printed wiring board further includes a second conductive pattern (4, Fig. 2) constituted by a second wiring (i.e. winding part of 4 in Fig. 2) section spirally wound on the second main surface, and the second wiring section has a length greater than or equal to 150 mm and less than or equal to 1000 mm (as explained in claim 1 analysis in light of MPEP 2144.05.I)
Regarding Claim 5:
As applied to claim 3, the modified Ueda teaches that the seed layer is a single layer formed (construed from Fig. 4A) of a material same as the material of the first electrolytic plating layer except the seed layer formed of a material same as the material of the first electrolytic plating layer.
Although it is not explicitly stated that the seed layer formed of a material same as the material of the first electrolytic plating layer, this appears to be the case since it is not taught that the seed layer formed of a material different as the material of the first electrolytic plating layer.
Alternatively, it would have been obvious that the seed layer formed of a material same as the material of the first electrolytic plating layer to simplify design, reduce manufacturing costs and provide a desired magnetic property.
Regarding Claim 6:
As applied to claim 5, the modified Ueda teaches that the seed layer is a single layer formed of a material same as the material of the first electrolytic plating layer (see Ueda’s para 0088).
Regarding Claim 7:
As applied to claim 1, the modified Ueda teaches that a height of the first wiring (h, Fig. 3; para 0077-0078) and a width of the first wiring section than or equal to 5 except a value obtained by dividing a height of the first wiring section by a width of the first wiring section is greater than or equal to 0.15 and less than or equal to 5.
It would have been obvious before the effective filing date of the claimed invention to a person having a value obtained by dividing a height of the first wiring section by a width of the first wiring section is greater than or equal to 0.15 and less than or equal to 5, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable range involves only routine skill in the art. In re Aller, 105 USPQ 233. MPEP 2144.05 (II-A).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have a value obtained by dividing a height of the first wiring section by a width of the first wiring section is greater than or equal to 0.15 and less than or equal to 5 as claimed to meet design requirements for certain application.
Regarding Claim 8:
As applied to claim 1, the modified Ueda teaches that in plain view, the first conductive pattern has a width less than or equal to 10 mm and a length less than or equal to 15 mm as explained in claim 7 analysis in light of MPEP 2144.05 (II-A).
Regarding Claim 9:
As applied to claim 1, the modified Ueda teaches that a value obtained by dividing a height of the first wiring section by an average distance between the first wiring sections adjacent to each other is greater than or equal to 2 and less than or equal to 25 as explained in claim 7 analysis in light of MPEP 2144.05 (II-A).
Regarding Claim 10:
As applied to claim 1, the modified Ueda teaches that the at least one printed wiring board includes a plurality of printed wiring boards (i.e. layer 5 or 6 in Ueda’s Fig. 2) disposed to be overlapped in a thickness direction (i.e. vertical direction in Fig. 2) of the base film.
Regarding Claim 11:
As applied to claim 10, the modified Ueda teaches that the at least one of the plurality of printed wiring boards further includes a second conductive pattern (4, Fig. 2) constituted by a second wiring section (i.e. winding part of 4 in Fig. 2) spirally wound on the second main surface, and the second wiring section has a length greater than or equal to 150 mm and less than or equal to 1000 mm (as explained in claim 1 analysis in light of MPEP 2144.05.I)
Regarding Claim 12:
As applied to claim 1, the modified Ueda teaches that the at least one printed wiring board includes a plurality of printed wiring boards (i.e. layer 5 or 6 in Ueda’s Fig. 2)
disposed to be overlapped in a thickness direction (i.e. vertical direction in Fig. 2) of the base film,
each of the plurality of printed wiring boards further includes a second conductive pattern (4, Ueda’s Fig. 2) constituted by a second wiring section (i.e. winding part of 4 in Fig. 2) that is wound on the second main surface and that is electrically connected to the first wiring section,
an average distance (d1, Fig. 3) between the second wiring sections adjacent to each other is greater than or equal to 3 µm and less than or equal to 15 µm, (see para 0076-0077)
the first wiring section of a first printed wiring board that is one of the plurality of
printed wiring boards is electrically connected (i.e. connected through hole 7; see para 0067) to the second wiring section of a second printed wiring board that is another one of the plurality of printed wiring boards adjacent to the first printed wiring board in the thickness direction of the base film, and
a sum of the length of the first wiring section and the length of the second wiring
section in the plurality of printed wiring boards is greater than or equal to 300 mm and less than or equal to 2000 mm (as explained in claim 1 analysis in light of MPEP 2144.05.I)
Regarding Claim 13:
Ueda teaches that a coil device comprising at least one printed wiring board,
Wherein
each of the plurality printed wiring board including: a base film (2, Fig. 2; para 0040-0061) that has a first main surface (upper surface of 2 ) and a second main surface (lower surface of 2 ); and a first conductive pattern (3, Fig. 1), that is constituted by a first wiring section (i.e. winding part of 3 in Fig. 1) wound on the first main surface, and a second conductive pattern (4, Ueda’s Fig. 2) constituted by a second wiring section (i.e. winding part of 4 in Fig. 2) spirally wound on the second main surface and that is electrically connected to the first wiring section,
the plurality of printed wiring boards (i.e. layer 5 or 6 in Ueda’s Fig. 2) is disposed to be overlapped in a thickness direction (i.e. vertical direction in Fig. 2) of the base film,
the first wiring section of a first printed wiring board (5) that is one of the plurality of printed wiring boards is electrically connected (i.e. connected through hole 7; see para 0067) to the second wiring section of another, second one of the plurality of printed wiring boards adjacent to the first printed wiring board in the thickness direction of the base film,
an average distance (d1, Fig. 3) between the first wiring sections adjacent to each other and an average distance between the second wiring sections adjacent to each other are greater than or equal to 3 µm and less than or equal to 15 µm, (see para 0076-0077),
the first wiring section has a first end (not labeled; i.e. bottom end part of 3 in Fig. 1), a second end (not labeled; i.e. center end part of 3 connected to hole 7 in Fig. 1), and a first length (i.e. length of coil 3 from first end to second end part) extending from the first end to the second end, the second wiring section has a third end (not shown; i.e. end part of 4 ), a fourth end (not shown; i.e. other end part of 4 connected to hole 7), and a second length (i.e. length of coil 4 from first end to second end part) extending from the first end to the second end,
and a sum of the length of the first wiring section and the length of the second wiring section in the plurality of printed wiring boards is greater than or equal to 300 mm and less than or equal to 2000 mm (as explained in claim 1 analysis in light of MPEP 2144.05.I).
Ueda does not teach that the first wiring section includes a seed layer disposed on the first main surface, a first electrolytic plating layer disposed on the seed layer, and a second electrolytic plating layer covering the seed layer and the first electrolytic plating layer.
However, Kim teaches that the first wiring section includes a seed layer (25b. Fig. 6F; para 0056) disposed on the first main surface (20), a first electrolytic plating layer (61) disposed on the seed layer, and a second electrolytic plating layer covering (62) the seed layer and the first electrolytic plating layer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the first wiring section includes a seed layer disposed on the first main surface, a first electrolytic plating layer disposed on the seed layer, and a second electrolytic plating layer covering the seed layer and the first electrolytic plating layer to provide a coil component exhibiting low direct current (DC) resistance Rdc by increasing cross-sectional areas of coil parts (para 0005).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ueda in view of Kim in view of Alberto and further in view of Hyung (US 20240006118 A1).
Regarding Claim 4:
As applied to claim 1, the modified Ueda teaches the seed layer, the electroless plating layer is formed of a material same as the material of the first electrolytic plating layer as explained 5 analysis above.
The modified Ueda does not teach that the seed layer includes a sputtered layer disposed on the first main surface and an electroless plating layer disposed on the sputtered layer, the sputtered layer is formed of a material different from a material of the first electrolytic plating layer.
However, Hyung taught in para 0062 that each of the coil patterns 311 and 312 and the via 320 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), chromium (Cr), molybdenum (Mo) or alloys thereof, but a material thereof is not limited thereto. As a non-limiting example, when the first conductive layers 311 a and 312 a are formed by sputtering and the second conductive layers 311 b and 312 b are formed by electroplating, the first conductive layers 311 a and 312 a may include at least one of molybdenum(Mo), chromium (Cr), and titanium (Ti), and the second conductive layers 311 b and 312 b may include copper (Cu).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the seed layer includes a sputtered layer disposed on the first main surface and an electroless plating layer disposed on the sputtered layer, the sputtered layer is formed of a material different from a material of the first electrolytic plating layer to provide a coil component with improved component characteristics in a high frequency band (para 0007).
Response to Arguments
Applicant's arguments have been fully considered. However, upon further consideration, a new ground(s) of rejection is made in view of different interpretation of the previously applied reference, and/or newly found prior art reference(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. A list of pertinent prior art is attached in form 892.
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/KAZI HOSSAIN/
Examiner, Art Unit 2837
/SHAWKI S ISMAIL/Supervisory Patent Examiner, Art Unit 2837