DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-7, 9-13, 15, 16 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 2023/0079023) hereinafter “Lee”.
Regarding claim 1, Fig. 12 of Lee teaches an array substrate having a display area (Item DA1) and a peripheral area (Item PA), the array substrate comprising: a substrate (Item 100); a first common voltage line (Item 13) disposed on a first side of the substrate (Item 100), the first common voltage line (Item 13) being located in the peripheral area (Item PA) and arranged along at least part of a boundary of the display area (Item DA1); and a voltage signal introduction structure (Item CLP) disposed on the first side of the substrate (Item 100), the voltage signal introduction structure (Item CLP) being electrically connected to at least one position except two ends of the first common voltage line (Where Items CLV2 and CLH3 connect to Item 13 in areas other than the end of Item 13), so as to input a voltage signal to the first common voltage line (Paragraph 0196), a plurality of bonding pads (pads that are a part of pad unit PAD) disposed on the first side (Bottom) of the substrate, the two ends of the first common voltage line (Item 13) being electrically connected to respective bonding pads, where the two ends of the first common voltage line (Item 13) are located on a same side of the display area (Bottom), and the two ends of the first common voltage line (Item 13) are both signal input terminals (Where the ends terminate in the pad region); the first common voltage line (Item 13) includes a first portion (Horizontal portion of Item 13 on the top of the page), and the first portion is located on a side of the display area away from the two ends; and the voltage signal introduction structure (Item CLP) is electrically connected to at least one position of the first portion (Where Items CLV2 contact the first portion of Item 13), the voltage signal introduction structure (Item CLP) includes: at least one first auxiliary voltage line (Item CLV2) passing through the display area (Item DA1), where in the at least one first auxiliary voltage line (Item CLV2), a first end of a first auxiliary voltage line is electrically connected to the first portion (Horizontal portion of Item 13 at the top of the page), and a second end of the first auxiliary voltage line is located on the same side (Bottom) of the display area as the two ends of the first common voltage line; and a second conductive connection portion (Item CNT4) located between the two ends of the first common voltage line (Item 13), the second end of the first auxiliary voltage line being electrically connected to the second conductive connection portion; and an end of the second conductive connection portion (Item CNT4) being connected (electrically) to a bonding pad of the plurality of bonding pads.
Regarding claim 4, Fig. 12 of Lee further teaches where the voltage signal introduction structure (Item CLP) further includes: a first conductive connection portion (Portion of Item CLV2 between Items 13 and DA1) located between the first portion (Horizontal portion of Item 13 at the top of the page) and the display area (Item DA1), wherein the first end of the first auxiliary voltage line (Portion of Item CLV2 at the top of DA1) is electrically connected to the first portion through the first conductive connection portion (Where all of Item CLV2 and 13 are electrically connected to each other).
Regarding claim 5, Fig. 12 of Lee further teaches where the first conductive connection portion (Portion of Item CLV2 between Items 13 and DA1) includes: a first connection line (Item CNT3), the first connection line and the first portion being arranged at an interval; and a plurality of second connection lines (Top two CLH3) each connected (electrically) between the first connection line (Portion of Item CLV2 between Items 13 and DA1) and the first portion (Horizontal portion of Item 13 at the top of the page), wherein the first end of the first auxiliary voltage line is connected (electrically) to the first connection line.
Regarding claim 6, Fig. 12 of Lee further teaches where the plurality of second connection lines (Top two CLH3) are arranged at equal intervals along an extension direction as the first portion (Where each of the second connection lines extend across the entirety of the display region such that the second connection line is equal at intervals along an extension direction as the first portion).
Regarding claim 7, Fig. 12 of Lee further teaches where the voltage signal introduction structure (Item CLP) further includes: at least one second auxiliary voltage line (Top Item CLH3) extending in a same direction (Left to right) as the first portion (Horizontal portion of Item 13 at the top of the page), wherein the first common voltage line (Item 13) further includes a second portion (Left vertical portion of Item 13) and a third portion (Right vertical portion of Item 13) that are disposed opposite to each other; in the at least one second auxiliary voltage line (Top Item CLH3), a first end of a second auxiliary voltage line is connected to a second connection line in the plurality of second connection lines, and a second end of the second auxiliary voltage line is connected to the second portion or the third portion.
Regarding claim 9, Fig. 12 of Lee further teaches where the second conductive connection portion (Item CNT4) includes: a connection segment located on a side of the display area away from the first portion; and a plurality of voltage signal input segments each connected to the connection segment and each extending to a side away from the display area (Item DA1), wherein the second end of the first auxiliary voltage line is connected to the connection segment.
Regarding claim 10, Fig. 12 of Lee further teaches where the voltage signal introduction structure (Item CLP) further includes: at least one third auxiliary voltage line (Item CLH3) passing through the display area (Item DA1) and crossing the first auxiliary voltage line (Item CLV2), wherein the first common voltage line (Item 13) further includes a second portion (Left vertical portion of Item 13) and a third portion (Right vertical portion of Item 13) that are disposed opposite to each other; in the at least one third auxiliary voltage line (Item CLH3), a first end of a third auxiliary voltage line is connected to the second portion, and a second end of the third auxiliary voltage line is connected to the third portion.
Under an alternative interpretation of Lee, Regarding claim 10, Fig. 12 of Lee further teaches where the voltage signal introduction structure (Item CLP) further includes: at least one third auxiliary voltage line (Combination of Items CLH3 and CNT4) passing through the display area (Item DA1) and crossing the first auxiliary voltage line (Item CLV2), wherein the first common voltage line (Item 13) further includes a second portion (Left vertical portion of Item 13) and a third portion (Right vertical portion of Item 13) that are disposed opposite to each other; in the at least one third auxiliary voltage line (Combination of Items CLH3 and CNT4), a first end of a third auxiliary voltage line is connected to the second portion, and a second end of the third auxiliary voltage line is connected to the third portion.
Regarding claim 11, Fig. 12 of Lee further teaches where the third auxiliary voltage line (Item CLH3) and the first auxiliary voltage line (Item CLV2) are electrically connected at a cross position (Paragraph 0176).
Regarding claim 12, Fig. 12 of Lee further teaches where the first auxiliary voltage line (Item CLV2) and the third auxiliary voltage line (Item CLH3) are disposed in a different layer from the first common voltage line (Item 13).
Under the alternative interpretation of Lee, Regarding claim 13, Fig. 12 of Lee further teaches where the at least one third auxiliary voltage line (Combination of Items CLH3 and CNT4) includes a plurality of third auxiliary voltage lines, part of the third auxiliary voltage lines (Item CNT4) are disposed in the same layer (Where the portion of Item CNT4 that contacts Item 13 is in the same layer) as the first common voltage line (Item 13), and remaining part of the third auxiliary voltage lines (Item CLH3) are disposed in a different layer from the first common voltage line (Item 13).
Regarding claim 15, Fig. 12 of Lee further teaches where the display area (Item DA1) includes a plurality of sub-pixel regions (Items PX1, PX2 and PX3, respectively) arranged in a plurality of rows and a plurality of columns, wherein the first auxiliary voltage line (Item CLV2) and the third auxiliary voltage line (Item CLH3) each pass through the display area (Item DA1) through gaps between sub-pixel regions in the plurality of sub-pixel regions.
Regarding claim 16, Figs. 9 and 12 of Lee further teaches where the at least one first auxiliary voltage line (Item CLV2) includes a plurality of first auxiliary voltage lines (Item CLV2), the plurality of first auxiliary voltage lines are arranged at equal intervals along a row (Left to right across the page) direction of the plurality of sub-pixel regions.
Regarding claim 19, Fig. 12 of Lee further teaches a display apparatus, comprising: the array substrate according to claim 1 (See the rejection of claim 1 above; For brevity the rejection of claim 1 will not be repeated here).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2023/0079023) hereinafter “Lee” in view of Ren et al. (US 2019/0096924) hereinafter “Ren”.
Regarding claim 17, Fig. 12 of Lee teaches an array substrate having a display area (Item DA1) and a peripheral area (Item PA), the array substrate comprising: a substrate (Item 100); a first common voltage line (Item 13) disposed on a first side of the substrate (Item 100), the first common voltage line (Item 13) being located in the peripheral area (Item PA) and arranged along at least part of a boundary of the display area (Item DA1); and a voltage signal introduction structure (Item CLP) disposed on the first side of the substrate (Item 100), the voltage signal introduction structure (Item CLP) being electrically connected to at least one position except two ends of the first common voltage line (Where Items CLV2 and CLH3 connect to Item 13 in areas other than the end of Item 13), so as to input a voltage signal to the first common voltage line (Paragraph 0196), where the first common voltage line (Item 13) includes a first portion (Horizontal portion of Item 13 on top of the page), and the first portion is located on a side of the display area away from the two ends.
Lee does not teach where the voltage signal introduction structure includes: at least one connection block located on a side of the first portion away from the display area, and connected to the first portion, a connection block in the at least one connection block being configured to be connected to an external voltage signal source.
Ren teaches where a common electrode line pattern (Item 14) includes a plurality of common electrode lines (Item 141) and a plurality of common electrode connection blocks (Item 142).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the voltage signal introduction structure includes: at least one connection block located on a side of the first portion away from the display area, and connected to the first portion, a connection block in the at least one connection block being configured to be connected to an external voltage signal source because this results in voltage uniformity throughout the common electrode line pattern (Ren Paragraph 0045).
Regarding claim 18, Lee teaches all of the elements of the claimed invention as stated above except where the at least one connection block includes a plurality of connection blocks, the connection blocks are connected to different positions of the first portion, and the connection blocks are arranged at equal intervals along an extension direction of the first portion.
Ren teaches where a common electrode line pattern (Item 14) includes a plurality of common electrode lines (Item 141) and a plurality of common electrode connection blocks (Item 142).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the at least one connection block include a plurality of connection blocks, the connection blocks are connected to different positions of the first portion, and the connection blocks are arranged at equal intervals along an extension direction of the first portion because this results in voltage uniformity throughout the common electrode line pattern (Ren Paragraph 0045).
Allowable Subject Matter
Claim 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 14, the prior art of record does not teach, suggest or motivate one having ordinary skill in the art to have the device further comprising: a circuit structure layer located on the first side of the substrate, the circuit structure layer including at least one conductive layer; an anode layer located on a side of the circuit structure layer away from the substrate; and a light-shielding metal layer located between the circuit structure layer and the substrate, wherein the first common voltage line is disposed in a same layer as any one of the at least one conductive layer and the anode layer; and a first auxiliary voltage line in the at least one first auxiliary voltage line or a third auxiliary voltage line in the at least one third auxiliary voltage line disposed in a different layer from the first common voltage line is disposed in a same layer as the light-shielding metal layer.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive.
Specifically, with regard to claim 1, the Applicant argues that the structure identified in Lee by the Examiner as being the second conductive connection portion (Item CNT4) are located on the left and right vertical portions of the common voltage line (Item 13) and thus is not located between two ends of the common voltage line. The Examiner disagrees. Being between two ends of the first common voltage line can be understood as being two possible scenarios a) where a structure or part of a structure is horizontally between the ends of the first common voltage line (as this would place a structure along an imaginary line connecting two respective ends of the first common voltage line) or b) where a structure or part of a structure is located along the first common voltage line (as the first common voltage line is between its two respective ends). In the case of Lee the respective portions of Item CNT4 in Lee lie at two respective points along the first common voltage line (Item 13). Thus, at least a portion of the structure CNT4, lies between two ends of the first common voltage line. The Applicant points out that Item CNT4 is away from the bottom (first) side of the display but the claim does not require that the second conductive connection portion have any specific orientation to the first side. To overcome the current rejection the Examiner suggests the Applicant additionally claim that the second conductive connection portion is present at the same side as the ends of the first common voltage line (i.e. first side of the display).
The Applicant next argues, with regard to claim 1, that Item CNT4 is only electrically connected to the common voltage line but is not directly electrically connected to the pad unit PAD. The Examiner agrees but disagrees with the conclusion that the Lee reference does not read on the claim language as the claim language does not require a direct electrical or physical connection between the second conductive connection portion and a bonding pad but instead merely requires an electrical connection between the structures, which the Lee reference teaches as an indirect electrical connection.
The Applicant next argues, with regard to claim 17, that the transparent conductive pattern (Item 12) of Ren has display functionality and thus concludes that the connection block of Ren does not satisfy the claim language. The Examiner disagrees. The teaching in Ren discusses the connection block (Item 142) in association with a gate line (Item 13) and common electrode pattern (Item 14). The Examiner is unclear how any possible display functionality of Item 12 would impact the applicability of the teaching of the function of the connection block in Ren to Lee. Ren teaches where connection blocks are placed on two sides of a gate line (Paragraph 0052). This teaching in Ren does not limit the placement of connection blocks to a being on either side of a gate line in a display area but gives motivation as to why one having ordinary skill in the art would place connection blocks on either side of the gate line in any portion of the display. As the gate lines in Lee are present in peripheral and display portions, the teaching in Ren renders a placement of a connection block located in a peripheral portion obvious. Therefore, the Examiner does not find the Applicant’s argument persuasive and continues to rely on a combination of Lee and Ren to reject claim 17.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891