DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/07/2026 has been entered.
Response to Amendment
Examiner acknowledges the amendments made to claim 1. No new claims have been added.
Response to Arguments
Applicant's arguments filed 04/07/2026 have been fully considered but they are not persuasive.
Regarding the argument that there is no necessity to intentionally adopt the ridge configuration of Kaneko as opposed to a different prior art configuration (Applicant cites WO 2018/08396 which is not relied upon for the rejection of claim 1), Examiner respectfully disagrees. As disclosed in the rejection of claim 1 below, the reference of Kankeo discloses that the specific structure shown in Kaneko produces a desired result of high productivity of infrared emission (Kaneko Para. [0054]) and this specific motivation to adopt the single ridge structure of Kaneko.
Regarding the argument that “there is no motivation to apply Inoue to a configuration where the problem Inoue intends to solve does not exist”, Examiner notes that Inoue discloses a problem of stress between a submount substrate and semiconductor laser influencing the laser construction and use (Inoue Para. [0010]) that is solved by the material properties and method of creating the electrode structure as disclosed in Inoue Para. [0011]. Inoue discloses in Para. [0017] the potential issues of bonding methods that arise if there are separation grooves, then a problem of voids can arise. Therefore, one would assume that a ridge structure without separation grooves (as shown in Kaneko for example) would further help solve the problems of voids being formed during a bonding step.
Applicant notes that the inventor of the present application considered that more efficient heat dissipation is necessary for improving reliability and conceived of adopting a configuration in which a thick metal plating layer is provided to cover the ridge portion from both sides to contribute to heat dissipation,
In response to applicant's argument that “Even if any of the cited references were known to a person skilled in the art, it is not considered that the present invention, which breaks through conventional common sense to enable polishing, could have been easily conceived” in regard to the improved heat dissipation of the claimed application, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Examiner notes that Fig. 2 of Kaneko discloses the amended limitations of “layers constituting a semiconductor laminate [30,40,50,60 and 72 Fig. 2] (Para. [0022]) are absent on the remaining portion of the lower cladding layer [32 Fig. 1] (Para. [0022]) between a side surface of the ridge portion [side of mesa Fig. 2] and a side surface of the semiconductor substrate [side of 20 Fig. 2] (Para. [0022])” as recited in the rejection of claim 1 below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue et al. (hereinafter Inoue) (US 20080291960 A1) in view of Kaneko et al. (hereinafter Kaneko) (US 20200274331 A1) and further in view of Wakisaka et al. (hereinafter Wakisaka) (US 20030151059 A1)
Regarding claim 1, Inoue discloses,
A method for manufacturing a laser element [Fig. 1] including a semiconductor substrate [2 Fig. 1], a semiconductor laminate [3 Fig. 1] (Para. [0127]) formed on the semiconductor substrate [2 Fig. 1] to include an active layer [5 Fig. 1] (Para. [0127]), a lower cladding layer [4 Fig. 1] (Para. [0127]) disposed on the semiconductor substrate side with respect to the active layer [4 below 5 Fig. 1] (Para. [0127]), and an upper cladding layer [6 Fig. 1] (Para. [0127]) disposed on a side opposite to the semiconductor substrate [2 Fig. 1] (Para. [0127]) with respect to the active layer [5 Fig. 1] (Para. [0127]), a first electrode [21 Fig. 1] (Para. [0134]) formed on a surface on an opposite side [above semiconductor laminate 3 Fig. 1] of the semiconductor laminate [3 Fig. 1] from the semiconductor substrate [2 Fig. 1], and a second electrode [18 Fig. 1] (Para. [0133]) formed on a surface on an opposite side [bottom of substrate 2 Fig. 1] of the semiconductor substrate [2 Fig. 1] from the semiconductor laminate [3 Fig. 1], the method comprising:
a first step [Fig. 3A] of preparing a semiconductor wafer [30 Fig. 3A] including a plurality of portions each of which becomes the semiconductor substrate [Fig. 3A wafer 30 forms plurality of devices and separated later] (Para. [0138]), and having a first major surface [top of 30 Fig. 3A] and a second major surface [bottom of 30 Fig. 3A], and of forming a semiconductor layer [3 Fig. 3B] including a plurality of portions each of which becomes the semiconductor laminate [multilayer semiconductor layer 3 shown in Fig. 3B separates into plurality of portions] Para. [0138]) on the first major surface [top of 30];
a second step [Fig. 3D] of removing a part of the semiconductor layer by etching [etching of bulk layer 3 Fig. 3C to Fig. 3D Para. (0142)] such that each of the plurality of portions [plurality shown in Fig. 3D divided by lines 12 Para. (0142)] each of which becomes the semiconductor laminate includes a ridge portion [14 Fig. 3D] (Para. [0142]) after the first step;
a third step [Fig. 4A] of forming an insulating layer [15 Fig. 4A] (Para. [0144]) on the semiconductor wafer [30 Fig. 4A] and on a surface [top surface of 3 Fig. 4A] on an opposite side of the semiconductor layer [3 Fig. 4A] from the second major surface [bottom of 30 Fig. 4A] such that at least a part of a surface on an opposite side [top of ridge portion 14 Fig. 4A] of the ridge portion [14 Fig. 4A] from the semiconductor wafer [30 Fig. 4A] is exposed [top of layer 11 exposed Fig. 4A], (Para. [0144]) after the second step;
a fourth step [Figs. 4B-5A] of forming a plurality of metal plating layers [23] (Para [0147]) each of which becomes the first electrode [21 Fig. 5A Para. (0134)] on the plurality of portions each of which becomes the semiconductor laminate [3 from Fig. 4A],
and of embedding the ridge portion [14 Fig. 5A] in each of the plurality of metal plating layers [23 Fig. 5A] (Para. [0147]), after the third step;
a fifth step [Figs. 5B-6B] of flattening a surface [top surface of 23 Fig. 5B] on an opposite side of each of the plurality of metal plating layers [23 Fig. 5B] from the semiconductor wafer [30 Fig. 5B] by polishing (Para. [0148]) in a state where a protective member [35 Fig. 5B] is disposed in a region [Mask 35 shown in Fig. 4C disposed in partition grooves 12 separating plurality of partitions] between each pair [metal plating layers 23 in other portions of device] (Para. [0144]) of the plurality of metal plating layers [23 Fig. 5B], after the fourth step;
a sixth step [Fig. 6C] of forming an electrode layer [18 Fig. 6C] (Para. [0151]) including a plurality of portions [Fig. 6C shows single portion of a plurality of portions] each of which becomes the second electrode [18 Fig. 6C] on the second major surface [bottom of 30 Fig. 6C] (Para. [0151]); and
a seventh step [Fig. 7A] of cleaving (Para. [0152]) the semiconductor wafer [30] and the semiconductor layer [layer 3 included in device 1 as shown in Fig. 1] along a line [dotted line Fig. 7A] partitioning a plurality of portions each of which becomes the laser element [1 Fig. 7B] off from each other, in a state where the protective member [35] is removed [Mask 35 removed in step shown by Fig. 5C] (Para. [0148]), after the fifth step and the sixth step.
Inoue fails to disclose,
the laser element being a quantum cascade laser element and an active layer of the device having a quantum cascade structure,
the ridge portion including the active layer and a part of the lower cladding layer, whereby a remaining portion of the lower cladding layer not included in the ridge portion extends on both sides of the ridge portion in a width direction of the ridge portion to side surfaces of the semiconductor substrate in the width direction of the ridge portion, and the remaining portion of the lower cladding layer has a thickness at the side surfaces of the semiconductor substrate, and layers constituting the semiconductor laminate are absent on the remaining portion of the lower cladding layer between a side surface of the ridge portion and a side surface of the semiconductor substrate,
a part of each of the plurality of metal plating layers is positioned on both sides of the active layer in the width direction and,
a step of cleaving the wafer along a line partitioning a plurality of portions in a state where the surface of each of the plurality of metal playing layers is flattened
Kaneko discloses in Fig. 2,
A quantum cascade laser element [Fig. 2] (Paras. [0020,22]) including an active layer [40] (Paras. 0022,0024]) having a quantum cascade structure [see Fig. 3] (Para. 0026])
and a ridge portion [mesa including 30,40,50,60 and 72 Fig. 2] (Para. [0022]) including an active layer [40] (Para. [0022]) and a part of a lower cladding layer [32] (Para. [0022]), whereby a remaining portion of the lower cladding layer [32] not included in the ridge portion extends on both sides of the ridge portion in a width direction [left and right of mesa portion Fig. 2] (Para. [0022]) of the ridge portion (Para. [0022]) to side surfaces of a semiconductor substrate [left and right edges of 20 Fig. 2] (Para. [0022]) in the width direction of the ridge portion, and the remaining portion of the lower cladding layer [32] has a thickness at the side surfaces of the semiconductor substrate [20] (Para. [0022])
and layers constituting a semiconductor laminate [30,40,50,60 and 72 Fig. 2] (Para. [0022]) are absent on the remaining portion of the lower cladding layer [32 Fig. 1] (Para. [0022]) between a side surface of the ridge portion [side of mesa Fig. 2] and a side surface of the semiconductor substrate [side of 20 Fig. 2] (Para. [0022]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the active layer and the single ridge structure that includes a quantum cascade structure as disclosed in Kaneko in place of mesa portion as shown in the device of Inoue for the purpose of providing high productivity of infrared emission. (Kaneko Para. [0054])
When the single ridge structure including the active layer and a portion of the lower cladding layer as shown in Kaneko is implemented into the device of Inoue, the limitation of “a part of each of the plurality of metal plating layers is positioned on both sides of the active layer in the width direction” is met as the metal plating layers of Inoue are shown to be positioned on both sides of the mesa portion.
Inoue in view of Kaneko fails to disclose,
cleaving the semiconductor wafer along a line in a state where the surface of each of the plurality of metal plating layer is flattened
Wakisaka discloses in Fig. 1A
a metal film [15] (Para. [0041]) with a flat upper surface [Fig. 1A]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement flat structure of the metal layer described in Wakisaka with the metal plating layers of the modified device of Inoue for the purpose of evenly distributing pressure during bonding and preventing breaking of the bonded element. (Wakisaka Para. [0048])
Regarding claim 2, Inoue in view of Kaneko and Wakisaka as applied to claim 1 above further discloses in Inoue,
wherein in the fourth step [Figs. 4B-5A], a mask member [35 Fig. 4C] (Para. [0146]) is formed on the semiconductor layer [layer 3 shown in Fig. 4A] along the line [mask 35 along partition groove 12 Fig. 4C], and the plurality [Fig. 4C shows single portion of plurality of portions Para. (0144)] of metal plating layers [23 Fig. 5A] are formed through a plurality of openings [space between masks 35 Fig. 5A] included in the mask member [35] (Para. [0147]).
Regarding claim 3, Inoue in view of Kaneko and Wakisaka as applied to claim 2 above further discloses in Inoue,
wherein in the fifth step [Figs. 5B-6B], the mask member [35 Fig. 5B] is used as the protective member (Para. [0146]).
Regarding claim 4, Inoue in view of Kaneko and Wakisaka as applied to claim 1 above further discloses in Inoue,
wherein in the fourth step [Figs. 4B-5A], a metal foundation layer [22 Fig. 5A] each of which becomes the first electrode [22 is part of electrode 21 Para. (0134) and shown in Fig. 5A] is formed to cover at least the part of the surface of the ridge portion [14 Fig. 4B] and to cover the insulating layer [15 Fig. 4B] (Para. [0132]), and the plurality of metal plating layers [23 Fig. 5A] are formed on the metal foundation layer [22 Fig. 5A] (Para. [0146]).
Regarding claim 5, Inoue in view of Kaneko and Wakisaka as applied to claim 4 above further discloses in Inoue,
wherein in the fifth step [Figs. 5B-6B], after the surface of each of the plurality of metal plating layers [23 Fig. 5B] is flattened by the polishing [Fig. 5B Para. (0148)], the protective member [35] is removed [35 removed from Fig. 5B to Fig. 5C] (Para. [0148]), and a portion of the metal foundation layer [22] along the line [partition groove 12] is removed by etching [between Fig. 6B and 6C] (Para. [0150]).
Regarding claim 6, Inoue in view of Kaneko and Wakisaka as applied to claim 1 above further discloses in Inoue,
wherein in the fourth step [Figs. 4B-5A], the plurality of metal plating layers [23 Fig. 5A] are formed by plating Au (Para. [0134]), and in the fifth step [Figs. 5B-6B], the surface of each of the plurality of metal plating layers [23 Fig. 5A] is flattened by chemical mechanical polishing [Fig. 5B] (Para. [0148]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Examiner particularly notes (WO 2014173823 A1) which discloses a single ridge structure with improved heat dissipation in the ridge and contact structure. See PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828
/XINNING(Tom) NIU/Primary Examiner, Art Unit 2828
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