Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/24/2026 has been entered.
Response to Amendments
Acknowledgment is made of the amendment filed June 24th, 2026 (“AMSB”), in which: claims 1 and 13 are amended; claim 3 is cancelled; no new claims are added; and rejections of the claims are traversed. Claims 1 and 4 – 20, wherein claims 15 – 20 are withdrawn from consideration due to a Restriction/Election requirement, are currently pending an Office Action on the merits as follows.
Response to Arguments
Applicant’s arguments filed June 24th, 2026 have been fully considered but are not persuasive.
Applicant argues on pages 10 of the instant Remarks:
Song remains silent regarding, “an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate; wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part”.
Respectfully the examiner disagrees and will provide an explanation for clarity of record. For clarity, it is the examiner’s opinion that Song et al. (US 20200006406 A1) teaches the interlayer dielectric layer has a step structure on a side wall facing the first part; however, for the sake of compact prosecution, the examiner was considering all the features associated with the step structure of the interlayer dielectric layer when stating,
“However, Song remains silent on:
wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate;
the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface;
a height of the first inclined surface in a direction perpendicular to the base substrate is less than a thickness of the interlayer dielectric layer;
the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer.”
That is to say, the examiner was stating that Song does not disclose the step structure of the interlayer dielectric layer including all of the above features, not that Song does not disclose a step structure in general. Examiner asserts that song teaches a step structure in an interlayer dielectric. Further, Song’s step structure already includes the feature wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate. The examiner is not persuaded by the applicant’s arguments. See rejection of claim 1 below.
Further, applicant appears to argue on pages 11 – 12 of the instant Remarks that Chen (US 20180046045 A1) does not disclose an active layer or a shielding layer and therefore does teach the claimed distances. Respectfully, Examiner is not persuaded by applicant’s arguments. Chen’s disclosure was relied upon for its teaching of a semi-closed frame pattern for a via hole; wherein Chen’s teaching is used to modify Song’s via hole, including the relevant active layer and shielding layer. The distances of the portions of the step structure, and how features may be nested therein, are directly applicable to Song’s via hole, including their active layer and shielding layer. See rejections below.
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 5, 7, and 11 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20200006406 A1), and further in view of Chen et al. (US 20180046045 A1).
Regarding independent claim 1, Song teaches an array substrate, comprising:
a base substrate (Fig. 6L; base substrate 1);
a light shielding layer (Fig. 6L; light-shielding layer 2), located on a side of the base substrate (Fig. 6L);
a buffer layer (Fig. 6L; buffer layer 3), located on a side of the light shielding layer facing away from the base substrate (Fig. 6L);
an active layer (Fig. 6L; active layer 4), located on a side of the buffer layer facing away from the light shielding layer (Fig. 6L), an orthographic projection of the active layer on the base substrate being covered by an orthographic projection of the light shielding layer on the base substrate (Fig. 6L);
an interlayer dielectric layer (Fig. 6L; interlayer dielectric layer 5), located on a side of the active layer facing away from the buffer layer (Fig. 6L), the interlayer dielectric layer having a via hole (Fig. 6L; first via hole 41, second via hole 51, and third via hole 31 are interpreted by the examiner to be a via hole), the via hole comprising a first part (Fig. 6L; first via hole 41 and third via hole 31 are interpreted to be a first part) and a second part (Fig. 6L; third via hole 51 is interpreted to be a second part), an orthographic projection of the first part on the base substrate being in contact with an orthographic projection of the second part on the base substrate (Fig. 6L), the first part of the via hole penetrating through the interlayer dielectric layer and the buffer layer (Fig. 6L; see first via hole 41 and third via hole 31 with respect to the interlayer dielectric layer 5 and the buffer layer 3) and exposing a part of the light shielding layer (Figs. 6K and 6L), and the second part penetrating through the interlayer dielectric layer and exposing at least a part of the active layer (Fig. 6L; see second via hole 51 with respect to the interlayer dielectric layer 5 and the active layer 4); and
a source drain layer (Fig. 6L; source electrode 61), located on a side of the interlayer dielectric layer facing away from the active layer (Fig. 6L), the source drain layer being electrically connected with the light shielding layer through the first part (Fig. 6L), and being electrically connected with the active layer through the second part (Fig. 6L), ...
However, Song remains silent on:
wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate;
the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface;
a height of the first inclined surface in a direction perpendicular to the base substrate is less than a thickness of the interlayer dielectric layer;
the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer;
wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part.
However, in the same field of endeavor, Chen teaches an array substrate including a via hole structure (Fig. 3a) wherein:
the interlayer dielectric layer (Fig. 3a; insulating layer 102) has a step structure on a side wall (Fig. 3a; semi-retaining region M) facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern (Fig. 2a); …
the step structure comprises: a first inclined surface (Chen: Fig. 3a; inclined portion of the insulating layer 102 in the via hole associated with the vertical distance h2) connected with a surface of the interlayer dielectric layer facing away from the buffer layer (Chen: Fig. 3a; top surface of the insulating layer 102), a second inclined surface (Chen: Fig. 3a; inclined portion of the insulating layer 102 in the via hole associated with the vertical distance h1) connected with a surface of the interlayer dielectric layer (Chen: Fig. 3a; a portion of the bottom surface of insulating layer 102) ... and a plane (Chen: Fig. 3a; a portion insulating layer 102 in the via hole between the first and second inclined surfaces) connecting the first inclined surface with the second inclined surface (Chen: Fig. 3a);
a height of the first inclined surface (Chen: examiner is interpreting the height = h2 – h1 to be a height of the first inclined surface, as shown in Fig. 3a) in a direction perpendicular to the base substrate is less than a thickness of the interlayer dielectric layer (Chen: Fig. 3a); ...
Examiner asserts that Chen’s disclosed structure for a via hole is a structure that one of ordinary skill in the art would find applicable to Song’s array substrate, as Song describes a similar step structure within their disclosure (Fig. 6L of Song). Chen’s disclosed via hole structure applied to Song’s array substrate structure yields the above claimed limitations with Song’s buffer layer, such that Song, further in view of Chen, also yield a second inclined surface (Chen: Fig. 3a; inclined portion of the insulating layer 102 in the via hole associated with the vertical distance h1) connected with a surface of the interlayer dielectric layer (Chen: Fig. 3a; a portion of the bottom surface of insulating layer 102) facing the buffer layer (Combination of Song and Chen (Fig. 3a).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s via hole to include Chen’s via hole structure wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Chen’s via hole is comparable to Song’s via hole because they both disclose via holes at the transistor level for an array substrate; wherein they address problems caused by a deep via hole in the insulating layer of an existing array substrate (Chen: [0004]). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Song’s via hole to include Chen’s via hole structure wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface with the predictable result of improving problems caused by a deep via hole in the insulating layer of an existing array substrate (Chen: [0004]).
Further, Examiner asserts that the array substrate feature wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate would be naturally yielded and obvious. For clarity, Song does include a step structure in their interlayer dielectric, albeit with some differences (wherein the differences are bridged by Chen); and Song’s opening, and projection thereof, is already facing the active layer, and projection thereof. Thus, when Song’s via hole is modified by Chen’s features, e.g., slanted sides, the light emitting substrate wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate would be naturally yielded.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song, further in view of Chen, to include a step structure wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify the interlayer dielectric layer having a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern of Song, further in view of Chen, to include an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate is expressly provided by Song, showing in at least Fig. 6L that Song’s opening, and projection thereof, is already facing the active layer, and projection thereof. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song, further in view of Chen, to include a step structure wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate with the motivation of exposing a portion of the active layer. The person of ordinary skill in the art would have recognized the benefit of selectively exposing contact regions for a circuit structure, such as an active layer.
Additionally, to the best of the examiner’s understanding, Chen’s semi-closed frame pattern results from the step structure of the interlayer dielectric layer, wherein the steps are not fully covering sides around the via hole, while the first part of the via hole is still a looped structure, i.e., a semi-closed frame pattern. The geometry disclosed by Chen’s semi-closed frame pattern is an example of a structure wherein the projection of the top portion has a center point that is off-set from the center of the bottom portion, i.e., wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part. Examiner asserts that this would naturally yield the modification of Song’s array substrate, in view of Chen’s semi-closed frame pattern.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song, further in view of Chen, to include Chen’s semi-closed frame pattern, wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify the via hole of Song, further in view of Chen, to include Chen’s a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part is implicitly provided by Chen’s teaching of a semi-closed frame pattern, showing in Figs. 2a and 3a that the projection of the top portion of the semi-closed frame pattern has a center point that is off-set from the center of the bottom portion the semi-closed frame pattern. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the via hole of Song, further in view of Chen, to include Chen’s semi-closed frame pattern with the motivation of providing structure geometry favorable to protect device features. The person of ordinary skill in the art would have recognized the benefit of Chen’s semi-closed frame pattern.
Examiner asserts that the modification of Song, further in view of Chen, yields the display substrate including a via hole structure wherein:
the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness (Chen: Fig. 3a; vertical distance h1. Also see [0010]); the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer (Combination of Song and Chen (Fig. 3a). The modification, as disclosed by Chen, applied to Song’s via hole yields the preceding limitation since the vertical distance h1includes this the distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer) and a thickness of the active layer (Song: Fig.6L; thickness of the active layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s array substrate to include Chen’s disclosed via hole structure wherein, the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer, because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, Chen’s via hole structure permits thicknesses wherein, “the vertical distance between the upper surface of the semi-retaining region of the insulating layer and the upper surface of the first conductive layer is smaller than or equal to half the vertical distance between the upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer.” This known benefit in Chen’s array substrate is applicable to Song’s array substrate as they both share characteristics and capabilities, namely, they are directed to array substrates of display panels. Therefore, it would have been recognized that modifying the via hole structure of the array substrate of Song, further in view of Chen, to further include Chen’s via hole structure wherein the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate Chen’s via hole structure wherein the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer in array substrates that may be implemented in display devices and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Regarding dependent claim 5, Song, further in view of Chen, teach the array substrate according to claim 1, wherein
the orthographic projection of the active layer on the base substrate is in contact with the orthographic projection of the first part on the base substrate (Fig. 6L).
Regarding dependent claim 7, Song, further in view of Chen, teach the array substrate according to claim 1, wherein
a material of the active layer comprises a semiconductor oxide (Song: [0082]).
Regarding dependent claim 11, Song, further in view of Chen, teach the array substrate according to claim 1, wherein
the array substrate comprises a driving transistor (Song: the transistor shown in Fig. 6L and [0074] - [0080] is considered by the examiner to be a driving transistor because Song teaches that the transistor receives an electrical signal for display pixels), and the source drain layer is a source drain layer of the driving transistor (Fig. 6L).
Regarding dependent claim 12, Song, further in view of Chen, teach the array substrate according to claim 1, wherein
a material of the light shielding layer is metal (Song: [0080]).
Regarding independent claim 13, Song teaches a display panel, comprising an array substrate, wherein the array substrate comprises:
a base substrate (Fig. 6L; base substrate 1);
a light shielding layer (Fig. 6L; light-shielding layer 2), located on a side of the base substrate (Fig. 6L);
a buffer layer (Fig. 6L; buffer layer 3), located on a side of the light shielding layer facing away from the base substrate (Fig. 6L);
an active layer (Fig. 6L; active layer 4), located on a side of the buffer layer facing away from the light shielding layer (Fig. 6L), an orthographic projection of the active layer on the base substrate being covered by an orthographic projection of the light shielding layer on the base substrate (Fig. 6L);
an interlayer dielectric layer (Fig. 6L; interlayer dielectric layer 5), located on a side of the active layer facing away from the buffer layer (Fig. 6L), the interlayer dielectric layer having a via hole (Fig. 6L; first via hole 41, second via hole 51, and third via hole 31 are interpreted by the examiner to be a via hole), the via hole comprising a first part (Fig. 6L; first via hole 41 and third via hole 31 are interpreted to be a first part) and a second part (Fig. 6L; third via hole 51 is interpreted to be a second part), an orthographic projection of the first part on the base substrate being in contact with an orthographic projection of the second part on the base substrate (Fig. 6L), the first part of the via hole penetrating through the interlayer dielectric layer and the buffer layer (Fig. 6L; see first via hole 41 and third via hole 31 with respect to the interlayer dielectric layer 5 and the buffer layer 3) and exposing a part of the light shielding layer (Figs. 6K and 6L), and the second part penetrating through the interlayer dielectric layer and exposing at least a part of the active layer (Fig. 6L; see second via hole 51 with respect to the interlayer dielectric layer 5 and the active layer 4); and
a source drain layer (Fig. 6L; source electrode 61), located on a side of the interlayer dielectric layer facing away from the active layer (Fig. 6L), the source drain layer being electrically connected with the light shielding layer through the first part (Fig. 6L), and being electrically connected with the active layer through the second part (Fig. 6L) , ...
However, Song remains silent on:
wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate;
the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface;
a height of the first inclined surface in a direction perpendicular to the base substrate is less than a thickness of the interlayer dielectric layer;
the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer.
wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part.
However, in the same field of endeavor, Chen teaches an array substrate including a via hole structure (Fig. 3a) wherein:
the interlayer dielectric layer (Fig. 3a; insulating layer 102) has a step structure on a side wall (Fig. 3a; semi-retaining region M) facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern (Fig. 2a);
the step structure comprises: a first inclined surface (Chen: Fig. 3a; inclined portion of the insulating layer 102 in the via hole associated with the vertical distance h2) connected with a surface of the interlayer dielectric layer facing away from the buffer layer (Chen: Fig. 3a; top surface of the insulating layer 102), a second inclined surface (Chen: Fig. 3a; inclined portion of the insulating layer 102 in the via hole associated with the vertical distance h1) connected with a surface of the interlayer dielectric layer (Chen: Fig. 3a; a portion of the bottom surface of insulating layer 102) ... and a plane (Chen: Fig. 3a; a portion insulating layer 102 in the via hole between the first and second inclined surfaces) connecting the first inclined surface with the second inclined surface (Chen: Fig. 3a);
a height of the first inclined surface (Chen: examiner is interpreting the height = h2 – h1 to be a height of the first inclined surface, as shown in Fig. 3a) in a direction perpendicular to the base substrate is less than a thickness of the interlayer dielectric layer (Chen: Fig. 3a); ...
Chen’s disclosed via hole structure applied to Song’s array substrate structure yields the above claimed limitations with Song’s buffer layer, such that Song, further in view of Chen, also yield a second inclined surface (Chen: Fig. 3a; inclined portion of the insulating layer 102 in the via hole associated with the vertical distance h1) connected with a surface of the interlayer dielectric layer (Chen: Fig. 3a; a portion of the bottom surface of insulating layer 102) facing the buffer layer (Combination of Song and Chen (Fig. 3a).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s via hole to include Chen’s via hole structure wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Chen’s via hole is comparable to Song’s via hole because they both disclose via holes at the transistor level for an array substrate; wherein they address problems caused by a deep via hole in the insulating layer of an existing array substrate (Chen: [0004]). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Song’s via hole to include Chen’s via hole structure wherein the interlayer dielectric layer has a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern; the step structure comprises: a first inclined surface connected with a surface of the interlayer dielectric layer facing away from the buffer layer, a second inclined surface connected with a surface of the interlayer dielectric layer facing the buffer layer, and a plane connecting the first inclined surface with the second inclined surface with the predictable result of improving problems caused by a deep via hole in the insulating layer of an existing array substrate (Chen: [0004]).
Further, Examiner asserts that the array substrate feature wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate would be naturally yielded and obvious. For clarity, Song does include a step structure in their interlayer dielectric, albeit with some differences (wherein the differences are bridged by Chen); and Song’s opening, and projection thereof, is already facing the active layer, and projection thereof. Thus, when Song’s via hole is modified by Chen’s features, e.g., slanted sides, the light emitting substrate wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate would be naturally yielded.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song, further in view of Chen, to include a step structure wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify the interlayer dielectric layer having a step structure on a side wall facing the first part, and an orthographic projection of the step structure on the base substrate is a semi-closed frame pattern of Song, further in view of Chen, to include an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate is expressly provided by Song, showing in at least Fig. 6L that Song’s opening, and projection thereof, is already facing the active layer, and projection thereof. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song, further in view of Chen, to include a step structure wherein an opening of the orthographic projection of the step structure on the base substrate faces the orthographic projection of the active layer on the base substrate with the motivation of exposing a portion of the active layer. The person of ordinary skill in the art would have recognized the benefit of selectively exposing contact regions for a circuit structure, such as an active layer.
Additionally, to the best of the examiner’s understanding, Chen’s semi-closed frame pattern results from the step structure of the interlayer dielectric layer, wherein the steps are not fully covering sides around the via hole, while the first part of the via hole is still a looped structure, i.e., a semi-closed frame pattern. The geometry disclosed by Chen’s semi-closed frame pattern is an example of a structure wherein the projection of the top portion has a center point that is off-set from the center of the bottom portion, i.e., wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part. Examiner asserts that this would naturally yield the modification of Song’s array substrate, in view of Chen’s semi-closed frame pattern.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song, further in view of Chen, to include Chen’s semi-closed frame pattern, wherein a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify the via hole of Song, further in view of Chen, to include Chen’s a center of the orthographic projection of the step structure on the base substrate does not overlap a center of a first region, and the first region is a region of the light shielding layer exposed by the first part is implicitly provided by Chen’s teaching of a semi-closed frame pattern, showing in Figs. 2a and 3a that the projection of the top portion of the semi-closed frame pattern has a center point that is off-set from the center of the bottom portion the semi-closed frame pattern. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the via hole of Song, further in view of Chen, to include Chen’s semi-closed frame pattern with the motivation of providing structure geometry favorable to protect device features. The person of ordinary skill in the art would have recognized the benefit of Chen’s semi-closed frame pattern.
Examiner asserts that the modification of Song, further in view of Chen, yields the display substrate including a via hole structure wherein:
the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness (Chen: Fig. 3a; vertical distance h1. Also see [0010]); the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer (Combination of Song and Chen (Fig. 3a). The modification, as disclosed by Chen, applied to Song’s via hole yields the preceding limitation since the vertical distance h1includes this the distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer) and a thickness of the active layer (Song: Fig.6L; thickness of the active layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s array substrate to include Chen’s disclosed via hole structure wherein, the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer, because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, Chen’s via hole structure permits thicknesses wherein, “the vertical distance between the upper surface of the semi-retaining region of the insulating layer and the upper surface of the first conductive layer is smaller than or equal to half the vertical distance between the upper surface of the full-retaining region of the insulating layer and the upper surface of the first conductive layer.” This known benefit in Chen’s array substrate is applicable to Song’s array substrate as they both share characteristics and capabilities, namely, they are directed to array substrates of display panels. Therefore, it would have been recognized that modifying the via hole structure of the array substrate of Song, further in view of Chen, to further include Chen’s via hole structure wherein the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate Chen’s via hole structure wherein the height of the first inclined surface in the direction perpendicular to the base substrate is equal to a first thickness; the first thickness is a sum of a distance from a surface of a side of the light shielding layer away from the base substrate to a surface of a side of the buffer layer away from the light shielding layer and a thickness of the active layer in array substrates that may be implemented in display devices and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Regarding dependent claim 14, Song, further in view of Chen, teach
a display apparatus (Song: [0080] teaches that the array substrate may be used in an organic light-emitting diode (OLED) display device), comprising the display panel according to claim 13.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20200006406 A1), and further in view of Chen et al. (US 20180046045 A1) and Oh et al. (US 20160071891 A1).
Regarding dependent claim 4, Song, further in view of Chen, teach the array substrate according to claim 1; however, Song remains silent wherein the step structure comprises:
wherein the buffer layer has a third inclined surface on a side wall facing the first part; and the second inclined surface and the third inclined surface are located on a same inclined surface.
However, in the same field of endeavor, Oh teaches similar via hole in comparison to Song, wherein the via hole is made through a buffer layer present in the disclosed device (e.g., Fig. 6C; drain contact hole 124D). Oh’s disclosed via hole is made with a tapered shape, analogous to Chen’s via hole formed with tapered/angled/inclined sidewalls, such that Oh’s disclosure may be readily combined with the array substrate of Song, further in view of Chen, to yield the array substrate wherein the buffer layer has a third inclined surface on a side wall facing the first part; and the second inclined surface and the third inclined surface are located on a same inclined surface.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the via hole of Song, further in view of Chen, to include the structure at the buffer layer wherein the buffer layer has a third inclined surface on a side wall facing the first part; and the second inclined surface and the third inclined surface are located on a same inclined surface, as disclosed by Oh, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Oh’s via hole is comparable to the via holes of Song and Chen because they all disclose via holes at the transistor level for an array substrate. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the via hole of Song, further in view of Chen, to include the structure at the buffer layer wherein the buffer layer has a third inclined surface on a side wall facing the first part; and the second inclined surface and the third inclined surface are located on a same inclined surface, as disclosed by Oh, with the predictable result of simplifying the method of forming a contact via, as the via hole is formed to have an inclined surface through the interlayer dielectric layer and active layer.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20200006406 A1), and further in view of Chen et al. (US 20180046045 A1) and Song, K. et al. (US 20060046361 A1).
Regarding dependent claim 6, Song, further in view of Chen, teach the array substrate according to claim 1; however, Song remains silent wherein
the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part on the base substrate have a gap therebetween.
However, in the same field of endeavor, Song, K. (US 20060046361 A1) teaches a similar array substrate wherein a source/drain structure (Fig. 27; source electrode 412) are formed in a through hole (contact hole 161) that exposes the light barrier layer 121, i.e., a light shielding layer, and semiconductor layer 171, i.e., an active layer; wherein the portion of the through hole exposing the light shielding layer is considered by the examiner to be a first part, i.e., portion of contact hole 161 between a top surface of buffer layer 140 and a bottom surface of buffer layer 140. Examiner notes the portion of gate insulating layer 160 that extends past the active layer (Fig. 27) creates a gap between the first part and the active layer; such that Song teaches the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part on the base substrate have a gap therebetween. Thus, in view of Song. K.’s teaching, modifying Song’s top gate transistor to a bottom gate transistor, necessitating a gate insulating layer between the active layer and the buffer layer yields the array substrate wherein the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part on the base substrate have a gap therebetween.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the array substrate of Song to include Song, K.’s structure of a bottom gate transistor, such that an additional layer may be formed between the buffer layer and the active layer, allowing for the formation of a gap between the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part on the base substrate, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Song’s transistor in their array substrate is comparable to Song, K.’s transistor in their array substrate because both transistor may have the same functionality and use in semiconductor devices, such as display panels. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the array substrate of Song to include Song, K.’s structure of a bottom gate transistor, such that an additional layer may be formed between the buffer layer and the active layer, allowing for the formation of a gap between the orthographic projection of the active layer on the base substrate and the orthographic projection of the first part on the base substrate with the predictable result of forming a bottom gate transistor.
Claims 8 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20200006406 A1), and further in view of Chen et al. (US 20180046045 A1) and Gou et al. (US 20190004660 A1).
Regarding dependent claim 8, Song, further in view of Chen, teach the array substrate according to claim 1; however, Song remains silent wherein
a depth of the via hole at a position exposing the light shielding layer is 5000 Å to 16000 Å.
However, in the same field of endeavor, Gou teaches a via hole 121 that penetrates through an interlayer dielectric layer 108, a gate insulating layer 106, and buffer layer 104. Further, Gou teaches in [0054] that in order to form the via hole 121 to electrically connect the force electrode wire 111 and the force electrode 103 (of the shielding layer 102), the interlayer dielectric layer 108, the gate insulating layer 106 and the buffer layer 104 are etched, and it is needed to etch a thickness over 10000 Å. Thus, applying Gou’s teaching to the array substrate of Song yields an array substrate wherein a depth of the via hole at a position exposing the light shielding layer is 5000 Å to 16000 Å.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s via hole to include a depth of the via hole at a position exposing the light shielding layer is 5000 Å to 16000 Å, as disclosed by Gou, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Song’s via hole is comparable to Gou’s via hole because they both disclose via holes at the transistor level for an array substrate. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Song’s via hole to include a depth of the via hole at a position exposing the light shielding layer is 5000 Å to 16000 Å, as disclosed by Gou, with the predictable result of forming an opening to connect a source drain contact to a layer/component including the light shielding layer.
Further, the feature wherein a depth of the via hole at a position exposing the light shielding layer is 5000 Å to 16000 Å would have been obvious, from at least [0054] Gou, to one of ordinary skill in the art before the effective filing date of the instant invention because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding dependent claim 9, Song, further in view of Chen and Gou, teach the array substrate according to claim 8; however, Song remains silent wherein
a depth of the via hole at a position exposing the active layer is 4000 Å to 12000 Å.
However, in the same field of endeavor, Gou teaches via holes 122 and 123 that penetrates through an interlayer dielectric layer 108 and a gate insulating layer 106. Further, in [0054], Gou teaches layer thicknesses for the dielectric layer 108 and the gate insulating layer 106 to be 5500 Å and 1200 Å, respectively. Therefore, Gou teaches depths of the via holes 122 and 123 to be in the range of 5500 Å to 6700 Å. Thus, applying Gou’s teaching to the array substrate of Song yields an array substrate wherein a depth of the via hole at a position exposing the active layer is 4000 Å to 12000 Å.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s via hole to include a depth of the via hole at a position exposing the active layer is 4000 Å to 12000 Å, as disclosed by Gou, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Song’s via hole is comparable to Gou’s via hole because they both disclose via holes at the transistor level for an array substrate. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Song’s via hole to include a depth of the via hole at a position exposing the active layer is 4000 Å to 12000 Å, as disclosed by Gou, with the predictable result of forming an opening to connect a source drain contact to a layer/component including the light shielding layer.
Further, the feature wherein a depth of the via hole at a position exposing the active layer is 4000 Å to 12000 Å would have been obvious, from at least [0054] Gou, to one of ordinary skill in the art before the effective filing date of the instant invention because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20200006406 A1), and further in view of Chen et al. (US 20180046045 A1) and Okada et al. (US 20180259820 A1).
Regarding dependent claim 10, Song, further in view of Chen, teach the array substrate according to claim 1; however, Song remains silent wherein
an angle of gradient of the via hole is 40° to 80°.
However, Okada teaches an array substrate including a contact hole 22a (see Figs. 6 and 7(b)); wherein the contact hole 22a includes an inclination angle α of a side surface of the contact hole. The inclination angle α is set to be less than 90°, for example, about 40° to 60°. Thus, applying Okada’s teaching to the array substrate of Song yields an array substrate wherein an angle of gradient of the via hole is 40° to 80°.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Song’s via hole to include inclined sidewalls, such that an angle of gradient of the via hole is 40° to 80°, as disclosed by Okada, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, More specifically, Song’s via hole is comparable to Okada’s via hole because they both disclose via holes at the transistor level for an array substrate. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Song’s via hole to include inclined sidewalls, such that an angle of gradient of the via hole is 40° to 80°, as disclosed by Okada with the predictable result of suppressing light leakage (Okada: [0104] – [0106]).
Further, the feature wherein an angle of gradient of the via hole is 40° to 80° would have been obvious, from at least [0104] – [0106] of Okada, to one of ordinary skill in the art before the effective filing date of the instant invention because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20130026475 A1 teaches relevant via structures for structures relevant to the instant disclosure (Figs. 1 – 3).
US 20200083604 A1 teaches relevant structures and widths for vias (e.g., Fig. 22A).
US 20200105789 A1 teaches relevant structures vias (e.g., Figs. 1 - 6).
US 10942403 B2 teaches via heights/vertical distances, e.g., Fig. 2.
US 20120057110 A1 teaches via heights/vertical distances, e.g., Fig. 2.
US 20140209915 A1 teaches via heights/vertical distances, e.g., Fig. 15.
US 20150116623 A1 teaches via heights/vertical distances, e.g., Fig. 3.
US 20150228675 A1 teaches via heights/vertical distances, e.g., Fig. 2.
US 10050223 B2 teaches similar etching patterns of insulating layers.
US 20210091333 A1 teaches similar etching patterns of insulating layers (Fig. 11).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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