Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is nonfinal and is in response to claims filed on 09/28/2022. Claims 1-19 are pending for examination.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/28/2022 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Specification
The abstract of the disclosure is objected to because it is not on a separate sheet, apart from any other text. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claims 1-3, 7-7, and 10 are objected to because of the following informalities:
Claim 1 recites “wherein the processor system is arranged to support a plurality of of random number generating processes”. This should be changed to “wherein the processor system is arranged to support a plurality of [[of]] random number generating processes”.
Claim 1 recites “wherein the processor system is arranged to initiate the plurality of of supported parallel random number generating processes,”. This should be changed to “wherein the processor system is arranged to initiate the plurality of [[of]] supported parallel random number generating processes,”.
Claim 1 recites “wherein the random matrix is divided into as many parts as the plurality of of parallel random number generating processes,”. This should be changed to “wherein the random matrix is divided into as many parts as the plurality of [[of]] parallel random number generating processes,”.
Claim 1 recites “wherein the processor system is arranged to assemble assembling the random matrix”. This should be changed to “wherein the processor system is arranged to assemble
Claim 2 recites “The generation device as in claim 1, wherein the plurality of of parallel random number generating processes equals, a register size divided by a word size of the random number state”. This should be changed to “The generation device as in claim 1, wherein the plurality of [[of]] parallel random number generating processes equals, a register size divided by a word size of the random number state”.
Claim 3 recites “wherein the random number generation function is arranged to generate multiple random numbers in conjunction with updating the at one of the random number states in parallel”. This should be changed to “wherein the random number generation function is arranged to generate multiple random numbers in conjunction with updating the at least one of the random number states in parallel.”
Claim 6 recites “the input interface is arranged to receive the seed”. This should be changed to “the input interface circuit is arranged to receive the seed” to bring it inline with the language of claim 1.
Claim 7 recites “a noisy multiplication between the generated random matrix (A) and the private-key”. This should be changed to “a noisy multiplication between the generated random matrix [[(A)]] and the private-key.”
Claim 10 recites “computer program stored on a transitory medium wherein the computer program when executed on a processor performs the method as claimed in claim 9”. This should be changed to “A computer program stored on a transitory medium wherein the computer program when executed on a processor performs the method as claimed in claim 9”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 11-12, 15, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein each random number generating process executes in parallel to the random number initiation function”. It is unclear how the initiation function and generation processes can be executed in parallel if the generation processes require the state from the initiation function as recited in “wherein each random number generating process obtains the random number state from the random number initiation function,” of claim 1.
Claim 15 recites “wherein the number is amount of the plurality of cores of a processor system”. It is unclear if this the same processor system of claim 9 or a different processor system. For examination purposes, examiner has interpreted “wherein the number is amount of the plurality of cores of a processor system” as “wherein the number is amount of the plurality of cores of [[a]] the processor system”.
Claim 19 recites the limitation " wherein the generation device and the second device are arranged to generate the random matrix from the same seed". There is insufficient antecedent basis for this limitation in the claim. “the generation device” is not recited in claims 9 or 18, which claim 19 depends from.
Claims 2-8 and 11-12 are rejected for being dependent on an above rejected claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 10 is rejected under 35 U.S.C. 101, based upon consideration of all the relevant factors, because the claimed invention is directed to non-statutory subject matter. Applicant does not include any language in the specification providing any further guidance or definition to the term “transitory medium.” Therefore, the broadest reasonable interpretation of the claim covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable medium. See Ex parte Mewherter, BPAI Appeal No. 2012-7692 (May 8, 2013). Since signals per se do not fall under any of the four statutory categories (i.e., process, machine, manufacture, or composition of matter), they are ineligible for patenting. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007).
Claim 10 is therefore rejected under 35 U.S.C. § 101 for covering non- statutory embodiments. See MPEP § 2106.03 (“A claim whose BRI covers both statutory and non-statutory embodiments embraces subject matter that is not eligible for patent protection and therefore is directed to non-statutory subject matter. Such claims … should be rejected under 35 U.S.C. 101, for at least this reason.”).
Examiner recommends amending claim 10 by changing the “transitory” to “non-transitory” in order to overcome this ground of rejection.
Claims 1-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at Step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
a generation device comprising (mental process, evaluation)
an input interface circuit, wherein the input interface circuit is arranged to receive a request for a random matrix; and (mental process, evaluation)
a processor system,
wherein the processor system is arranged to support a plurality of of random number generating processes, (mental process, evaluation)
wherein each of the random number generation processes are arranged to (mental process, evaluation) generate the elements of the random matrix; (mathematical calculation)
wherein the processor system is arranged to provide at least one random number initiation function, (mental process, evaluation)
wherein the at least one random number initiation function is arranged to (mental process, evaluation) receive a seed and to generate a random number state; (mathematical calculation)
wherein the processor system is arranged to provide a random number generation function, (mental process, evaluation)
wherein the random number generation function is arranged to (mental process, evaluation) generate random numbers (mathematical calculation) in conjunction with updating the random number state, (mathematical calculation)
wherein the processor system is arranged to initiate the plurality of of supported parallel random number generating processes, (mental process, evaluation)
wherein each random number generating process executes in parallel to the random number initiation function, (mental process, evaluation)
wherein each random number generating process obtains the random number state from the random number initiation function, (mental process, evaluation)
wherein the plurality of parallel random number generating processes produce at least as many random numbers as elements in the random matrix, (mental process, evaluation; mathematical calculation)
wherein the random matrix is divided into as many parts as the plurality of of parallel random number generating processes, (mental process, evaluation; mathematical calculation)
wherein each part is filled with random numbers in parallel by the random number generating processes executing in parallel, (mental process, evaluation; mathematical calculation)
wherein the processor system is arranged to (mental process, evaluation) assemble the random matrix. (mathematical calculation)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “a generation device comprising” limitation is an evaluation mental process that can be performed by choosing what the generation device comprises. The “wherein the input interface circuit is arranged to” limitation is an evaluation mental process that can be performed by choosing what the input interface circuit is arranged to do. The “wherein the processor system is arranged to” limitation is an evaluation mental process that can be performed by choosing what the processor system is arranged to do. The “wherein each of the random number generation processes are arranged to” limitation is an evaluation mental process that can be performed by choosing what each of the random number generation processes are arranged to do. The “generate the elements of the random matrix” limitation is a mathematical calculation that can be performed by generating the elements of the random matrix by hand using pen and paper. The “wherein the processor system is arranged to” limitation is an evaluation mental process that can be performed by choosing what the processor system is arranged to do. The “wherein the at least one random number initiation function is arranged to” limitation is an evaluation mental process that can be performed by choosing what the at least one random number initiation function is arranged to do. The “a seed and to generate a random number state” limitation is a mathematical calculation that can be performed by generating the random number state by hand using pen and paper. The “wherein the processor system is arranged to provide a random number generation” limitation is an evaluation mental process that can be performed by choosing what the processor system is arranged to do. The “wherein the random number generation function is arranged to” limitation is an evaluation mental process that can be performed by choosing what the random number generation function is arranged to do. The “generate random numbers” limitation is a mathematical calculation that can be performed by generating the random numbers by hand using pen and paper. The “in conjunction with updating the random number state” limitation is a mathematical calculation that can be performed by updating the random number state by hand using pen and paper. The “wherein the processor system is arranged to initiate the plurality” limitation is an evaluation mental process that can be performed by choosing what the processor system is arranged to do. The “wherein each random number generating process executes in parallel to the” limitation is an evaluation mental process that can be performed by choosing when each random number generating process executes. The “wherein each random number generating process obtains the random number state from the random number initiation function” limitation is an evaluation mental process that can be performed by choosing what each random number generating process obtains. The “wherein the plurality of parallel random number generating processes produce at least” limitation is an evaluation mental process that can be performed by choosing what each of the random number generating processes produce. The “wherein the random matrix is divided into as many parts as the plurality” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing how many parts the random number is divided into and dividing it by hand using pen and paper. The “wherein each part is filled with random numbers in parallel” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing how each part is filled and filling them by hand using pen and paper. The “wherein the processor system is arranged to” limitation is an evaluation mental process that can be performed by choosing what the processor system is arranged to do. The “assemble the random matrix” limitation is a mathematical calculation that can be performed by assembling the matrix by hand using pen and paper.
At step 2A Prong 2, the additional elements are bolded above. The “receive a request for a random matrix” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The receive in the context of the claim encompasses mere data gathering. The “receive a seed and to generate a random number state” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The receive in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “receive a request for a random matrix”, “receive a seed and to generate a random number state”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 9, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 9 is directed towards the statutory category of a method thus also satisfying step 1. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 2 and 13, they are directed to mental processes and/or mathematical concepts. The “wherein the plurality of of parallel random number generating processes equals” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing how many parallel random number generating processes there are and calculating the number by hand using pen and paper. Under step 2A prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 3, it is directed to mental processes and/or mathematical concepts. The “wherein the processor system is arranged with” limitation is an evaluation mental process that can be performed by choosing what the processor system is arranged with. The “wherein a vector is arranged to” limitation is an evaluation mental process that can be performed by choosing what the vector is arranged to do. The “wherein the random number initiation function is configured to” limitation is an evaluation mental process that can be performed by choosing what the random number initiation function is configured to do. The “generate at least one of the random number states in parallel,” limitation is a mathematical calculation that can be performed by generating the random number states by hand using pen and paper. The “wherein the random number generation function is arranged to” limitation is an evaluation mental process that can be performed by choosing what the random number generation function is arranged to do. The “generate multiple random numbers in conjunction with updating the at one of the random number states in parallel” limitation is a mathematical calculation that can be performed by generating the random numbers and updating the random number states in parallel by hand using pen and paper. Under step 2A Prong 2, the “store a word of at least one” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘store’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the processor system, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At Step 2B, the claim recites “store a word of at least one”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claims 4 and 16, they are directed to mental processes and/or mathematical concepts. The “wherein the plurality of parallel random number generating processes receive the same seed and a unique number for each random number generating process” limitation is an evaluation mental process that can be performed by choosing what the plurality of parallel random number generating processes receives. Under step 2A Prong 2, the “receive the same seed” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘receive’ in the context of the claim encompasses mere data gathering. the claims do not recite any more additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. At Step 2B, the claim recites “receive the same seed”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claims 5 and 17, they are directed to mental processes and/or mathematical concepts. The “wherein at least one part comprises multiple rows and/or columns of the random matrix” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the at least one part comprises. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 6, it is directed to mental processes and/or mathematical concepts. The “wherein the input interface is arranged” limitation is an evaluation mental process that can be performed by choosing what the input interface is arranged to do. Under step 2A Prong 2, the “receive the seed” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘receive’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the input interface, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At Step 2B, the claim recites “receive the seed”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claims 7 and 18, they are directed to mental processes and/or mathematical concepts. The “wherein the generation device is arranged to” limitation is an evaluation mental process that can be performed by choosing what the device participates in. The “wherein the processor system is arranged to” limitation is an evaluation mental process that can be performed by choosing what the processing system is arranged to do. The “generating a private-key” limitation is a mathematical calculation that can be performed by generating a private-key by hand using pen and paper. The “and compute a public-key based on the private-key” limitation is a mathematical calculation that can be performed by computing the public key by hand using pen and paper. The “wherein the computation comprises” limitation is an evaluation mental process that can be performed by choosing what the computation comprises. The “a noisy multiplication between the generated random matrix (A) and the private-key” limitation is a mathematical calculation that can be performed by performing a noisy multiplication by hand using pen and paper. Under step 2A prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the generation device, the processor system, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 8 and 19, they are directed to mental processes and/or mathematical concepts. The “wherein the generation device is arranged to” limitation is an evaluation mental process that can be performed by choosing what the device participates in. The “wherein the processor system is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing system is configured to do. The “wherein the computation comprises a multiplication” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what the computation comprises and performing the computation by hand using pen and paper. The “wherein the generation device and the second device are arranged to generate the random matrix from the same seed” limitation is an evaluation mental process that can be performed by choosing how the random numbers are generated. Under step 2A prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the generation device, the processor system, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 10, it is directed to mental processes and/or mathematical concepts. The “computer program stored on a transitory medium wherein the computer program when executed on a processor performs the method as claimed in claim 9” limitation is an evaluation mental process that can be performed by choosing what the computer program does. Under step 2A Prong 2, the “computer program stored on a transitory medium” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering. none of the remaining additional elements regarding the generic computer components (i.e. the generation device, the processor system, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At Step 2B, the claim recites “computer program stored on a transitory medium”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claims 11 and 14, they are directed to mental processes and/or mathematical concepts. The “wherein the plurality of parallel random number generating processes equals a number” limitation is an evaluation mental process that can be performed by choosing the amount of processes. The “wherein the number is the amount of the plurality of cores of the processor system” limitation is an evaluation mental process that can be performed by choosing the number. Under step 2A prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the processor system, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 12 and 15, they are directed to mental processes and/or mathematical concepts. The “wherein the plurality of parallel random number generating processes equals, the product of a register size divided by a random number state size multiplied by a number” limitation is an evaluation mental process that can be performed by choosing the amount of processes. The “wherein the number is amount of the plurality of cores of the processor system” limitation is an evaluation mental process that can be performed by choosing the number. Under step 2A prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the processor system, the register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6, 9-10, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tredak et al. (US 20160162262 A1) hereinafter Tredak.
With regards to claim 1, Tredak teaches a generation device comprising an input interface circuit, wherein the input interface circuit is arranged to receive a request for a random matrix (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns; Tredak [0023]: integer numbers M and N are accessed, where N may denote the length of the sequence of pseudo-random numbers to be generated in an iteration, with M<N. In some embodiments, M and N are constant parameters specified by the random generation algorithm. For instance, M=397 and N=624 are constant parameters in MT19937. In some other embodiments, M and/or N may be a variable to be configured by a user)
and a processor system, wherein the processor system is arranged to support a plurality of of random number generating processes, wherein each of the random number generation processes are arranged to generate the elements of the random matrix; (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns… computing respective second values of the N elements by the K execution threads in parallel)
wherein the processor system is arranged to provide at least one random number initiation function, wherein the at least one random number initiation function is arranged to receive a seed and to generate a random number state; (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns, wherein, a respective pair of adjacent elements in a column are related by g=(M+j) mod N; (N being the seeds))
wherein the processor system is arranged to provide a random number generation function, wherein the random number generation function is arranged to generate random numbers in conjunction with updating the random number state, (Tredak [0009]: computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the processor system is arranged to initiate the plurality of of supported parallel random number generating processes, (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel)
wherein each random number generating process executes in parallel to the random number initiation function, (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel)
wherein each random number generating process obtains the random number state from the random number initiation function, (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the plurality of parallel random number generating processes produce at least as many random numbers as elements in the random matrix, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the random matrix is divided into as many parts as the plurality of of parallel random number generating processes, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein each part is filled with random numbers in parallel by the random number generating processes executing in parallel, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the processor system is arranged to assemble the random matrix (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
With regards to claim 5, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein at least one part comprises multiple rows and/or columns of the random matrix (Tredak [0009]: dividing the N elements into K sections based on indexes of the N elements; (4) assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
With regards to claim 6, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the input interface is arranged to receive the seed (Tredak [0047]: The user configuration input may include M, N, function f, and seed values for the state elements for processing).
With regards to claim 9, Tredak teaches A generation method comprising: receiving a request for a random matrix, (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns; Tredak [0023]: integer numbers M and N are accessed, where N may denote the length of the sequence of pseudo-random numbers to be generated in an iteration, with M<N. In some embodiments, M and N are constant parameters specified by the random generation algorithm. For instance, M=397 and N=624 are constant parameters in MT19937. In some other embodiments, M and/or N may be a variable to be configured by a user)
initiating a plurality of of parallel random number generating processes in a processor system, (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns… computing respective second values of the N elements by the K execution threads in parallel)
wherein the processor system is arranged to generate elements of the random matrix, (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns… computing respective second values of the N elements by the K execution threads in parallel)
wherein the processor system is arranged to execute at least one random number initiation function for each random number generating process, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns, wherein, a respective pair of adjacent elements in a column are related by g=(M+j) mod N)
wherein the processor system is arranged to obtain a random number state for each random number generating process, (Tredak [0009]: computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the at least one random number initiation function is arranged to receive a seed and to generate the random number state, for each random number generating process, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns, wherein, a respective pair of adjacent elements in a column are related by g=(M+j) mod N; (N being the seeds))
wherein the plurality of parallel random number generating processes produce at least as many random numbers as elements in the random matrix, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the random number generation function is arranged to generate random numbers in conjunction with updating the random number state, (Tredak [0009]: computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the random matrix is divided into as many parts as the plurality of of parallel random number generating processes, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein each part is filled with random numbers in parallel by the random number generating processes executing in parallel, for each random number generating process, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein the processor system is arranged to assemble the random matrix (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns… assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
With regards to claim 10, Tredak teaches all of the limitations of claim 9 above. Tredak further teaches computer program stored on a transitory medium wherein the computer program when executed on a processor performs the method as claimed in claim 9 (Tredak [0009]: a non-transient computer-readable recording medium storing pseudo-random number generator program).
With regards to claim 17, Tredak teaches all of the limitations of claim 9 above. Tredak further teaches wherein at least one part comprises multiple rows and/or columns of the random matrix (Tredak [0009]: dividing the N elements into K sections based on indexes of the N elements; (4) assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 11, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tredak in view of Truta et al. (WO 2015179942 A1) hereinafter Truta.
With regards to claim 2, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the plurality of of parallel random number generating processes equals, [a register size divided by a word size] of the random number state (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach that the number of processes is equal to a register size divided by a word size.
However, Truta teaches that the number of processes of Tredak is equal to a register size divided by a word size (Truta [0020]: the number N is taken as the number of execution units... In an example SIMD machine, the number N is taken to be the length of the SIMD register divided by the machine word size M).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the number of processes as taught by Truta. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of system as it would optimize the amount of parallel operations that can be performed.
With regards to claim 3, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the processor system is arranged with [Single Instruction Multiple Data (SIMD) instructions] operating on data vectors, (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
wherein a vector is arranged to store a word of at least one of the random number states for a portion of the plurality of parallel random number generating processes, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns, wherein, a respective pair of adjacent elements in a column are related by g=(M+j) mod N)
wherein the random number initiation function is configured to generate at least one of the random number states in parallel, (Tredak [0009]: arranging the N elements into a matrix comprising x rows and a plurality of columns, wherein, a respective pair of adjacent elements in a column are related by g=(M+j) mod N)
wherein the random number generation function is arranged to generate multiple random numbers in conjunction with updating the at one of the random number states in parallel (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach the Single Instruction Multiple Data (SIMD) instructions.
However, Truta teaches Single Instruction Multiple Data (SIMD) instructions (the number N is taken as the number of execution units... In an example SIMD machine).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the SIMD instructions as taught by Truta. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of system as it would decrease the complexity of the instructions.
With regards to claim 11, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the plurality of parallel random number generating processes equals a number, (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
Tredak fails to teach wherein the number is the amount of the plurality of cores of the processor system.
However, Truta teaches wherein the number is the amount of the plurality of cores of the processor system (Truta [0016]: The processor 10 includes a plurality of parallel execution units 14. Each execution unit (EU) 14 is capable of performing operations independent from the other execution units 14. The execution units 14 may be referred to as cores and the processor 14 may be referred to as a multi-core processor).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the number of processes being equal to the number of cores as taught by Truta. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of system as it would optimize the amount of parallel operations that can be performed.
With regards to claim 13, Tredak teaches all of the limitations of claim 9 above. Tredak further teaches wherein the plurality of parallel random number generating processes equals, [a register size divided by a word size] of the random number state (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach that the number of processes is equal to a register size divided by a word size.
However, Truta teaches that the number of processes of Tredak is equal to a register size divided by a word size (Truta [0020]: the number N is taken as the number of execution units... In an example SIMD machine, the number N is taken to be the length of the SIMD register divided by the machine word size M).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the number of processes as taught by Truta. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of system as it would optimize the amount of parallel operations that can be performed.
With regards to claim 14, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the plurality of parallel random number generating processes equals a number, (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M))
Tredak fails to teach wherein the number is the amount of the plurality of cores of the processor system.
However, Truta teaches wherein the number is the amount of the plurality of cores of the processor system (Truta [0016]: The processor 10 includes a plurality of parallel execution units 14. Each execution unit (EU) 14 is capable of performing operations independent from the other execution units 14. The execution units 14 may be referred to as cores and the processor 14 may be referred to as a multi-core processor).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the number of processes being equal to the number of cores as taught by Truta. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of system as it would optimize the amount of parallel operations that can be performed.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tredak in view of Paladini et al. (US 20160343161 A1) hereinafter Paladini.
With regards to claim 4, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the plurality of parallel random number generating processes receive [the same seed] and a unique number for each random number generating process (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach of using the same seed.
However, Paladini teaches of using the same seed (Paladini [0042]: For example, in some embodiments, a pseudo-random number generator that relies on an initial seed value may be used. In such embodiments, the common sequence of random numbers may be obtained by using the same seed value for each parallel processing act).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with using the same seed as taught by Paladini. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as it would only have to store one seed.
With regards to claim 16, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches wherein the plurality of parallel random number generating processes receive [the same seed] and a unique number for each random number generating process (Tredak [0009]: assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach of using the same seed.
However, Paladini teaches of using the same seed (Paladini [0042]: For example, in some embodiments, a pseudo-random number generator that relies on an initial seed value may be used. In such embodiments, the common sequence of random numbers may be obtained by using the same seed value for each parallel processing act).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with using the same seed as taught by Paladini. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as it would only have to store one seed.
Claims 7-8 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tredak in view of Bhattacharya et al. (WO 2018206344 A1) hereinafter Bhattacharya.
With regards to claim 7, Tredak teaches all of the limitations of claim 1 above. Tredak further teaches the generated random matrix (A) (Tredak [0009]: dividing the N elements into K sections based on indexes of the N elements; (4) assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach wherein the generation device is arranged to participate in a public-private key protocol, wherein the processor system is arranged to generate a private-key and compute a public-key based on the private-key, wherein the computation comprises a noisy multiplication between [the generated random matrix (A)] and the private-key.
However, Bhattacharya teaches wherein the generation device is arranged to participate in a public-private key protocol, (Bhattacharya Page 2 Lines 5-8: Cryptographic key-encapsulation (KEM) schemes use asymmetric cryptography to establish a shared secret among two parties, using a publicly known (e.g., public-key) and a secretly-owned (e.g., secret-key) value for each party)
wherein the processor system is arranged to generate a private-key (Bhattacharya Page 3 Line 15: generate a private key polynomial)
and compute a public-key based on the private-key, (Bhattacharya Page 3 Line 17-23: generate a public key polynomial by computing a polynomial product between the shared polynomial and the private key polynomial modulo the first modulus obtaining a polynomial product, scaling coefficients of the polynomial product down to a second modulus, a scaled coefficient being equal to the unsealed coefficient multiplied with the second modulus, divided by the first modulus and rounded to the nearest integer)
wherein the computation comprises a noisy multiplication between [the generated random matrix (A)] and the private-key (Bhattacharya Page 3 Line 17-23: generate a public key polynomial by computing a polynomial product between the shared polynomial and the private key polynomial modulo the first modulus obtaining a polynomial product, scaling coefficients of the polynomial product down to a second modulus, a scaled coefficient being equal to the unsealed coefficient multiplied with the second modulus, divided by the first modulus and rounded to the nearest integer (the rounding making it a noisy multiplication)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the public-private key protocol as taught by Bhattacharya. One of ordinary skill in the art would be motivated to make this combination because it would increase the flexibility of the system as the random number generator could be used for the public-private key protocol as well as other uses of a modified MT19937 generator. Also, because of the rounding down operation, an attack who observes traffic between the first node and the second node will not be able to reconstruct the private polynomials used by the nodes, increasing the security of the system as taught by Bhattacharya (Bhattacharya Page 4 Lines 28-30).
With regards to claim 8, Tredak in view of Bhattacharya teaches all of the limitations of claim 7 above. Tredak further teaches wherein the generation device [and the second device are arranged to generate] the random matrix [from the same seed] (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns… computing respective second values of the N elements by the K execution threads in parallel).
Tredak fails to teach wherein the generation device is arranged to participate in a public-private key protocol with a second device, wherein the processor system is configured to compute a raw shared key using a public-key of the second device and the private-key wherein the computation comprises a multiplication, [wherein the generation device] and the second device are arranged to generate the [random matrix] from the same seed.
However, Bhattacharya teaches wherein the generation device is arranged to participate in a public-private key protocol with a second device, (Bhattacharya Page 2 Lines 5-8: cryptographic key-encapsulation (KEM) schemes use asymmetric cryptography to establish a shared secret among two parties, using a publicly known (e.g., public-key) and a secretly-owned (e.g., secret-key) value for each party; Bhattacharya Page 3 Lines 26-27: Send the public key polynomial of the first network node to the second network node)
wherein the processor system is configured to compute a raw shared key using a public-key of the second device and the private-key (Bhattacharya Page 3 Lines 28-30: receive a public key polynomial of the second network node, compute a raw key polynomial as a polynomial product between the received public key of the second node and the private key polynomial of the first network node)
wherein the computation comprises a multiplication, (Bhattacharya Page 3 Lines 28-30: receive a public key polynomial of the second network node, compute a raw key polynomial as a polynomial product between the received public key of the second node and the private key polynomial of the first network node)
[wherein the generation device] and the second device are arranged to generate the [random matrix] from the same seed (Bhattacharya Page 16 Lines 15-17: After receiving the seed, the first and second network node may use it to generate the polynomial a in any of the above ways. The same random seed is used to seed a deterministic pseudo random number generator).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak in view of Bhattacharya with the public-private key protocol as taught by Bhattacharya. One of ordinary skill in the art would be motivated to make this combination for at least the same reasons as claim 7 above. Also, this would reduce the overhead of the system as taught by Bhattacharya (Bhattacharya Page 16 Line 13).
With regards to claim 18, Tredak teaches all of the limitations of claim 9 above. Tredak further teaches the generated random matrix (A) (Tredak [0009]: dividing the N elements into K sections based on indexes of the N elements; (4) assigning K execution threads for processing the K sections, wherein each execution thread corresponds to a respective section; (5) computing respective second values of the N elements by the K execution threads in parallel in accordance with a recursion relationship representable as a.sub.i+N=f(a.sub.i, a.sub.i+c, a.sub.i+M)).
Tredak fails to teach further comprising: participating in a public-private key protocol; generating a private-key; and computing a public-key based on the private-key, wherein the computation comprises a noisy multiplication between [the generated random matrix (A)] and the private-key.
However, Bhattacharya teaches further comprising: participating in a public-private key protocol; (Bhattacharya Page 2 Lines 5-8: Cryptographic key-encapsulation (KEM) schemes use asymmetric cryptography to establish a shared secret among two parties, using a publicly known (e.g., public-key) and a secretly-owned (e.g., secret-key) value for each party)
generating a private-key; (Bhattacharya Page 3 Line 15: generate a private key polynomial)
and computing a public-key based on the private-key, (Bhattacharya Page 3 Line 17-23: generate a public key polynomial by computing a polynomial product between the shared polynomial and the private key polynomial modulo the first modulus obtaining a polynomial product, scaling coefficients of the polynomial product down to a second modulus, a scaled coefficient being equal to the unsealed coefficient multiplied with the second modulus, divided by the first modulus and rounded to the nearest integer)
wherein the computation comprises a noisy multiplication between [the generated random matrix (A)] and the private-key (Bhattacharya Page 3 Line 17-23: generate a public key polynomial by computing a polynomial product between the shared polynomial and the private key polynomial modulo the first modulus obtaining a polynomial product, scaling coefficients of the polynomial product down to a second modulus, a scaled coefficient being equal to the unsealed coefficient multiplied with the second modulus, divided by the first modulus and rounded to the nearest integer (the rounding making it a noisy multiplication)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak with the public-private key protocol as taught by Bhattacharya. One of ordinary skill in the art would be motivated to make this combination because it would increase the flexibility of the system as the random number generator could be used for the public-private key protocol as well as other uses of a modified MT19937 generator. Also, because of the rounding down operation, an attack who observes traffic between the first node and the second node will not be able to reconstruct the private polynomials used by the nodes, increasing the security of the system as taught by Bhattacharya (Bhattacharya Page 4 Lines 28-30).
With regards to claim 19, Tredak in view of Bhattacharya teaches all of the limitations of claim 7 above. Tredak further teaches wherein the generation device [and the second device are arranged to generate] the random matrix [from the same seed] (Tredak [0009]: a computing system comprises: a memory; a processor; a non-transient computer-readable recording medium storing pseudo-random number generator program… arranging the N elements into a matrix comprising x rows and a plurality of columns… computing respective second values of the N elements by the K execution threads in parallel).
Tredak fails to teach further comprising: participating in a public-private key protocol with a second device; computing a raw shared key using a public-key of the second device and the private-key, wherein the computation comprises a multiplication, [wherein the generation device] and the second device are arranged to generate the [random matrix] from the same seed.
However, Bhattacharya teaches further comprising: participating in a public-private key protocol with a second device; (Bhattacharya Page 2 Lines 5-8: cryptographic key-encapsulation (KEM) schemes use asymmetric cryptography to establish a shared secret among two parties, using a publicly known (e.g., public-key) and a secretly-owned (e.g., secret-key) value for each party; Bhattacharya Page 3 Lines 26-27: Send the public key polynomial of the first network node to the second network node)
computing a raw shared key using a public-key of the second device and the private-key, (Bhattacharya Page 3 Lines 28-30: receive a public key polynomial of the second network node, compute a raw key polynomial as a polynomial product between the received public key of the second node and the private key polynomial of the first network node)
wherein the computation comprises a multiplication, (Bhattacharya Page 3 Lines 28-30: receive a public key polynomial of the second network node, compute a raw key polynomial as a polynomial product between the received public key of the second node and the private key polynomial of the first network node)
[wherein the generation device] and the second device are arranged to generate the [random matrix] from the same seed (Bhattacharya Page 16 Lines 15-17: After receiving the seed, the first and second network node may use it to generate the polynomial a in any of the above ways. The same random seed is used to seed a deterministic pseudo random number generator).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Tredak in view of Bhattacharya with the public-private key protocol as taught by Bhattacharya. One of ordinary skill in the art would be motivated to make this combination for at least the same reasons as claim 7 above. Also, this would reduce the overhead of the system as taught by Bhattacharya (Bhattacharya Page 16 Line 13).
Allowable Subject Matter
Claims 12 and 15 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 101, 35 U.S.C. 112, and the objections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
While prior art teaches of choosing the number of parallel processes, it fails to teach that that number is equal to the product of a register size divided by a random number state size multiplied by a number cores of the processor system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151