Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed July 29th, 2026 (“A...”), in which: claims 1, 3 – 5, 8 – 9, 11, 13, and 18 are amended; claims 2 and 7 are cancelled; no new claims are added; and the rejections of the claims are traversed. Claims 1, 3 – 5, 8 – 11, 18 – 20, and 22 – 23 are currently pending an Office Action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3 – 5, 8 – 11, 18 – 20, and 22 – 23 have been fully considered and but not found to be allowable in view of Wang et al. (WO 2021190508 A1; publication date 09/30/2021). This additional Non-Final Rejection is provided herein.
Rejections
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 5, 8 – 11, 18, 22 – 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (WO 2021190508 A1).
Regarding independent Claim 1, Wang teaches a display panel (the display substrate shown in Figs. 30A – 30B and 33 – 35C), comprising:
a substrate (Figs. 33 – 35C; substrate 110);
a circuit structure layer (Figs. 33 – 35C; section of the disclosed display substrate including conductive layers 120 – 160; such that the examiner is interpreting layers 120 – 160 to be a circuit structure layer) located on a side of the substrate (Fig. 34) and including a plurality of pixel driving circuits (Figs. 33 and 34; plurality of pixel driving circuits 265. See pg. 81 of the provided translation); the plurality of pixel driving circuits being arranged in a first direction (row extension direction, i.e., Fig. 33; first direction) to constitute pixel driving circuit rows (Fig. 33. See pgs. 81 – 83 of the provided translation), and the pixel driving circuit rows being sequentially arranged in a second direction (column extension direction, i.e., Fig. 33; second direction); the first direction intersecting the second direction (Fig. 33);
a first electrode layer (Fig. 34; anode 175) located on a side of the circuit structure layer away from the substrate (Fig. 34) and including a plurality of first electrodes (pgs. 85 – 86 teaches anodes 1751 – 1754); a first electrode being electrically connected to a pixel driving circuit (Fig. 34 shows anode 175 connected to second conducive layer 160); and
a pixel definition layer (Fig. 34; pixel defining layer 190) located on a side of the first electrode layer away from the substrate (Fig. 34) and having a plurality of pixel openings (Fig. 34; plurality of openings 195. See pgs. 85 – 86 of provided translation) therein; a pixel opening exposing at least a portion of a respective first electrode (Fig. 34 shows an opening from the plurality of opening 196 to expose first electrode layer 175);
wherein the plurality of pixel driving circuits each include a driving transistor (Pg. 81 teaches each pixel driving circuit 265 includes a functional thin film transistor, such as a compensating thin film transistor T3. The plurality of pixel driving circuits 265 include a first pixel driving circuit 2657 and a second pixel driving circuit 2658 that are adjacent to each other) and a data compensation transistor (Pg. 81 teaches each pixel driving circuit 265 includes a functional thin film transistor, such as a compensating thin film transistor T3. The plurality of pixel driving circuits 265 include a first pixel driving circuit 2657 and a second pixel driving circuit 2658 that are adjacent to each other);
an orthographic projection of a first electrode of at least one first electrode on the substrate at least partially overlaps with both of an orthographic projection, on the substrate, of a gate of a data compensation transistor (See pgs. 81 – 83 of the provided translation) in a pixel driving circuit corresponding to the first electrode of the at least one first electrode (See pgs. 81 – 83 of the provided translation) and an orthographic projection, on the substrate, of a gate of a data compensation transistor in at least one pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode of the at least one first electrode (Pgs. 81 – 83 teaches orthographic projections of a channel region of the compensating thin film transistor T3 in the first pixel driving circuit 2657 and a channel region, including associated gates, of the compensating thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 both overlap the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110. See Figs. 33 – 35B);
an orthogonal projection, on the substrate, of a pixel opening corresponding to the first electrode of the at least one first electrode is spaced apart from the orthographic projection, on the substrate, of the gate of the data compensation transistor in the pixel driving circuit corresponding to the first electrode of the at least one first electrode (See Fig. 35A – 35C which corresponds to lines MM, NN, and QQ, respectively. Also see at least pg. 88 of the provided translation); and
a distance, in the first direction, between the data compensation transistor corresponding to the first electrode of the at least one first electrode and a data compensation transistor in one of the at least one pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode of the at least one first electrode is greater than a dimension, in the first direction, of a pixel opening corresponding to the first electrode of the at least one first electrode (Fig. 33; pixel electrode 1754 fully overlaps a gate electrode of T3, i.e., a data compensation transistor, in the circuit 2657 and partially overlaps the gate electrode of T2 in pixel driving circuit 2658. These overlapping portions lie outside, i.e., are spaced apart more than the dimension of, the pixel opening 195, visible as a solid line inside the pixel electrode 1754);
wherein the plurality of pixel openings are arranged in a plurality of rows (Figs. 33 and 36. See pgs. 85 – 86) and a plurality of columns (Figs. 33, 35A, 35B, and 36. See pgs. 85 – 86), and two adjacent rows of pixel openings are staggered from one another in the first direction (Figs. 33 and 36);
in two adjacent rows of pixel openings, a row of pixel openings (pgs. 85 – 86; e.g., one opening group from the plurality of opening groups 1950) include first pixel openings (pgs. 85 – 86; e.g., first opening 1951) and second pixel openings (pgs. 85 – 86; e.g., fourth opening 1954) that are alternately arranged in the first direction (Figs. 33, 35A, 35B, and 36), and another row of pixel openings (Fig. 36; row of second openings 1952 and third openings 1953) include third pixel openings (pgs. 85 – 86; e.g., third opening 1953 or second opening 1952) sequentially arranged in the first direction (Fig. 33);
in two adjacent columns of pixel openings, a column of pixel openings (pgs. 85 – 86; e.g., another one opening group from the plurality of opening groups 1950) include first pixel openings (pgs. 85 – 86; e.g., first opening 1951) and second pixel openings (pgs. 85 – 86; e.g., fourth opening 1954) that are alternately arranged in the second direction, and another column of pixel openings include third pixel openings (pgs. 85 – 86; e.g., third opening 1953 or second opening 1952) sequentially arranged in the second direction (Fig. 33); and
an area of a first pixel opening is less than an area of a second pixel opening, and the area of the first pixel opening is greater than an area of a third pixel opening (See pgs. 85 – 86; wherein first opening 1951 corresponds to electrode 1751; second opening 1952 corresponds to electrode 1752; third pixel opening 1953 corresponds to electrode 1753; and fourth pixel opening 1954 corresponds to electrode 1754. Further, Fig. 33 shows an area of electrode 1754 > 1751 > (1753 or 1752), such that 1954 > 1951 > (1953 or 1952)), wherein
an orthographic projection, on the substrate, of a first electrode corresponding to the first pixel opening at least partially overlaps with both of an orthographic projection, on the substrate, of a gate of a data compensation transistor in a pixel driving circuit corresponding to the first electrode that corresponds to the first pixel opening (Fig. 33 shows overlaps of the first electrode with the gate of the transistor T3), and an orthographic projection, on the substrate, of a gate of a data compensation transistor in at least one pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode that corresponds to the first pixel opening (Fig. 33 shows overlaps of the first electrode with the gate of the adjacent transistor T3 ); and/or
an orthographic projection, on the substrate, of a first electrode corresponding to the second pixel opening at least partially overlaps with both of an orthographic projection, on the substrate, of a gate of a data compensation transistor in a pixel driving circuit corresponding to the first electrode that corresponds to the second pixel opening (Fig. 33), and an orthographic projection, on the substrate, of a gate of a data compensation transistor in at least one pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode that corresponds to the second pixel opening (Fig. 33).
Regarding dependent Claim 5, Wang teaches the display panel according to claim 1; however, they remain silent wherein
in a same row of a pixel openings, a center of a first pixel opening and a center of a second pixel opening have a distance in the second direction therebetween (Fig. 36); or
in a same row of pixel openings, a center of a first pixel opening and a center of a second pixel opening have a distance in the second direction therebetween, and the distance is less than or equal to half of a dimension of the first pixel opening in the second direction.
Regarding dependent Claim 8, Wang teaches the display panel according to claim 1, wherein
an orthogonal projection of the first pixel opening on the substrate is spaced apart from an orthographic projection, on the substrate, of a gate of a data compensation transistor in a pixel driving circuit corresponding to the first pixel opening (Figs. 33 and 36; pixel openings 1951,1952, 1953, and 1954 are arranged in crossing directions and first opening 1951 overlaps the gates of T5 and T7 as shown in Fig. 30A)); and/or
an orthogonal projection of the third pixel opening on the substrate is spaced apart from an orthographic projection, on the substrate, of a gate (Fig. 30B; see gate layer 130) of a data compensation transistor in a pixel driving circuit corresponding to the third pixel opening (see spacing of the an orthogonal projection of the third pixel opening relative to the gate layer 130 from Fig. 30B).
Regarding dependent Claim 9, Wang teaches the display panel according to claim 1, wherein
the plurality of pixel openings include first groups of pixel openings and a second group of pixel openings (Fig. 36; see excerpt below), a first group of pixel openings includes first pixel openings and third pixel openings that are alternately arranged in a third direction (Fig. 36; see excerpt below), and a second group of pixel openings (Fig. 36; see excerpt below) includes second pixel openings and another third pixel openings that are alternately arranged in the third direction (Fig. 36; see excerpt below); the third direction intersects the fourth direction (Fig. 36);
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wherein in a first group of pixel openings, an orthographic projection, on the substrate, of a first electrode corresponding to a first pixel opening at least partially overlaps with an orthographic projection, on the substrate, of a gate of a data compensation transistor in a pixel driving circuit corresponding to a third pixel opening adjacent to the first pixel opening (Fig. 33 wherein the first electrode of a first pixel electrode overlaps with first gate electrode layer 130); and
in a second group of pixel openings, an orthographic projection, on the substrate, of a first electrode corresponding to a second pixel opening at least partially overlaps with an orthographic projection, on the substrate, of a gate of a data compensation transistor corresponding to another third pixel opening adjacent to the second pixel opening (Fig. 33 wherein the first electrode of the second pixel overlaps with first gate electrode layer 130/140).
Regarding dependent Claim 10, Wang teaches the display panel according to claim 9, wherein
orthographic projections, on the substrate, of two first electrodes respectively corresponding to a first pixel opening and a second pixel opening that are adjacent to each other at least partially overlap with orthographic projections, on the substrate, of gates of data compensation transistors respectively corresponding to two third pixel openings that are located on a same side of the first pixel opening and the second pixel opening that are adjacent to each other, respectively (Figs. 30B and 33).
Regarding dependent Claim 11, Wang teaches the display panel according to claim 1, wherein
the display panel has a display region (examiner is considering Fig. 33 to be a display region of the display substrate); pixel openings closest to a border of the display region includes at least one row of pixel openings including first pixel openings and second pixel openings that are alternately arranged in the first direction (Fig. 33), and/or at least one column of pixel openings including first pixel openings and second pixel openings that are alternately arranged in the second direction (Fig. 33); and/or
the first pixel opening is configured to define an effective light-emitting regions of first-color light (See pg. 83 and pg. 84 of provided translation with the discussion relative to the plurality of first electrodes; wherein a first color may be red), the second pixel opening is configured to define an effective light-emitting region of second-color light (See pg. 83 and pg. 84 of provided translation with the discussion relative to the plurality of second electrodes; wherein a second color may be blue), and the third pixel opening is configured to define an effective light-emitting region of third-color light (See pg. 83 and pg. 84 of provided translation with the discussion relative to the plurality of third electrodes; wherein a third color may be green); the first-color light is red light, the second-color light blue light, and the third-color light is green light (see above).
Regarding dependent Claim 18, Wang teaches the display panel according to claim 1, further comprising:
a first planarization layer (Fig. 34; first planarization layer 241), a conductive connection layer (Fig. 34; second conductive layer 160) and a second planarization layer that (Fig. 34; second planarization layer 242) are located between the circuit structure layer and the first electrode layer (Fig. 34) and sequentially away from the substrate (Fig. 34); wherein the first planarization layer has a plurality of first via holes therein (Fig. 34; first via hole H1. Also see Fig. 33), the conductive connection layer includes a plurality of conductive portions (Fig. 34; connection electrode 161. Also see Fig. 33), and the second planarization layer has a plurality of second via holes therein (Fig. 34; second via hole H2. Also see Fig. 33);
the display panel has a plurality of sub-pixel regions (Fig. 33 shows a plurality of sub-pixel regions); the plurality of sub-pixel regions are in a one-to-one correspondence with the plurality of pixel driving circuit (pg. 81 of provided translation); in a sub-pixel region,
a first electrode is electrically connected to a conductive portion through a second via hole (Fig. 34), and the conductive portion is electrically connected to a pixel driving circuit through a first via hole (Fig. 34); and
a minimum distance between an orthogonal projection of a border of the first via hole on the substrate (Fig. 34) and an orthogonal projection of a pixel opening corresponding to the first electrode electrically connected to the conductive portion on the substrate (Fig. 34) is less than a minimum distance between an orthogonal projection of a border of the second via hole on the substrate (Fig. 34) and the orthogonal projection of the pixel opening corresponding to the first electrode electrically connected to the conductive portion on the substrate (Fig. 34).
Regarding dependent Claim 22, Wang teaches the display panel according to claim 18, wherein
in a same column of pixel openings, first via holes respectively corresponding to all pixel openings (Fig. 33 shows that between two rows, the first vias, i.e., 2415, 2416, 2417, etc., line up in the vertical direction in the same position between the two rows) and second via holes respectively corresponding to all the pixel openings (Fig. 33 shows that between two rows, the second vias, i.e., 2421, 2422, 2423, etc., line up in the vertical direction in the same position between the two rows) are arranged on a straight line extending in the second direction.
Regarding dependent Claim 23, Wang teaches:
a display apparatus (Fig. 38), comprising:
the display panel according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (WO 2021190508 A1), and further in view of Lee et al. (US 20210241671 A1).
Regarding dependent Claim 3, Wang teaches the display panel according to claim 1, wherein
in any row of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has an equal distance to two second pixel openings adjacent to the any first pixel opening; and
in any column of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has distances, that are not equal, to two second pixel openings adjacent to the any first pixel opening, respectively.
However, in the same field of endeavor, Lee teaches in Fig. 10 first openings corresponding to red pixels Pmr, second openings corresponding to blue pixels Pmb, and third openings corresponding to green pixel Pmg. In Fig. 10, Lee teaches in any row of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has an equal distance to two second pixel openings adjacent to the any first pixel opening; and in any column of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has distances, that are not equal, to two second pixel openings adjacent to the any first pixel opening, respectively (See excerpt of Fig. 10 below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Wang’s pixel pitch to include Lee’s display device feature wherein in any row of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has an equal distance to two second pixel openings adjacent to the any first pixel opening; and in any column of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has distances, that are not equal, to two second pixel openings adjacent to the any first pixel opening, respectively, because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, Lee’s pixel layout permits light to pass through the display panel where the spacing is increased between pixels in a column; such that a sensor, e.g., a camera may be placed in this region of the display device. This known benefit in Lee’s display device is applicable to Wang’s display device as they both share characteristics and capabilities, namely, they are directed to display devices that may be combined with sensors, such as a camera. Therefore, it would have been recognized that modifying Wang’s display device to include Lee’s display device feature wherein in any row of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has an equal distance to two second pixel openings adjacent to the any first pixel opening; and in any column of pixel openings including first pixel openings and second pixel openings that are alternately arranged, any first pixel opening has distances, that are not equal, to two second pixel openings adjacent to the any first pixel opening, respectively, would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate Lee’s pixel opening spacing in display devices and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Regarding dependent Claim 19, Wang teaches the display panel according to claim 18, wherein
in the two adjacent rows of pixel openings, first via holes respectively corresponding to all pixel openings are arranged on a straight line extending in the first direction (Fig. 33), and second via holes respectively corresponding to all the pixel openings are alternately arranged, in the first direction (Fig. 33), …
However, Wang remains silent regarding the second via holes:
… on both sides of the straight line extending in the first direction.
However, in the same field of endeavor, Lee teaches a display device wherein a drain electrode of a transistor is connected to an anode electrode of the OLED via a contact metal CM coupled to a contact hole 48 (first via holes) and a via hole VIA (second via holes) coupled to the contact metal CM ([0092]. Also See Figs. 6 – 7). The via holes, e.g., VIA_R, VIA_G, and VIA_B (Fig. 6) connect the anode electrode of the OLED to a contact pad/metal layer through a second planarization layer (Fig. 8), similar to both Wang and the instant application. Further, in Fig. 6, Lee shows the via layout for a display device, wherein the relationship exists between two adjacent rows of pixels such that second via holes respectively corresponding to all the pixel openings are alternately arranged, in the first direction, on both sides of the straight line extending in the first direction (Fig. 6. See excerpt below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Wang’s display device to include Lee’s display device feature wherein second via holes respectively corresponding to all the pixel openings are alternately arranged, in the first direction, on both sides of the straight line extending in the first direction, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Lee’s display device feature is comparable to Wang’s because they both pertain to RBG pixel layouts. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Wang’s pixel circuitry layout to include Lee’s display device feature wherein second via holes respectively corresponding to all the pixel openings are alternately arranged, in the first direction, on both sides of the straight line extending in the first direction with the predictable result of providing a driving voltage to a plurality of pixels spaced apart in different rows and columns (Lee: [0078]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (WO 2021190508 A1), and further in view of Lee et al. (US 20210241671 A1) and Yue et al. (US 20220069031 A1).
Regarding dependent Claim 4, Wang teaches the display panel according to claim 1; however, Wang remain silent wherein
in two adjacent columns of pixel openings each including first pixel openings and second pixel openings, geometrical centers of two first pixel openings and two second pixel openings that are adjacent to one another, in which a first pixel opening and a second pixel opening are in a column of pixel openings and another first pixel opening and another second pixel opening are in another column of pixel openings, are connected to be in a shape of a trapezoid.
However, in the same field of endeavor, Yue teaches a pixel opening configuration wherein in two adjacent columns of pixel openings each including first pixel openings and second pixel openings, geometrical centers of two first pixel openings and two second pixel openings that are adjacent to one another, in which a first pixel opening and a second pixel opening are in a column of pixel openings and another first pixel opening and another second pixel opening are in another column of pixel openings, are connected to be in a shape of a trapezoid (Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Wang’s display device to include Yue’s display device feature wherein in two adjacent columns of pixel openings each including first pixel openings and second pixel openings, geometrical centers of two first pixel openings and two second pixel openings that are adjacent to one another, in which a first pixel opening and a second pixel opening are in a column of pixel openings and another first pixel opening and another second pixel opening are in another column of pixel openings, are connected to be in a shape of a trapezoid, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yue’s pixel layout is comparable to Wang’s pixel layout because they both pertain to RBG pixel layouts. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Wang’s display device to include Yue’s display device feature wherein in two adjacent columns of pixel openings each including first pixel openings and second pixel openings, geometrical centers of two first pixel openings and two second pixel openings that are adjacent to one another, in which a first pixel opening and a second pixel opening are in a column of pixel openings and another first pixel opening and another second pixel opening are in another column of pixel openings, are connected to be in a shape of a trapezoid with the predictable result of decrease color fringing in the displayed image (Yue: [0060]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (WO 2021190508 A1), and further in view of Lee et al. (US 20210241671 A1) and Song et al. (US 20210202633 A1).
Regarding dependent Claim 20, Wang, further in view of Lee, teach the display panel according to claim 19, wherein
in the two adjacent rows of pixel openings, the first via holes respectively
corresponding to all the pixel openings are each located at a same position in a respective pixel driving circuit (Wang: Fig. 33 shows that between two rows, the first vias, i.e., 2415, 2416, 2417, etc., line up in the vertical direction in the same position between the two rows); and
the second via holes respectively corresponding to the first pixel openings and second via holes respectively corresponding to the second pixel openings are each located at a same position in a respective pixel driving circuit (Wang: Fig. 33 shows that between two rows, the second vias, i.e., 2421, 2422, 2423, etc., line up in the vertical direction in the same position between the two rows); and/or
… the display panel further comprises light-emitting control signal lines (Emission control line 133 as disclosed in at least pg. 93 and pg. 101 of the provided translation) located in a first gate layer (Wang: Fig. 34; first gate electrode layer 130. Also see Fig. 30B for more context) and extending in the first direction (Wang: Fig. 34), an orthogonal projection of each first via hole on the substrate has an approximately equal overlapping area with an orthographic projection of a respective light-emitting control signal line on the substrate (Wang: From Fig. 33, as the first vias in a row are located on the same line, they each have approximately equal overlapping area with an orthographic projection of a respective light-emitting control signal line on the substrate).
However, Wang remains silent regarding:
… in the two adjacent rows of pixel openings, positions of the first via holes respectively corresponding to all the pixel openings are different in the second direction, …
However, in the same field of endeavor, Song teaches a similar display device wherein for each pixel their first holes (Fig. 6I; contact hole 40. Also see Fig. 9) and second via holes (Fig. 6I; contact hole 40’. Also see Fig. 9) overlap. Song shows that between pixel rows (Fig. 6I) that positions of the first via holes respectively corresponding to all the pixel openings are different in the second direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Wang’s display device to include Song’s display device feature wherein positions of the first via holes respectively corresponding to all the pixel openings are different in the second direction, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Song’s display device feature is comparable to Wang’s display device because they both pertain to RBG pixel layouts. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Wang’s display device circuitry to include Song’s display device feature wherein positions of the first via holes respectively corresponding to all the pixel openings are different in the second direction with the predictable result of forming device circuitry wherein the spacing between pixels is varied/shifted.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20170011685 A1 previously relied upon.
US 20220285472 A1 previously relied upon.
US 20180183008 A1 discloses similar device structures, layers, and layouts.
US 12426445 B1 discloses similar device features.
US 20200357325 A1 discloses similar pixel layouts.
US 12284875 B2 discloses similar pixel layouts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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