DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Remarks/Arguments
With respect to the rejection of claim 1 under 35 USC 103, Applicant's arguments filed 01/05/2026 have been fully considered but they are not persuasive.
Applicant argues, see page 2,
Kvatinsky does not teach a solution to make VCR stable and therefore useful.
In response to applicant’s argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., a solution to make VCR stable and therefore useful) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further argues, see page 2:
Examiner argues that Kvatinsky does teach that the third memristor is initiated in the low resistive state etc. However, in Kvatinsky, this particular state is only true for certain logic gates, namely NOR and NAND gates. Other gates are set up differently, So there is no indication that this configuration is especially important beyond being a specific configuration for NOR and NAND gates.
In response to applicant’s argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., beyond being a specific configuration for NOR and NAND gates) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further argues, see page 2,
Thus, the skilled person would be unable to solve the problem posed in AAPA paragraph 91, especially in view of the fact that NOR and NAND gates are already available in the MAGIC family. The interest is more in OR, XOR and NIMP gates.
Thus, taking the whole of paragraph 91 into account, the skilled person would not be able to solve the stability problem and the presence of the stability problem would prevent him/her from combining VCR with the specific NOR and NAND implementations in Kvatinsky.
Examiner respectfully disagrees. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, one having ordinary skill in the art would apply VCM devices to the teachings of Kvatinsky in order to take advantages of fast switching, relatively high endurance and long retention properties of VCM as recited in the previous Office Action, see page 5, paragraph 1 (09/04/2025).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10, 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kvatinsky (US 2015/0256178 A1) in view of Applicant Admitted Prior Art (US 2023/0170909 A1, hereinafter AAPA) .
Regarding claim 1, Kvatinsky teaches a method of using memristor aided logic (MAGIC) ([0086] MAGIC, a technique to design pure memristive logic gates), the method comprising:
connecting a first memristor (Fig. 10, 300,
i
n
1
which corresponds to
M
i
,
j
+
1
) between a bit line (
X
j
+
1
) and a word line (Fig. 10,
i
t
h
line connected to the Row decoder);
connecting a second memristor (Fig. 10, 300,
i
n
2
,
M
i
,
j
) between a further bit line and said word line (Fig. 10,
i
t
h
line connected to the Row decoder);
connecting a third memristor (Fig. 10, 300, out,
M
i
,
j
-
1
) between ground (Fig. 10, see 300, the “out” memristor is connected to ground via an amplifier/driver) and said word line (Fig. 10,
i
t
h
line connected to the Row decoder), each memristor having a high resistance state and a low resistance state ([0014]
R
o
n
,
R
o
f
f
);
using respective bit lines and said word line applying logic inputs to said first and second memristors (Fig. 10, 300, applying V0 to
i
n
1
and
i
n
2
);
setting said third memristor to said low resistance state (Fig. 11B,
R
o
u
t
is low resistance state at time 0.0; Fig. 2B, [0098-0101] prior to the calculation the output memristor must be set to ‘1’; [0087] high and low resistance are considered, respectively, as logical zero and one, thus logical one is low resistance);
setting said third memristor to said low resistance value (Fig. 11B,
R
o
u
t
is low resistance state at time 0.0);
with said third memristor in said low resistance state (Fig. 11B,
R
o
u
t
is low resistance state at time 0.0; Fig. 2B, [0098-0101] prior to the calculation the output memristor must be set to ‘1’; [0087] high and low resistance are considered, respectively, as logical zero and one, thus logic one is low resistance), applying a gate voltage, said gate voltage allowing states of said first and second memristors affect said third memristor (Fig. 10, applying “Select” input to the word line, Fig. 11B, transition of
R
o
u
t
depending on in1 and in2);
using said word line, obtaining an output from said third memristor, the output depending on whether said logic inputs have set said third memristor to from said low resistance state to said high resistance state (Fig. 11B,
R
o
u
t
switches from low resistance state to high resistance state with the in1 and in2 values as shown in the figure).
Kvatinsky does not explicitly teach the method, wherein said memristors are valence change memory - VCM – devices.
AAPA teaches valence change memory (VCM) device as one of categories of resistive switching devices ([0091]).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of claimed invention to apply VCM devices as taught by AAPA to the teachings of Kvatinsky in order to take advantages of fast switching speed, relatively high endurance and long retention properties (AAPA [0091]).
Regarding Claim 2, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the method, comprising grounding the output memristor (Fig. 10, 300, out memristor is grounded).
Regarding Claim 3, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the method, the memristors having a set voltage for switching respective memristors from said low voltage state to said high voltage state, wherein the output conforms to a truth table of an OR gate (Fig. 5A, [0069] pure memristive logic OR gate 50), and wherein at least one of said logic inputs comprises said set voltage, thereby to set said third memristor to said high resistance state ([0150] switch the logical state of the output memristor to logical one).
Regarding Claim 8, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the method, wherein a plurality of memristors are arranged in a crossbar structure, the method comprising selecting three of said plurality of memristors for a required logic operation (Fig. 10, 300).
Regarding Claim 10, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the method, comprising providing said logic inputs in pulses, said pulses being of less than 5 microseconds in duration (Fig. 11B, 1.5ns).
Regarding claim 12, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
AAPA teaches a method, wherein said memristors are constructed using
T
a
2
O
5
([0091]).
Regarding claim 13, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 13 is rejected under the same rationale as claim 1 above.
Regarding claim 14, this claim has substantially the same subject matter as that in claim 12. Therefore, claim 14 is rejected under the same rationale as claim 12 above.
Regarding claim 15, all the limitations of claim 13 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the memory block, wherein said memristor based logic gate is one member of the group consisting of an OR gate, a NIMP gate and an XOR gate (Fig. 12).
Regarding claim 16, all the limitations of claim 13 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the memory block, wherein said memristor aided logic is arranged in a crossbar configuration having a plurality of said memristor based logic gate between a bit line and a word line (Fig. 10).
Regarding claim 17, all the limitations of claim 13 are taught by Kvatinsky in view of AAPA.
Kvatinsky further teaches the memory block, wherein one memristor based logic gate of said plurality of memristor-based logic gates in said crossbar configuration is one member of the group consisting of an OR gate, a NOR gate, a NIMP gate and an XOR gate (Fig. 12).
Regarding claim 18, all the limitations of claim 13 are taught by Kvatinsky in view of AAPA.
AAPA further teaches the memory block, being a Pt/
T
a
2
O
5
/
W
/
P
t
device ([0091]).
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kvatinsky (US 2015/0256178 A1) in view of Applicant Admitted Prior Art (US 2023/0170909 A1, hereinafter AAPA) as applied to claim 1 above, and further in view of Kim (K. Kim and R. Williams, “A Family of Stateful Memristor Gates for Complete Cascading Logic,” IEEE Transactions on Circuits and Systems-I, Vol. 66, No. 11, November 2019).
Regarding claim 4, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky in view of AAPA does not explicitly teach the method, wherein the memristors having a set voltage for switching respective memristors from said low voltage state to said high voltage state, and a reset voltage for switching respective memristors from said low voltage state to said high voltage state, and wherein a ratio between said set voltage and said reset voltage is less than two.
Kim teaches a method, wherein the memristors having a set voltage for switching respective memristors from said low voltage state to said high voltage state, and a reset voltage for switching respective memristors from said low voltage state to said high voltage state, and wherein a ratio between said set voltage and said reset voltage is less than two (Fig. 1(b), SET=1.5V, RESET=-2V).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Kim to the teachings of Kvatinsky in view of AAPA in order to significantly improve stateful logic computing efficiency (Kim, Abstract).
Regarding claim 5, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky in view of AAPA does not explicitly teach the method, wherein the output conforms to the truth table of a NIMP gate, the method comprising applying a first, set, voltage to a first of said input memristors and a predetermined fraction of said first, set, voltage to a second of said input memristors.
Kim teaches a method, wherein the output conforms to the truth table of a NIMP gate (Fig. 1(d)), the method comprising applying a first, set, voltage to a first of said input memristors and a predetermined fraction of said first, set, voltage to a second of said input memristors (Fig. 1(c), IV. NIMP, 0.7V, -2.1V).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Kim to the teachings of Kvatinsky in view of AAPA in order to significantly improve stateful logic computing efficiency (Kim, Abstract).
Regarding claim 6, all the limitations of claim 5 are taught by Kvatinsky in view of AAPA and Kim.
Kim further teaches the method, wherein said fraction if a third (Fig. 1(c), IV. NIMP, 0.7V, -2.1V).
Regarding claim 7, all the limitations of claim 5 are taught by Kvatinsky in view of AAPA and Kim.
Kim further teaches the method, comprising: applying a first, set, voltage to a first of said input memristors and said predetermined fraction of said first, set, voltage to a second of said input memristors; applying a first, set, voltage to said second of said input memristors and said predetermined fraction of said first, set, voltage to said first of said input memristors, thereby to provide an output corresponding to a truth table of an XOR gate (page 4351, right column, first para. Fig. 3).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kvatinsky (US 2015/0256178 A1) in view of Applicant Admitted Prior Art (US 2023/0170909 A1, hereinafter AAPA) as applied to claim 1 above, and further in view of Ramadan (US 2018/0166137 A1).
Regarding claim 9, all the limitations of claim 1 are taught by Kvatinsky in view of AAPA.
Kvatinsky in view of AAPA does not explicitly teach the method, comprising providing said logic inputs in pulses, said pulses being between 5 and 100 microseconds in duration.
Ramadan teaches a method, comprising providing said logic inputs in pulses, said pulses being between 5 and 100 microseconds in duration (Fig. 3, [0072]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the various programming method as taught by Ramadan to the teachings of Kvatinsky in view of AAPA in order to investigate how the programming pulses affect resistance of memristor cells and thus to avoid potential memristor state tuning methods that may increase area overhead dramatically, and increase energy usage as well (Ramadan, [0007]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kvatinsky (US 2015/0256178 A1) in view of Applicant Admitted Prior Art (US 2023/0170909 A1, hereinafter AAPA) as applied to claim 13 above, and further in view of Kim (K. Kim and R. Williams, “A Family of Stateful Memristor Gates for Complete Cascading Logic,” IEEE Transactions on Circuits and Systems-I, Vol. 66, No. 11, November 2019).
Regarding claim 19, all the limitations of claim 13 are taught by Kvatinsky in view of AAPA.
Kvatinsky in view of AAPA does not explicitly teach a memory block wherein a plurality of said memristor-based logic gate are connected together to provide a half-adder.
Kim teaches a memory block wherein a plurality of said memristor-based logic gate are connected together to provide a half-adder (page 4354, left column, section VI. half and full adder).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Kim to the teachings of Kvatinsky in view of AAPA in order to in order to significantly improve stateful logic computing efficiency (Kim, Abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H. Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844