DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character not mentioned in the description: “34e” as illustrated in FIG. 12. It is believed that this reference character should be amended to “34”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following minor informalities:
In paragraph [0019]: “holes 22, 24, 24” should read “holes 22, 23, 24”;
In paragraph [0022]: “Conductive bonding member 35” should read “Conductive bonding member 32”; and
In paragraph [0116]: “described below as a sixth embodiment” should read “described below as a fifth embodiment”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 – 4, 6, 8 – 11, 16, and 18 – 19, are rejected under 35 U.S.C. 102(a)(1) as being anticipated Shikano, Taketoshi, US 2010/0007026 A1 (hereinafter “Shikano”). FIG. 12 of Shikano is reproduced herein-below, for reference.
PNG
media_image1.png
248
359
media_image1.png
Greyscale
Regarding claim 1, Shikano discloses a power semiconductor apparatus (see FIG. 12 and paras. [0004], [0040] – [0049], and [0059] – [0063]: “semiconductor device”) comprising:
a conductive circuit pattern including a first main surface (see FIG. 12 and paras. [0039] and [0041], heat spreader 17: (“Heat spreader 17 has the function as a part of a wiring path and the function of promoting heat radiation by dissipation of heat generated from free wheel diode 13f and IGBT 13i…. In order to form a circuit shown in FIG. 4, wire bonding by wires 14 is performed among free wheel diode 13f, IGBT 13i, external electrode lead 16, and heat spreader 17.” (Emphasis supplied); see also MPEP 2111 regarding “broadest reasonable interpretation”);
a power semiconductor device bonded on the first main surface (see FIG. 12 and paras. [0026] – [0027], free wheel diode 13f);
a sealing member sealing the first main surface and the power semiconductor device (see FIG. 12 and paras. [0046] – [0047], mold resin portion 15);
a first conductive post filling a first hole (see FIG. 9, OPh) formed in the sealing member, and connected to the first main surface of the conductive circuit pattern (see FIG. 12 and paras. [0042] – [0044] and [0059] – [0063], main electrode portion 42hp including left-most pin 28h and rotation suppressing portion 26h, as well as joint solder portion 11h); and
a second conductive post filling a second hole (see FIG. 9, OPf) formed in the sealing member, and connected to the power semiconductor device (see FIG. 12 and paras. [0042] – [0044] and [0059] – [0063], main electrode portion 42fu including left-most pin 28f and rotation suppressing portion 26f, as well as joint solder portion 11f),
wherein the first conductive post includes a first metal pin and a first conductive bonding member (see FIG. 12 and paras. [0042] – [0044] and [0059] – [0063], left-most pin 28h / joint solder portion 11h),
the second conductive post includes a second metal pin and a second conductive bonding member (see FIG. 12 and paras. [0042] – [0044] and [0059] – [0063], right-most pin 28f / joint solder portion 11f),
the first conductive bonding member fills between a first pin side surface of the first metal pin and a first side surface of the first hole and bonds the first metal pin to the conductive circuit pattern (as illustrated in FIG. 12, note that join solder portion 11h fills between both a first pin side surface at the lower end of left-most pin 28h as well as first side surface of the first hole at the lower end of left-most pin 28h), and
the second conductive bonding member fills between a second pin side surface of the second metal pin and a second side surface of the second hole and bonds the second metal pin to the power semiconductor device (as illustrated in FIG. 12, note that join solder portion 11f fills between both a second pin side surface at the lower end of right-most pin 28f as well as second side surface of the second hole at the lower end of right-most pin 28f).
Regarding claim 3, Shikano discloses the power semiconductor apparatus of claim 1 as above, and further discloses wherein the first conductive bonding member (11h) and the second conductive bonding member (11f) are formed of solder or metal fine particle sintered body (see paras. [0037], [0038], and [0041], noting joint “solder” portions 11h and 11f).
Regarding claim 4, Shikano discloses the power semiconductor apparatus of claim 1 as above, and further discloses wherein a first cross section of the first metal pin (28h) along a first longitudinal direction of the first metal pin and a second cross section of the second metal pin (28f) along a second longitudinal direction of the second metal pin have a T shape or an I shape (as illustrated in FIG. 12, a “T shape”).
Regarding claim 6, Shikano discloses the power semiconductor apparatus of claim 1 as above, and further discloses wherein a first diameter of a first proximal end of the first hole (OPh) with respect to the first main surface is smaller than a second diameter of a first distal end of the first hole with respect to the first main surface, and the first hole positions the first metal pin (28h) in a direction normal to the first main surface, and a third diameter of a second proximal end of the second hole (OPf) with respect to the first main surface is smaller than a fourth diameter of a second distal end of the second hole with respect to the first main surface, and the second hole positions the second metal pin (28f) in the direction normal to the first main surface (as illustrated in FIG. 12).
Regarding claim 8, Shikano discloses the power semiconductor apparatus of claim 6 as above, and further discloses:
wherein the first metal pin (28h) includes a first body (referring to FIG. 12, lower, vertically-oriented end) and a first head provided at a third distal end of the first body with respect to the first main surface (referring to FIG. 12, upper, horizontally-oriented end),
the second metal pin (28f) includes a second body (referring to FIG. 12, lower, vertically-oriented end) and a second head provided at a fourth distal end of the second body with respect to the first main surface (referring to FIG. 12, upper, horizontally-oriented end),
the first hole (OPh) has a first small diameter portion accommodating the first body (referring to FIG. 12, lower, vertically-oriented end of the hole enclosing pin 28h),
the first hole has a first large diameter portion accommodating the first head (referring to FIG. 12, upper, horizontally-oriented end of the hole enclosing pin 28f),
the second hole (OPf) has a second small diameter portion accommodating the second body (referring to FIG. 12, lower, vertically-oriented end of the hole enclosing pin 28f), and
the second hole has a second large diameter portion accommodating the second head (referring to FIG. 12, upper, horizontally-oriented end of the hole enclosing pin 28f).
Regarding claim 9, Shikano discloses the power semiconductor apparatus of claim 1 as above, and further discloses wherein the sealing member (15) includes a second main surface (referring to the embodiment of FIG. 1, “SF”) away from the first main surface in a direction normal to the first main surface, and a first end portion of the first conductive post and a second end portion of the second conductive post distal from the first main surface protrude from the second main surface (as illustrated in the embodiment of FIG. 1, pins 12hp and 12fu).
Regarding claim 10, Shikano discloses the power semiconductor apparatus of claim 1, wherein the sealing member (15) includes a second main surface (referring to the embodiment of FIG. 12, “SF”) away from the first main surface in a direction normal to the first main surface, and a first end portion of the first conductive post (42hp) and a second end portion of the second conductive post (42fu) distal from the first main surface are flush with the second main surface (as illustrated in the embodiment of FIG. 12).
Regarding claim 11, Shikano discloses a method of manufacturing a power semiconductor apparatus (see FIG. 12 and paras. [0004], [0040] – [0049], and [0059] – [0063]: “method of manufacturing a semiconductor device”), the method comprising:
bonding (see para. [0041], die bonding portion 20f) a power semiconductor device (see FIG. 12 and paras. [0026] – [0027], free wheel diode 13f) on a first main surface of a conductive circuit pattern (see FIG. 12 and paras. [0039] and [0041], heat spreader 17: (“Heat spreader 17 has the function as a part of a wiring path and the function of promoting heat radiation by dissipation of heat generated from free wheel diode 13f and IGBT 13i…. In order to form a circuit shown in FIG. 4, wire bonding by wires 14 is performed among free wheel diode 13f, IGBT 13i, external electrode lead 16, and heat spreader 17.” (Emphasis supplied); see also MPEP 2111 regarding “broadest reasonable interpretation”);
providing a sealing member sealing the first main surface and the power semiconductor device (see FIG. 12 and paras. [0046] – [0047], mold resin portion 15) and having a first hole and a second hole (see FIGS. 7 – 9 and paras. [0042] – [0046]);
forming a first conductive post in the first hole (see FIGS. 9 and 12 and paras. [0046] – [0063], main electrode 42hp); and
forming a second conductive post in the second hole (see FIGS. 9 and 12 and paras. [0046] – [0063], main electrode 42fu), wherein
providing the sealing member includes placing the conductive circuit pattern having the power semiconductor device bonded thereon in a cavity of a mold having a first mold pin and a second mold pin (see FIGS. 7 – 8 and paras. [0042] – [0045], pins 22, lower die 23, upper die 24),
injecting a sealing resin material into the cavity, and curing the sealing resin material to obtain the sealing member (see paras. [0045] – [0046]),
the first mold pin being arranged corresponding to the first hole (see FIGS. 7 – 8 and paras. [0042] – [0045], left pin 22),
the second mold pin being arranged corresponding to the second hole (see FIGS. 7 – 8 and paras. [0042] – [0045], right pin 22),
the first conductive post fills the first hole and is connected to the first main surface of the conductive circuit pattern (see FIGS. 9 and 12, and paras. [0047] and [0059] – [0063], main electrode 42hp),
the second conductive post fills the second hole and is connected to the power semiconductor device (see FIGS. 9 and 12, and paras. [0047] and [0059] – [0063], main electrode 42fu),
the first conductive post includes a first metal pin and a first conductive bonding member (see FIG. 12 and paras. [0054] and [0059] – [0063], pin 28h and solder 11h),
the second conductive post includes a second metal pin and a second conductive bonding member (see FIG. 12 and paras. [0054] and [0059] – [0063], pin 28f and solder 11f),
the first conductive bonding member fills between a first pin side surface of the first metal pin and a first side surface of the first hole and bonds the first metal pin to the conductive circuit pattern (as illustrated in FIG. 12, note that join solder portion 11h fills between both a first pin side surface at the lower end of left-most pin 28h as well as first side surface of the first hole at the lower end of left-most pin 28h), and
the second conductive bonding member fills between a second pin side surface of the second metal pin and a second side surface of the second hole and bonds the second metal pin to the power semiconductor device (as illustrated in FIG. 12, note that join solder portion 11f fills between both a second pin side surface at the lower end of right-most pin 28f as well as second side surface of the second hole at the lower end of right-most pin 28f).
Regarding claim 16, Shikano discloses the method of claim 11 as above, and further discloses wherein a first cross section of the first metal pin (28h) along a first longitudinal direction of the first metal pin and a second cross section of the second metal pin (28f) along a second longitudinal direction of the second metal pin have a T shape or an I shape (as illustrated in FIG. 12, a “T shape”).
Regarding claim 18, Shikano discloses the method of claim 11 as above, and further discloses wherein a first diameter of a first end of the first hole (OPh) proximal to the first main surface is smaller than a second diameter of a second end of the first hole distal from the first main surface, and the first hole positions the first metal pin (28h) in a direction normal to the first main surface, and a third diameter of a third end of the second hole (OPf) proximal to the first main surface is smaller than a fourth diameter of a fourth end of the second hole distal from the first main surface, and the second hole positions the second metal pin (28f) in the direction normal to the first main surface (as illustrated in FIG. 12).
Regarding claim 19, Shikano discloses a power conversion apparatus (see FIGS. 2 – 5 and paras. [0025] – [0039] and paras. [0059] – [0063] comprising:
a main conversion circuit including the power semiconductor apparatus according to claim 1 (see rejection of claim 1, supra), the main conversion circuit converting input power and outputting the converted power (see FIG. 4 and paras. [0034] – [0035]; and
a control circuit to output a control signal for controlling the main conversion circuit to the main conversion circuit (see FIG. 4 and paras. [0034] – [0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shikano as applied to claim 1, above, and further in view of Ikenouchi, Shun, US 2018/0366449 A1 (hereinafter “Ikenouchi”).
Regarding claim 2, Shikano discloses the power semiconductor apparatus of claim 1 as above, but does not explicitly disclose wherein the first metal pin (28h) and the second metal pin (28f) are formed of copper, aluminum, gold, or silver. Rather, it is only noted in Shikano that the pins be a conductive metal, throughout the disclosure. In a related art, Ikenouchi discloses a power semiconductor apparatus (see, e.g., FIG. 1 of Ikenouchi, semiconductor device 100) including conductive posts 5, 7, 8, and 9 made of copper or aluminum (see paras. [0075] and [0078]).
It is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415 – 21 (2007); MPEP 2143(I)(A).) Because both Shikano and Ikenouchi disclose similar power semiconductor devices using similar placed conductive pins / posts, it would have been readily predictable to person having ordinary skill in the art to have combined the particular type of metal used in Ikenouchi with the disclosure of Shikano such that Shikano would have used copper or aluminum for its pins 28h, 28f. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the disclosures of Shikano and Ikenouchi in the manner set forth above.
Claims 5 and 7, and claim 17, respectively, are rejected under 35 U.S.C. 103 as being unpatentable over Shikano as applied to claims 1 and 11, above, respectively, and further in view of Nishida, Yuhei, et al., US 2019/0189529 A1 (hereinafter “Nishida”).
Regarding claims 5 and 17, respectively, Shikano discloses the power semiconductor apparatus (and method of manufacturing) of claims 1 (and 11) as above, but does not explicitly disclose wherein a first cross section of the first metal pin (28h) along a first longitudinal direction of the first metal pin and a second cross section of the second metal pin (28f) along a second longitudinal direction of the second metal pin have a tapered shape becoming narrower toward the first main surface or a serrated shape becoming narrower toward the first main surface. Rather, its pins appear cylindrical with constant or stepped diameters and not “tapered” (see, e.g., FIGS. 1 and 12 of Shikano). In a related art, however, Nishida discloses a similar power semiconductor apparatus (manufacturing methods) including pins 7a, 7b (see, e.g., FIG. 1 and paras. [0040] – [0056] of Nishida). In one embodiment, its pins 7a are tapered (see FIG. 8A and paras. [0091] – [0094] of Nishida).
It is prima facie obvious to make a simple substitution of one known element for another to obtain predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(B).) Because both Shikano and Nishida disclose similar power semiconductor devices using similar placed conductive pins / posts, it would have been readily predictable to person having ordinary skill in the art to have substituted the known shape of one pin for another, namely, those of Shikano (28h, 28f) and Nishida (7a) as described above, while predictably expecting similar functionality. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have substituted the pin configurations in the respective disclosures of Shikano and Nishida in the manner set forth above.
Regarding claim 7, Shikano discloses the power semiconductor apparatus of claim 6 as above, and but does not explicitly disclose wherein the first hole (OPh) and the second hole (OPf) have a tapered shape becoming narrower toward the first main surface. Given that the holes (OPh, OPf) are complimentary in shape to the pins (28h, 28f) in Shikano, it would have been a predictable and straightforward modification to change the shape of the holes to similarly accommodate the reshaped pins as discussed above in connection with claims 5 and 17, pursuant to an “obvious to try” rationale, namely choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. (See KSR v. Teleflex, supra; MPEP 2143(I)(E).) Stated alternatively, a person having ordinary skill in the art would immediately see the alternate, straightforward possibilities of leaving the holes OPh, OPf in the same shape, or alternatively configuring them with a tapered end to match the shape of the pin 28h, 28f to the shape of the holes. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have substituted the pin configurations in the respective disclosures of Shikano and Nishida in the manner set forth above.
Claims 12 – 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shikano as applied to claim 11, above, and further in view of Nakamura, Yoko, et al., US 2015/0179551 A1 (hereinafter “Nakamura”)
Regarding claim 12, Shikano discloses the method of claim 11 as above, but does not explicitly disclose wherein:
forming the first conductive post (42hp) in the first hole (OPh) includes providing a first conductive bond precursor in paste or powder form in the first hole, bringing the first metal pin (28h) into contact with the first conductive bond precursor to arrange the first conductive bond precursor between the first metal pin and the conductive circuit pattern and between the first pin side surface of the first metal pin and the first side surface of the first hole, and heating and cooling the first conductive bond precursor to change the first conductive bond precursor into the first conductive bonding member (11h), and
forming the second conductive post (42fu) in the second hole (OPf) includes providing a second conductive bond precursor in paste of powder form in the second hole, bringing the second metal pin (28f) into contact with the second conductive bond precursor to arrange the second conductive bond precursor between the second metal pin and the power semiconductor device and between the second pin side surface of the second metal pin and the second side surface of the second hole, and heating and cooling the second conductive bond precursor to change the second conductive bond precursor into the second conductive bonding member (11f).
In a related art concerning the manufacturing of similar power semiconductor devices wherein pins / posts are joined to a substrate / semiconductor with solder, Nakamura discloses the aforementioned claim limitations (see Nakamura, FIG. 5C and para. [0040]: “the first conductive post 18a and second conductive posts 18b fixed in the printed substrate 14 are introduced into a reflow furnace in a state wherein the first conductive post 18a and second conductive posts 18b are in contact with the paste-form solder 21, and a reflow process is carried out.”).
As noted above, it is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(A).) Because both Shikano and Nakamura disclose similar power semiconductor devices using similar placed conductive pins / posts, it would have been readily predictable to person having ordinary skill in the art to have combined the particular type of solder paste and reflow process of Nakamura with the disclosure of Shikano such that Shikano would have used the same paste / reflow process for its pins 28h, 28f. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the disclosures of Shikano and Nakamura in the manner set forth above.
Regarding claim 13, Shikano discloses the method of claim 11 as above, but does not explicitly disclose wherein:
forming the first conductive post (42hp) in the first hole (OPh) includes providing a first conductive bond precursor in the first hole, heating the first conductive bond precursor to melt the first conductive bond precursor, dipping the first metal pin (28h) in the molten first conductive bond precursor to arrange the molten first conductive bond precursor between the first metal pin and the conductive circuit pattern and between the first pin side surface of the first metal pin and the first side surface of the first hole, and cooling the first conductive bond precursor to change the first conductive bond precursor into the first conductive bonding member (11h), and
forming the second conductive post (42hp) in the second hole (OPh) includes providing a second conductive bond precursor in the second hole. heating the second conductive bond precursor to melt the second conductive bond precursor, dipping the second metal pin in the molten second conductive bond precursor to arrange the molten second conductive bond precursor between the second metal pin (28f) and the power semiconductor device and between the second pin side surface of the second metal pin and the second side surface of the second hole, and cooling the second conductive bond precursor to change the second conductive bond precursor into the second conductive bonding member (11f).
In comparison to claim 12, claim 13 simply recites the application of the solder paste / reflow process in reverse, that is, heating prior to placing the pins. It is prima facie obvious, however, to merely change the order of process steps in the absence of new or unexpected results (see Ex part Rubin, 128 USPQ 440 (Bd. App. 1959); In re Burhans, 154 F.2d 690 (CCPA 1946); MPEP 2144.04(IV)(C)). Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the disclosures of Shikano and Nakamura in the manner set forth above in connection with claim 12, while merely reversing the order of the pin / post placement (into the solder paste) step with the heating / reflow step, there being no apparent reason on the present record to expecting obtaining new or unexpected results in doing so.
Regarding claim 15, Shikano in view of Nakamura is relied on for the method of claim 12 as above, and this combination of references further discloses wherein the first conductive bond precursor is heated using heat produced in the first metal pin (28h), and the second conductive bond precursor is heated using heat produced in the second metal pin (28f). Specifically, Nakamura discloses a similar power semiconductor manufacturing method including joining conductive posts 18a, 18b, to semiconductor chips using a solid state diffusion joining material (including silver nanoparticles) (see FIGS. 2 and 5C, and paras. [0043] – [0044]). As disclosed therein, “[f]urther, in a state wherein the first conductive posts 18a and second conductive posts 18b fixed in the printed substrate 14 are brought into contact on the solid state diffusion joining material, the first conductive posts 18a and second conductive posts 18b are electrically joined by heating and pressurizing to the electrode pads 11a and 11b across the solid state diffusion joining material.” (Note, claim 15 recites “heat produced in the first / second metal pins”; based on the broadest reasonable interpretation (MPEP 2111), heating the electrode pads 11a and 11b would result in conductive heat transfer to the posts 18a and 18b, thereby “producing heat” in the posts, especially as applicable to heating the diffusion joining material (21) along sides of the pins (18a, 18b) distal from the surface of the electrode pads 11a and 11b).
As noted above, it is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(A).) Because both Shikano and Nakamura disclose similar power semiconductor devices using similar placed conductive pins / posts, it would have been readily predictable to person having ordinary skill in the art to have combined the particular type of solder paste and reflow process of Nakamura, wherein the pins (28h, 28f) are used to provide the heat, with the disclosure of Shikano such that Shikano would have used the same paste / reflow / heating process for its pins (28h, 28f). Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the disclosures of Shikano and Nakamura in the manner set forth above.
Allowable Subject Matter
Claim 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (i.e., independent claim 11).
The following is a statement of reasons for the indication of allowable subject matter: No prior art reference of record, found by the examiner herein during the search and consideration of the present application, fairly could be said to disclose, teach, or suggest a method that includes applying a bonding precursor to either the first or second metal pin (28h, 28f), prior to insertion of the first or second metal pin into the first or second hole (OPh, OPf), respectively. Moreover, a review of the PCT search previously conducted in connection with the parent application (PCT/JP2020/022335, published as WO 2021/245915 A1) indicated that no prejudicial prior art exists of record that could be said to fairly disclose, teach, or suggest the aforementioned limitations in claim 14. Still further, review of prior art searches from other jurisdictions (DE, JP, CN) did not reveal any other relevant prior art. Accordingly, based on the current record, claim 14 would appear at present to recite allowable subject matter, if re-written in independent form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Nakamura, Yoko, US 2021/0020604 A1, disclosing a semiconductor device including: an insulating circuit substrate including a principal surface and a back surface; semiconductor chips each including an electrode on a principal surface and having a back surface on an opposite side to the principal surface, the back surface being fixed to the principal surface of the insulating circuit substrate; a wiring substrate facing the principal surface side of the insulating circuit substrate, separated from the semiconductor chip; a conductive post fixed to the electrode of the semiconductor chips and the wiring substrate; and a resin sealing body sealing the insulating circuit substrate (see, e.g., FIG. 15).
PNG
media_image2.png
191
429
media_image2.png
Greyscale
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Fortin whose telephone number is 703-756-5649. The examiner can normally be reached on Monday – Friday from 8:30 AM to 12:30 PM and from 2:30 PM to 6:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo, can be reached at telephone number 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center system. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated-interview-request-air-form.
/R.T.F./
Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897